D/M Note Block Diagram -- Intel Huron River ULV

Transcription

1 P STK UP L LYER : TOP LYER : SGN /M Note lock iagram -- Intel Huron River ULV POWER / V_PU, V_PU, V Page LYER : IN LYER : IN LYER : SV LYER : IN LYER : SGN LYER : OT R SO-IMM (ST) Page R SO-IMM (RVS) Page Intel Huron River Sandy ridge mmxmm, G ore Watt FI Page,,, X MI Environment temperature Thermal Sensor harger temperature Thermal Sensor R Thermal Sensor Page Page Page REGULTOR (R).V_SUS, 0.V_R_VTT REGULTOR.0V&.V REGULTOR VS PU ore harger Page Page Page Page Page RUN POWER SW/ischarge V_SUS, V_S, V_S V, V Page US ard Reader Realtek RTS0 Page in Socket S/SH/SX/MM Page HP/Mic udio Jack Page Internal MI H OE X0-Z Page Page Internal SPK Page SPI Flash (M) Page H udio ougar Point HM mmxmm, G PH.Watt PI-e/US PI-e/US PI-e ST Mini PIe Slot Mini PIe Slot 0/00/G Ethernet R-L-R." H / SS Module (Option) WLN Module Page Page Page Page WWN Module Page Page RJ- SIM ard Page LVS RG Page." H (x) L RT Page Page.KHz LP US Page,,, 0,, HMI HMI Page SPI Flash (K) Page IT Page TPM (for M-note) Page US amera onn amera Module Page Page ccelerometer (PS) Page Int. K T/P attery harger Page Page Page Page US luetooth Page US US PORT X Page 0 US Fingerprint(for M-note) Page Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev System lock iagram Monday, January, 0 ate: Sheet of

2 Table of ontents PGE ESRIPTION 0 LOK IGRM(UM) 0 FRONT PGE 0-0 Sandy ridge 0- ougar Point-PH - RIII SO-IMM L/MER RT/HMI ONN LN-RTLE-V-GR UIO (X0-Z, SPK) ST 0 US X ard Reader-RTS0 WLN WWN K/TP/FP T/G-SENSOR/TPM FN/Thermal SW/LE/RFI_EEPROM K IT/ Screw Hole/EMI 0 Power lock iagram POWER_V/V (RT0MGQW) POWER_R (TPS) POWER_.0V&.V (OZ) POWER_VS (OZ) POWER_V_ORE(ISL) POWER_harger (ISL) POWER_ischarge Power On Sequence OM Matrix Table 0 Schematic Value escript E REOR V Power E REOR V POWER PLNE VOLTGE 0V~0V V_RT.0V~.V VPU.V VPU V V V LNV.V V_S V V_S.V VSUS V VSUS.V.VSUS.V 0.V_R_VTT 0.V V V V.V V_GFX VS 0.V~0.V.V.V.0V.0V V_ORE LV.V V_H V V_H V T-V 0V~V PGE,,,,,,,,,,,,,,0,,,,,,,,,,,,,,,,,,,0,,,,,0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Power States MIN POWER RT IT/ POWER LRGE POWER LN POWER / POWER I SOURE PH SUS POWER R SOIMM POWER SLP_S# TRL POWER SLP_S# TRL POWER LVS,NVM POWER L Power O Power H Power MIN TTERY ESRIPTION Sys Management,PH Resume Well, US,WLN,WiMX POWER SLP_S# TRL POWER SLP_S# TRL POWER R SOIMM REFERENE POWER VG ORE POWER Sandy ridge Power Sandy ridge VTT POWER/PH ORE POWER PU ORE POWER ONTROL SIGNL VV_EN VV_EN VV_EN LN_ON S_ON S_ON SUSON SUSON SUSON MINON MINON MINON MINON MINON MINON MINON VRON ENV O_V_ON MINON# HG_PTT TIVE IN S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0 S0 S0 S0 S0 S0 S0 S0 S0 S0 S0 S0~S 0.V_PU.V,,, R.V Rails PS_SNTRL S0 Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev System lock iagram ate: Monday, January, 0 Sheet of

3 () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN ep_omp INT_eP_HP_Q U M MI_RX#[0] P MI_RX#[] P MI_RX#[] P0 MI_RX#[] N MI_RX[0] P MI_RX[] P MI_RX[] P MI_RX[] K MI_TX#[0] M MI_TX#[] N MI_TX#[] R MI_TX#[] K MI_TX[0] M MI_TX[] P MI_TX[] T MI_TX[] U FI0_TX#[0] W FI0_TX#[] W FI0_TX#[] FI0_TX#[] W FI_TX#[0] V FI_TX#[] Y FI_TX#[] FI_TX#[] U FI0_TX[0] W0 FI0_TX[] W FI0_TX[] FI0_TX[] W FI_TX[0] T FI_TX[] FI_TX[] FI_TX[] FI0_FSYN FI_FSYN U FI_INT 0 FI0_LSYN G FI_LSYN F ep_ompio ep_iompo G ep_hp G ep_ux# F ep_ux ep_tx[0] ep_tx[] E0 ep_tx[] E ep_tx[] ep_tx#[0] ep_tx#[] E ep_tx#[] E ep_tx#[] I,SN_G,P0 MI Intel(R) FI P PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] G G G H J 0 G H E K K K F H F K G F H K F F J H M0 F0 J F E G K G E K G K0 G0 K Sandy ridge Processor (MI,PEG,FI) Sandy ridge Processor (LK,MIS,JTG) 0 PEG_OMP PEG_OMP connect to PIN G&G W:mils/S:mils/L: 00mils. PEG_OMP connect to PIN G W:mils/S:mils/L: 00mils. (,,,,,,) PU RESET# PLTRST# () (,) (0) PRO_SELET# SN_IV# N. at SN ES # 0.v R U Placement close to E. N (0,) (0) GN IN () E_PEI H_PROHOT# PM_THRMTRIP# OUT LVG0GW PM_SYN H_PWRGOO V.0V PU_PLTRST# V_S *.K/F_ SM_RMPWROK Processor Input. V_S R _ R0 R E-SIT- R R R 0.U/0V/XR_ TP TP 0.U/0V/XR_./F_ *short_ E-SIT- *short_ *short_ 0K/F_ R _ R _ SKTO# TP_TERR# H_PEI H_PROHOT#_R PM_THRMTRIP#_R PM_SYN_R H_PWRGOO_R PM_RM_PWRG_R PU_PLTRST#_R R *0/F_.V_PU F E U PRO_SELET# PRO_ETET# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# I,SN_G,P0 MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] (,) LK LK# PLL_REF_LK PLL_REF_LK# LK_ITP LK_ITP# PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] J H G G N N T0 F E G R_RMRST# LK_PLL_SSLKP_R LK_PLL_SSLKN_R LK_ITP LK_ITP# PU_RMRST# SM_ROMP_0 SM_ROMP_ SM_ROMP_ SM_ROMP[0] W:0mils/S:0mils/L: 00mils, SM_ROMP[] W:0mils/S:0mils/L: 00mils, SM_ROMP[] W:mils/S:0mils/L: 00mils, N XP_PRY# TP N XP_PREQ# TP PU XP L L J M0 L K G E E G G H0 J J.VSUS XP_TLK XP_TMS XP_TRST# XP_TI XP_TO XP_RST# XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM LK_PU_LKP () LK_PU_LKN () R R R0 R TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP T 0/F_./F_ 00/F_ T R R *K/F_ V XP_RST# () R RM RESET R R K/F_ K/F_ R *0_ K_ K_.0V PU_RMRST# ep_omp connect to PIN F W:mils/S:mils/L: 00mils. ep_omp connect to PIN W:mils/S:mils/L: 00mils. (,) SYS_PWROK () PM_RM_PWRG R *short_ E-SIT- R *.K/F_ U PM_RM_PWRG_Q HG0 R0 *_ R 00/F_ R 0/F_ PM_RM_PWRG_R () RMRST_NTRL_PH R *short_ 0.0U/0V/XR_ Q N00 R0.K/F_ PM_RM_PWRG_R R *K/F_ Q *N00K MINON# ().VSUS (,,,,,).0V (,,,,,,,).V_PU (,,,) V_S (,,,0,,,,,) V (,,,0,,,,,,,,,,,,,,,,,,,,,,) P & PEG ompensation Processor pull-up (PU).0V R 0K/F_ INT_eP_HP_Q.0V.0V R0./F_ ep_omp ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms H_PROHOT# XP_TO XP_TMS XP_TI XP_PREQ# XP_TLK XP_TRST# R _ R /F_ R /F_ R /F_ R */F_ R /F_ R /F_.0V R./F_ PEG_OMP PEG_IOMPI and ROMPO signals should be routed within 00 mils typical impedance = mohms PEG_IOMPO signals should be routed within 00 mils typical impedance =. mohms Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Number Rev Size ocument ustom SN / (PIE&MI&FI) Monday, January, 0 ate: Sheet of

4 0 Sandy ridge Processor (R) () M Q[:0] () M S#0 () M S# () M S# () M S# () M RS# () M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U G S_Q[0] J S_Q[] P S_Q[] L S_Q[] J0 S_Q[] J S_Q[] L S_Q[] L S_Q[] R S_Q[] P S_Q[] U S_Q[0] V S_Q[] R S_Q[] P S_Q[] T S_Q[] U S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] Y S_Q[] V S_Q[] R S_Q[] Y S_Q[] R S_Q[] S_Q[] U S_Q[] S_Q[0] S_Q[] S_Q[] R S_Q[] W S_Q[] S_Q[] S_Q[] R S_Q[] T S_Q[] Y S_Q[] S_Q[0] V S_Q[] S_Q[] Y S_Q[] S_Q[] U S_Q[] S_Q[] S_Q[] S_Q[] V S_Q[] P0 S_Q[0] P S_Q[] V S_Q[] T S_Q[] P S_Q[] P S_Q[] N S_Q[] N S_Q[] G S_Q[] G S_Q[] N S_Q[0] N S_Q[] G S_Q[] K S_Q[] S_S[0] F S_S[] S_S[] E S_S# S_RS# T S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] U V Y T0 U0 0 Y0 L R V T V Y T K J R0 Y U W V T K G E T U T Y V E 0 0 W Y U M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 () M LKN0 () M KE0 () M LKP () M LKN () M KE () M S#0 () M S# () M OT0 () M OT () M QSN[:0] () M QSP[:0] () M [:0] () () M Q[:0] () M S#0 () M S# () M S# () M S# () M RS# () M WE# U M Q0 L M Q S_Q[0] L M Q S_Q[] N M Q S_Q[] R M Q S_Q[] K M Q S_Q[] K M Q S_Q[] N M Q S_Q[] R M Q S_Q[] U M Q S_Q[] T M Q0 S_Q[] V M Q S_Q[0] M Q S_Q[] U M Q S_Q[] R M Q S_Q[] Y M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] M Q S_Q[] F M Q0 S_Q[] F M Q S_Q[0] 0 M Q S_Q[] M Q S_Q[] E M Q S_Q[] F M Q S_Q[] E M Q S_Q[] E M Q S_Q[] E M Q S_Q[] E M Q S_Q[] G M Q0 S_Q[] G M Q S_Q[0] F M Q S_Q[] 0 M Q S_Q[] F M Q S_Q[] M Q S_Q[] F M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] E M Q0 S_Q[] F M Q S_Q[0] E M Q S_Q[] M Q S_Q[] Y0 M Q S_Q[] E M Q S_Q[] G M Q S_Q[] M Q S_Q[] W M Q S_Q[] W M Q S_Q[] U M Q0 S_Q[] N M Q S_Q[0] N M Q S_Q[] U M Q S_Q[] U M Q S_Q[] N M Q S_Q[] R M Q S_Q[] K M Q S_Q[] L M Q S_Q[] G M Q S_Q[] G M Q0 S_Q[] M0 M Q S_Q[0] L M Q S_Q[] F M Q S_Q[] H0 S_Q[] G S_S[0] S_S[] T S_S[] V S_S# F0 S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] Y R F E E T G L V G G T0 K M V E E R K F E U0 0 V0 G0 E0 E T V T U M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 () M LKN0 () M KE0 () M LKP () M LKN () M KE () M S#0 () M S# () M OT0 () M OT () M QSN[:0] () M QSP[:0] () M [:0] () I,SN_G,P0 I,SN_G,P0 Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom SN / (R I/F) ate: Monday, January, 0 Sheet of

5 V_ORE PU ore Power SN:. U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ *U/.V/XR_ SVI LK Layout note: need routing together and LERT need between LK and T. H_PU_SVI_LK Sandy ridge Processor (POWER) E E E E E E F F F F F F F F G H H H H H H H H H H0 J J J J J J J J J J0 J K K K K K K K K K L L L L L0 N N0 N N UF V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] I,SN_G,P0 Place PU resistor close to VR R./F_ ORE SUPPLY POWER.0V PEG N R SENSE LINES SVI QUIET RILS VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO0 VIO VIO_SEL VPQE[] VPQE[] VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSS_SENSE_VIO F G G0 G J J J J J K0 K L L L L0 L L L L M M M M M N0 N N N 0 E E F F F0 G G G G0 G J J W W M N F G N N R *short_ H_PU_SVI_T R *short_ H_PU_SVILRT# R _ R *short_ VR_SVI_T () VR_SVI_LK () VR_SVI_LERT# () E-SIT- E-SIT- E-SIT- H_PU_SVILRT# H_PU_SVI_LK H_PU_SVI_T SVI T Place PU resistor close to PU 0uF locate power side V U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ V_ORE.0V.0V.0V.V_SUS?(PG p) R R0 R R R 0 0 TP0 0.0/F_ U/0V/XR_ 00/F_ 00/F_ 0/F_ 0/F_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ R 0/F_.0V R 0/F_ V_SENSE () VSS_SENSE () VP_SENSE () () () Place PU resistor close to VR V_GFX V_GFX V_XG_SENSE VSS_XG_SENSE.V VS SN: U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ SVI LERT VS_VI0 VS_SEL Place PU resistor close to PU.0V Sandy ridge Processor (GRPHI POWER) 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ *U/.V/XR_ *U/.V/XR_ R R U/.V/XR_ U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ 0/F_ 0/F_ 0 0 E N P P P0 P P P P P P T T T T U V V V0 V V V V V V V W0 W W W W W W Y Y F G L L N N0 N P P0 R R R U V V V V W0 R _ UG VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG_SENSE VSSXG_SENSE VPLL[] VPLL[] VPLL[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[0] VS[] VS[] VS[] VS[] VS[] VS[] I,SN_G,P0 R R R R GRPHIS *K/F_ 0K/F_ *K/F_ K/F_ POWER SENSE LINES.V RIL S RIL SENSE LINES R -.V RILS QUIET RILS SM_VREF VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ_SENSE VSS_SENSE_VQ VS_SENSE VS_VI[0] VS_VI[].0V Y J J J J0 L0 L L L M M M0 N0 N N R R R0 R R R R0 V W 0 G M N U0 R R R VR_REF_PU R VS_VI0 VS_SEL E-V-0 R 00K/F_ R MIN.V_PU VS V_ORE (,,,) V_GFX (,,) VS (,).0V (,,,,,,,).V_PU (,,,).V (,,,) R_VTTREF (,,) Monday, January, 0 ate: Sheet of Note: VR_REF_PU should have 0 mil trace width 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ 0.0/F_ Q0 N00 U/0V/XR_ */F_ */F_ 00/F_ *0_ R_VTTREF (,,) MIN ().V_PU.V_PU SN_IV# N. at SN ES # 0.v VUS_SENSE () VS_SEL () If.V_PU will be implemented, have to change the two divided resistor as 00-ohm % Quanta omputer Inc. 0 PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom SN / (POWER)

6 UH Sandy ridge Processor (GN) UI Sandy ridge Processor (RESERVE, FG) UE E E F F F F F F0 F F F F F F F G0 G G G G G G H H J J J0 J J J0 J J J J J J K K L0 L L L L L L L L0 L L L M M0 M M M0 M VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] M M M M M M N N N N N N N0 N N N0 N P0 P P P R R R R R R R T T T T T T T U U U U U U V V V V V0 V V W W W W Y Y Y0 Y Y Y Y Y Y Y Y 0 E G G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] VSS[] VSS[] 0 VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] 0 VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[] E VSS[] E0 VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F0 VSS[] F VSS[0] G VSS[] G VSS[] G VSS[] G VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L0 VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[0] I,SN_G,P0 VSS NTF Processor Strapping FG (PI-E Static x Lane Reversal) VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[0] N VSS[] N0 VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R0 VSS[] R VSS[] R VSS[0] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[0] V0 VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[00] Y VSS[0] Y VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ G VSS_NTF_ G VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E Normal Operation V_ORE R */F_ V_VL_SENSE VSS_VL_SENSE R */F_ V_ORE R */F_ VXG_VL_SENSE VSSXG_VL_SENSE R0 */F_ The FG signals have a default value of '' if not terminated on the board. 0 Lane Reversed T T T T T T FG FG FG FG FG FG V_VL_SENSE VSS_VL_SENSE VXG_VL_SENSE H VSSXG_VL_SENSE K V_IE_SENSE PU_RSV PU_RSV FG FG R R 0 FG[0] FG[] FG[] FG[] FG[] FG[] FG[] H FG[] FG[] H FG[] K FG[0] K FG[] F FG[] G FG[] L FG[] F FG[] FG[] L FG[] H V_VL_SENSE K VSS_VL_SENSE F VXG_VL_SENSE VSSXG_VL_SENSE V_IE_SENSE H RSV K RSV RSV V RSV T RSV0 RSV RSV Y RSV RSV Y RSV U RSV U RSV RSV RSV RSV0 RSV G RSV E RSV G RSV E RSV F RSV E RSV I,SN_G,P0 *K/F_ *K/F_ FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG FG FG FG R0 R R R RESERVE _TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_E E _TEST_E E _TEST_G G _TEST_G G _TEST_G G _TEST_G G _TEST_G G _TEST_E E _TEST_G G _TEST_E E _TEST_ *K/F_ *K/F_ *K/F_ *K/F_ RSV E RSV G RSV0 N RSV L RSV L RSV L RSV M RSV M RSV U RSV W RSV P RSV T RSV0 K RSV H RSV G RSV M RSV M RSV N0 I,SN_G,P0 FG (PI-E Static x Lane Reversal) Normal Operation Lane Reversed FG (P Presence Strap) isable; No physical P attached to ep Enable; n ext P device is connected to ep Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom SN / (GN) ate: Monday, January, 0 Sheet of

7 () () SUS_PWR_K_R E_PWROK_R MI_OMP MI_RIS SUSK#_R XP_RST# PIE_WKE# () XP_RST# K SYS_RESET# WKE# PIE_WKE# (,) E-SIT- (V) SYS_PWROK R *short_ SYS_PWROK_R P PI_LKRUN# PI_LKRUN# (,) R *0_ SYS_PWROK LKRUN# / GPIO N (VS) () EPWROK R0 *short_ E_PWROK_R L PWROK SUS_STT# / GPIO G LPP# () PM_RM_PWRG () () () IH_RSMRST# SUS_PWR_K NSWON# () () () () () () () () () () () () () () () () _PRESENT.0V MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R0 R0 R R R R R E-SIT-./F_ 0/F_ *0_ *short_ *short_ *short_ *short_ PWROK_R PM_RM_PWRG RSMRST# SUS_PWR_K_R NSWON#_R _PRESENT_R PM_TLOW# PM_RI# ougar Point (MI,FI,PM) U0 E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H L0 K E0 H0 E0 0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# PWROK RMPWROK RSMRST# (VS) (SW) (VS) MI System Power Management FI SUSWRN#/SUSPWRNK/GPIO0 PWRTN# PRESENT / GPIO TLOW# / GPIO RI# FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SWVRMEN PWROK (VS) SUSLK / GPIO (VS) SLP_S# / GPIO SLP_S# SLP_S# SLP_# SLP_SUS# PMSYNH (VS) SLP_LN# / GPIO J Y E H J G0 G G F G E G J0 H W V 0 V 0 E R0 SWVREN E-SIT- PH_SUSLK_L E-SIT- SLP_LN# *short_ RSMRST# PM_SYN () TP FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_INT () FI_FSYN0 () FI_FSYN () FI_LSYN0 () FI_LSYN () TP TP0 PM_SLP_S# () SIO_SLP_S# () TP () () () () () () () () () () () () () () () () () () () () R R R RT ON RT_G_ON RT_R_ON RTLK RTT HSYN VSYN INT_LVS_LON INT_ISP_ON INT_PST_PWM INT_EILK INT_EIT V INT_TXLLKN INT_TXLLKP INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP 0/F_ 0/F_ 0/F_ R R R R R TP0 L_TRL_LK L_TRL_T LVS_IG LVS_VG HSYN_R VSYN_R _IREF ougar Point (LVS,I) J M P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F N P T T M0 M M T T U0 L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN ougarpoint_rp0 LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y M M T T H F E F E J G P_HP_Q P_LNE0_N P_LNE0_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P () HMI_HP INT_HMI_SL () INT_HMI_S () 0 Layout note: coupling capacitors of P are placed on near connector R00 00K_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ V Q MEN00E HMI_TX- () HMI_TX () HMI_TX- () HMI_TX () HMI_TX0- () HMI_TX0 () HMI_LK- () HMI_LK () 0 P_HP_Q INT. HMI RSMRST# N 0 H F G0 G P K R R *short_ *short_ TP R.K_.K_.K/F_ /F_ /F_ K/F_ ougarpoint_rp0 RV *TVM0G0M00R(V,p)_ E-V-0 PH Pull-high/low(LG) V_S PM_RI# R 0K_ PM_TLOW# R.K_ PIE_WKE# R 0K_ System PWR_OK(LG) V_S 0 0.U/0V/XR_ SLP_LN# R0 SUS_PWR_K_R R _PRESENT_R R PM_RM_PWRG R 0K_ 0K_ 0K_ 00/F_ (,) SYS_PWROK SYS_PWROK U TSH0FU ELY_VR_PWRGOO () EPWROK R *00K_ V XP_RST# R 0K_ PI_LKRUN# RSMRST# SYS_PWROK R R R.K_ 0K_ 0K_ V_RT R 0K_ SWVREN R00 On ie SW VR Enable High = Enable (efault) Low = isable *0K_.0V (,,,,,,,) V_RT (,,) V_S (,,,0,,,,,) V (,,,0,,,,,,,,,,,,,,,,,,,,,,) V (,,,,,,,,) Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev PH / (MI/FI/VIEO) ate: Sheet of Monday, January, 0

8 V_RT () Z_SPKR () V V_S VPU R Z_SIN0 R0 R0 R TP TP0 TP TP TP M_ *0K_ *0K_ *0K_ RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_LK Z_SYN_R SPKR Z_RST# Z_SOUT GPIO GPIO PH_JTG_TK PH_JTG_TMS PH_JTG_TI PH_JTG_TO SPI_LK_R SPI_S0#_R PH_SPI_S# SPI_SI_R SPI_SO_R ougar Point (H,JTG,ST) U0 0 RTX 0 RTX 0 RTRST# G SRTRST# K INTRUER# INTVRMEN N H_LK L H_SYN T0 SPKR RT K H_RST# E H_SIN0 G H_SIN H_SIN H_SIN H_SO (V) H_OK_EN# / GPIO (VS) N H_OK_RST# / GPIO J JTG_TK H JTG_TMS K JTG_TI H JTG_TO T SPI_LK Y SPI_S0# T SPI_S# V SPI_MOSI U SPI_MISO IH JTG SPI FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# E LRQ# / GPIO K (V) SERIRQ V ST0RXN M ST0RXP M ST0TXN P ST0TXP P ST LP ST G STRXN M0 STRXP M STTXN P STTXP P0 STRXN STRXP STTXN H STTXP H STRXN STRXP 0 STTXN F STTXP F STRXN Y STRXP Y STTXN STTXP STRXN Y STRXP Y STTXN STTXP STIOMPO Y STIOMPI Y0 STROMPO STOMPI STRIS H STLE# P (V) ST0GP / GPIO V (V) STGP / GPIO P SERIRQ ST_OMP ST_OMP ST_RIS T_ET# S_IT0 R R0 R R R0 R LP_0 (,,) LP_ (,,) LP_ (,,) LP_ (,,) LP_FRME# (,,) LP_RQ#0 () L_K_OFF ().K_ SERIRQ (,,) ST_RXN0 () ST_RXP0 () ST_TXN0 () ST_TXP0 ()./F_./F_ 0/F_ 0K_ 0K_ V V.0V V ST H/SS TP T_ET# ().0V (,,,,,,,).V (,,,) V_RT (,,) VPU (,,,0,,,,,,,) V (,,,0,,,,,,,,,,,,,,,,,,,,,,) V (,,,,,,,,,) E-SIT- V RT ircuitry(rt) VPU V_RT_0 T RT_ON R itpm Function Enable isable R R *short_ V_RT_ V_RT_ SPI_SI RT lock.khz 0mils V_RT RT Power trace width 0mils. itpm ENLE/ISLE *K_ K_ R K N 0 P/0V/NPO_ E-SIT- P/0V/NPO_ T V R R 0K/F_ RT_RST# Y.KHZ 0K/F_ RT_X R0 0M_ RT_X 0 U/.V/XR_ U/.V/XR_ U/.V/XR_ R *0_ SRT_RST# For PH Mbit (M yte), SPI 0 RT_RST# J *SOLERJUMPER- SRT_RST# J *SOLERJUMPER- V PH Strap Table SPKR GPIO GNT# / GPIO F_TVS Pin Name Strap description Sampled onfiguration GNT# / GPIO GNT# / GPIO No reboot mode setting Top-lock Swap Override oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] ESI strap (Server only) MI Termination voltage PWROK PWROK PWROK PWROK PWROK PWROK 0 efault (weak pull-down 0K) = Setting to No-Reboot mode 0 "top-block swap" mode = efault (weak pull-up 0K) INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up H_SO ifferent from alpella ifferent from alpella Flash escriptor Security Only for Interposer ougarpoint_rp0 PWROK 0 effective(efault: weak pull down) = Override GNT# 0 GNT0# 0 Should not be pull-down (weak pull-up 0K) weak pull-down 0kohm if default boot destination is SPI, no external pull-up/-down resistors on the board are necessary oot Location SPI LP V SPKR R R PH_INVRMEN Z_SOUT [Need external pull-down for LP IOS] USE GPIO PIN () PRO_SELET# ircuit R R R *K_ 0K_ R R.V V PI_GNT# () ios request, for can't boot apella /. 0K_ *K_ *K_ *K_ *K_ R R V_RT V_S S_IT0 S_IT ().K_ K_ N. at PT ES 0. F_TVS (0) H us(lg) Z_SYN R SPI_S0#_R R SPI_LK_R R SPI_SI_R R SPI_SO_R R Q N00 K/F_ E-SIT- Z_SYN_R P/0V/NPO_ *short_ SPI_S0# *short_ SPI_LK *short_ SPI_SI *short_ SPI_SO P/0V/NPO_ () Z_ITLK_UIO () Z_SYN_UIO () Z_RST#_UIO () Z_SOUT_UIO R.K_ U E# V SK SI SO HOL# WP# VSS WQVSSIG R _ R _ R0 _ R _ *0P/0V/OG_ Z_LK Z_SYN Z_RST# R.K_ 0 0.U/0V/XR_ Z_SOUT H_SYN On-ie PLL VR Voltage Select RSMRST 0 = Support by.v (weak pull-down) = Support by.v V_S R0 K_ Z_SYN_R V Place near the audio codec GPIO GPIO SWVREN ifferent from alpella On-die PLL Voltage Regulator 0: disable : enable RSMRST# 0 isable = Enable (efault) (0) GPIO GPIO R R *K_ K_ V_S PLL_OVR_EN (0) Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev PH / (ST/H/SPI) ate: Monday, January, 0 Sheet of

9 () () () PI/USO# Pull-up(LG) PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# OK_I0 PI_REQ# OK_I US_O# US_O# US_O# US_O# () PLK_EUG LK_LP_TPM PLK_ () () V V_S R R R R0 RP 0 RP 0 S_IT TP PI_GNT# SIO_EXT_WKE# LK_PI_F *P/0V/NPO_ *0P/0V/OG_.K_.K_.K_.K_ 0K_0PR_ 0K_0PR_ OK_I INTH# PI_REQ# PI_REQ# US_O# US_O0# US_O# US_O# R _ R _ R _ R _ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_REQ# PI_REQ# PI_REQ# S_IT PWM_SELET# PI_GNT# OK_I0 OK_I OK_I INTH# PI_PLTRST# PLK_EUG_ PLK_ V ougar Point-M (PI,US,NVRM) PLK_EUG_ LK_LP_TPM_ PLK LK_PI_F_ G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 U0E TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 PIRQ# PIRQ# PIRQ# PIRQ# RSV PI REQ# / GPIO0 (V) REQ# / GPIO (V) REQ# / GPIO (V) GNT# / GPIO (V) GNT# / GPIO (V) GNT# / GPIO (V) PIRQE# / GPIO (V) PIRQF# / GPIO (V) PIRQG# / GPIO (V) PIRQH# / GPIO (V) PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI ougarpoint_rp0 US (VS) O0# / GPIO (VS) O# / GPIO0 (VS) O# / GPIO (VS) O# / GPIO (VS) O# / GPIO (VS) O# / GPIO (VS) O# / GPIO0 (VS) O# / GPIO RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E K0 L NV_ROMP US_IS US_O0# US_O# US_O# US_O# US_O# US_O# US_O# US_O# R USP0- (0) USP0 (0) USP- (0) USP (0) USP- () USP () USP- () USP () USP- () USP () USP- (0) USP (0) USP0- () USP0 () USP- () USP () R./F_ *./F_ US0 US_O0_# (0) US_O_# (0) TP US(UO) amera WLN WWN US (Wire) Finger Printer luetooth WLN ard Reader WWN EHI EHI LN () () () () () () () () () () () () () () () () PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN WLN () () ard Reader () () WWN LN () () () () Reserved PIE_LKREQ_WLN# () () () () LK_PIE_WLNN LK_PIE_WLNP LK_PIE_R# LK_PIE_R PIE_LKREQ_R# LK_PIE_WNN LK_PIE_WNP PIE_REQ_WWN# LK_PIE_LNN LK_PIE_LNP PIE_LKREQ_LN# TP TP TP TP 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ TP TP TP TP TP PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ J G PIE_TXN_LN_U PIE_TXP_LN_V PIELKRQ0# PIE_LKREQ_WLN# PIE_LKREQ_R# PIE_REQ_WWN# LK_PIE_REVN LK_PIE_REVP LK_PIE_REQ# PIE_LKREQ_LN# LK_PEG_REQ# PIELKRQ# PIELKRQ# LK_PIE_XPN LK_PIE_XPP ougar Point-M (PI-E,SMUS,LK) G J V U E F Y G J V U F E Y G H Y G0 J0 Y0 0 E W Y Y0 Y J M V0 Y Y Y Y L V V L 0 E V0 V T V V K K K U0 PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P (VS) LKOUT_PIEN LKOUT_PIEP (V) LKOUT_PIEN LKOUT_PIEP (V) LKOUT_PIEN LKOUT_PIEP (VS) LKOUT_PIEN LKOUT_PIEP (VS) LKOUT_PIEN LKOUT_PIEP (VS) (VS) PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (VS) LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (VS) LKOUT_ITPXP_N LKOUT_ITPXP_P ougarpoint_rp0 LOKS SMUS ontroller 0 (VS) SMLERT# SMLERT# / GPIO E (VS) (VS) SMLLERT# / PHHOT# / GPIO (VS) SMLLK / GPIO (VS) SMLT / GPIO Link FLEX LOKS SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T L_LK L_T L_RST# (VS) PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN_GN_N LKIN_GN_P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP (V) LKOUTFLEX0 / GPIO (V) LKOUTFLEX / GPIO (V) LKOUTFLEX / GPIO (V) LKOUTFLEX / GPIO H G E M M T P0 M0 V U M M F E J0 G0 G E K K K H V V Y K F H K SM_PH_LK SM_PH_T RMRST_NTRL_PH SM_ME0_LK SM_ME0_T SMLLERT#_R SM_ME_LK SM_ME_T L_LK_R L_T_R L_RST#_R LK_PEG_REQ# LK_UF_PIE_GPLL# LK_UF_PIE_GPLL LK_UF_LK_N LK_UF_LK_P LK_UF_REFLK# LK_UF_REFLK LK_UF_REFSSLK# LK_UF_REFSSLK LK_PH_M LK_PI_F XTL_IN XTL_OUT XLK_ROMP LK_FLEX0 LK_FLEX LK_FLEX LK_FLEX R 0./F_ RMRST_NTRL_PH () TP TP TP TP TP TP LK_PU_LKN () LK_PU_LKP () R M_.0V TP TP TP TP P/0V/NPO_ Y MHz P/0V/NPO_ PLTRST#(LG) PI_PLTRST# E-SIT- R *short_ PLTRST# V_S *0.U/0V/XR_ PLTRST# U *TSH0FU R 00K_ PLTRST# (,,,,,,) SMus/Pull-up(LG) N00K (,) MLK_THRM SM_ME_LK Q V (,) MT_THRM Q N00K SM_PH_T R0.K_ V_S R.K_ SM_ME_T PT_SM (,,,) LK_REQ/Strap Pin(LG) PIE_LKREQ_WLN# R 0K_ PIE_LKREQ_R# R 0K_ PIELKRQ0# R0 0K_ PIE_REQ_WWN# R 0K_ LK_PIE_REQ# R 0K_ LK_PEG_REQ# R0 0K_ PIELKRQ# R 0K_ PIELKRQ# R 0K_ LK_PEG_REQ# R 0K_ PIE_LKREQ_LN# R 0K_ LK_PEG_REQ# R *0K_ LK_UF_LK_N R0 0K_ LK_UF_LK_P R0 0K_ V V_S PIE lock Layout note: PIE_LKREQ_LN# layout adjacent to LK_PEG_REQ# V_S R SMus/Pull-up(LG) K_ R 0K_ R.K_ R.K_ R.K_ R.K_ R 0K_ RMRST_NTRL_PH SMLERT# SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T SMLLERT#_R V_S R00 R R *0K_ *0K_ *0K_ L_LK_R L_T_R L_RST#_R Q N00K V SM_PH_LK R R Q0 N00K.K_.K_ PLK_SM (,,,) LK_UF_PIE_GPLL# R 0K_ LK_UF_PIE_GPLL R 0K_ LK_UF_REFLK# R 0K_ LK_UF_REFLK R0 0K_ LK_UF_REFSSLK# R 0K_ LK_UF_REFSSLK R 0K_ LK_PH_M R 0K_ LOK TERMINTION for FIM V_S (,,,0,,,,,) V (,,,0,,,,,,,,,,,,,,,,,,,,,,) Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev PH / (PIE/US/LK) ate: Sheet of Monday, January, 0

10 () () PLL_OVR_EN () _ON (,) T_ON () SIO_EXT_SMI# () SIO_EXT_SI# GPIO E-SIT- R *short_ GPU_PWROK MOEL_I0 GPIO MST_TT# GPIO _ON T_ON OR_I0 OR_I OR_I OR_I GPIO GPIO PH_GPIO ougar Point (GPIO,VSS_NTF,RSV) U0F GPIO0 T MUSY# / GPIO0 SIO_EXT_SMI# (V) TH / GPIO SIO_EXT_SI# H (V) TH / GPIO EXPRR_PWREN# E (V) TH / GPIO GPIO 0 (V) GPIO GPIO (VS) LN_PHY_PWR_TRL / GPIO GPIO G (VS) GPIO (VS) GPIO U STGP / GPIO TP0 (V) 0 TH0 / GPIO T (V) SLOK / GPIO E (V) GPIO / MEM_LE (VS) E GPIO (SW) P GPIO K (VS) STP_PI# / GPIO K (V) GPIO V (V) STGP / GPIO (V) M STGP / GPIO (V) N SLO / GPIO M (V) STOUT0 / GPIO V (V) STOUT / GPIO V (V) STGP / GPIO (V) GPIO (VS) E E F F VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ ougarpoint_rp0 GPIO NTF PU/MIS TH / GPIO 0 (V) TH / GPIO (V) TH / GPIO0 (V) TH / GPIO 0 (V) 0GTE PEI RIN# PROPWRG THRMTRIP# INIT_V# F_TVS TS_VSS TS_VSS TS_VSS TS_VSS N_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ P U P Y Y0 T Y H K H0 K0 P G G H H J J J J J J E E F F GPIO GPIO WLN_OFF# WWN_OFF# SIO_0GTE SIO_RIN# PH_THRMTRIP# F_TVS R R R R R 0_ *0_ 0K_ *.K/F_ 0K_ F_TVS () V V WLN_OFF# () WWN_OFF# () SIO_0GTE () E_PEI (,) SIO_RIN# () H_PWRGOO () PM_THRMTRIP# () GPIO Pull-up/Pull-down(LG) GPIO GPIO MST_TT# GPIO GPIO R 0K_ E-SIT- _ON R 0K_ GPIO R 0K_ R *short_ GPIO0 R 0K_ SIO_EXT_SI# SIO_EXT_SMI# EXPRR_PWREN# SIO_0GTE R0 R R R 0K_ 0K_ 0K_ 0K_ SIO_RIN# GPIO R R 0K_ 0K_ TP GPU_PWROK R 0K_ TP TP WWN_OFF# WLN_OFF# WWN_OFF# T_ON R R R R R R R R 0K_ 0K_ 0K_ 0K_ *0K_ 0K_ M_ 00K/F_ V_S V 0 V_S (,,,,,,,,) V (,,,,,,,,,,,,,,,,,,,,,,,,,) OR I SETTING oard I For Function V SV SIV SIT SVT SOVP I GPIO I GPIO I GPIO I0 GPIO Model I INTEL M MOEL_I0 0 V R *0K_ MOEL_I0 R0 0K_ TPM physical presence V_S R *0K/F_ R R R R0 *0K_ *0K_ *0K_ *0K_ OR_I0 OR_I OR_I OR_I R R R R 0K_ 0K_ 0K_ 0K_ PH_GPIO Low: efault PH_GPIO R 0K/F_ Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev PH / (GPIO/MIS) ate: Monday, January, 0 Sheet 0 of

11 .0V V_S.0V.0V.0V.0V.0V.0V.0V.0V.0V_VEPW R 0.00/F_0 V_RT VRT<m (0mils) R0 R E-SIT- L *0uH/00m_ E-SIT- R *short_ VPLL_PY_PH E-SIT- R0 U/.V/XR_ E-SIT- R U/.V/XR_ E-SIT- R0 R0 R0 E-SIT- *0_ *short_ 0.U/0V/XR_ U/.V/XR_ *short_ *short_ *short_ 0 U/.V/XR_ *0_ *U/.V/XR_ *short_ U/.V/XR_ 0 0 *0U/.V/XR_.0 (0mils) U/.V/XR_ VLK VPSW m (0mils) PH_VSW VPLL_PY VSUS VFI_VRM 0m (0mils).0V_V PL 0m 0mils).0V_V PL 0m (0mils) VIFFLK VIFFLKN m (0mils) V.0V_SSV m (0mils) VSST 0.U/0V/XR_ V.0M_VSUS VTT_VPPU 0.U/0V/XR_ ougar Point-M (POWER) m (0mils) OUGR POINT (POWER) V V U0J POWER.0V_VUSORE.0V. (0mils) L T V H L L 0 *U/.V/XR_ W W W W W W W Y F PSUSYP VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VSW[] VSW[] VPLL ougarpoint_rp0 0.U/0V/XR_ lock and Miscellaneous F VIO[] F VIFFLKN[] F VIFFLKN[] G VIFFLKN[] G VLK VRTEXT N 0.U/0V/XR_ PRT V VSW_ 0.U/0V/XR_ V_SUS_LKF T V_[] U/.V/XR_ U/.V/XR_ U/.V/XR_ VPLLMI VIO[] PSUS[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VVRM[] VPLL VSS PSST T PSUS[] V PSUS[] V_PRO_IO=m J V_PRO_IO (0mils) 0U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ VRT PU RT ST PI/GPIO/LP US MIS H VIO[] VIO[0] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VIO[] VREF_SUS PSUS[] VSUS_[] VREF VSUS_[] VSUS_[] VSUS_[] VSUS_[] V_[] V_[] V_[] V_[] VIO[] VIO[] VIO[] VIO[] VPLLST VVRM[] VIO[] VIO[] VIO[] VSW[] VSW[] VSW[] VSUSH V_VPUS V_VUG VUPLL V_PH_VREFSUS V_USSUS V_VPSUS V_PH_VREF m (mils) V_VPSUS m (0mils) V_VPORE V.0S_ST V.LN_VPLL VFI_VRM.0V_VIO.0V_VEPW V_RT (,,) V_S (,,,,0,,,,) V (,,,,0,,,,,,,,,,,,,,,,,,,,,) V_S (0,) V (,,,,,,,,).0V (,,,,,,,).VSUS (,,,,,).V (,,,) N P P T T T T V V P T M N N P N0 N P0 P W T J F H H F K F T V T P V 0.U/0V/XR_.0 (0mils) 0m (0mils) V._._H_IO 0.U/0V/XR_ E-SIT- U/.V/XR_ m (0mils) E-SIT- 0.U/0V/XR_ E-SIT- 0.U/0V/XR_ E-SIT- 0 R R R0 R R R E-SIT- R0 0 U/.V/XR_ E-SIT- R V 0.U/0V/XR_ E-SIT- *0U/.V/XR_ E-SIT- E-SIT- *U/.V/XR_ V_S *short_.0v *short_ *short_ 0.U/0V/XR_ R U/.V/XR_ R *short_ *U/.V/XR_ U/.V/XR_ *short_ *short_ *short_ L *0uH/00m_ *short_ *0_ V_S V.0V.0V.0V.VSUS *short_ V_S.0V.0V.0V.0V.V.0V R 0.00/F_0 R.0V_PH_VPLL_EXP E-SIT-.0V_VPLL_EXP L *uh/m_ R 0.00/F_0 V (Mobile.V).0V V *short_.0v_vio R.0V_PH_V E-SIT- 0m (mils) VFI_VRM.0V.0V L0 0uH/00M_ L 0uH/00M_ R. (0mils) V_V_EXP VFI_VRM.0V_VPLL_FI R0 *0_ E-SIT-.0V_VPLL_FI 0m (0mils).0V_V PL 0m (0mils).0V_V PL 0m (0mils) V_SUS_LKF /F_ V_SUS_LKF_R L 0uH/00m_ 0m (0mils).0V V_MI_I.V_V_MI_I R E-SIT- 0 U/.V/XR_ U/.V/XR_ 0 0 0U/.V/XR_ U/.V/XR_ R R R R *0_ *0_ */F_ 0 0.U/0V/XR_ U/.V/XR_ 0U/.V/XR_ U/.V/XR_ *short_ *short_ *short_ 0 *0U/.V/XR_ R 0 U/.V/XR_ 0 U/.V/XR_ E-SIT- *short_ L *0uH/00m_ 0 U0G VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] G VORE[] G VORE[] G VORE[] G VORE[0] G VORE[] G VORE[] J VORE[] J VORE[] J VORE[] J VORE[] J VORE[] N J N N N N N P P P P T N N H P G P U0 0 ougarpoint_rp0 VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VccFIPLL VIO[] VMI[] U/.V/XR_ U/.V/XR_ 0U/.V_ POWER V ORE VIO FI 0U/.V_ RT LVS FT / SPI MI HVMOS U/.V/XR_ 0U/.V/XR_ V VSS VLVS VSSLVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] VVRM[] VMI[] VLKMI VFTERM[] VFTERM[] VFTERM[] VFTERM[] VSPI U U K K M M P P V V T T0 G G J J V V_PH_VREF VREF= m m (0mils) V_PH_VREFSUS VREFSUS=m VLVS 0m (0mils) V_TX_LVS L 0.uH/0m_ V_V_GIO V R VFI_VRM.V_V_MI_I 0m (0mils) V_VME_SPI.V_V_MI VP_NN ate: Monday, January, 0 Sheet of V Quanta omputer Inc. V.V V V V_S V_S.0V.V PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev PH / (POWER) H0KF-T/._ 0 0 R R U/.V/XR_ 0U/.V/XR_ 0.U/0V/XR_ *0_ *short_ *short_ E-SIT- 0.0U/V/XR_ E-SIT- 0.U/0V/XR_ U/.V/XR_ R 0.U/0V/XR_ 0.0U/V/XR_ U/.V/XR_ 0.0U/V/XR_ m (0mils) R *0U/.V/XR_ E-SIT- 0 U/.V/XR_ 0 m (mils) *short_ R0 E-SIT- U/.V/XR_ R0 0_ E-SIT- 0.U/0V/XR_ R00V-0 R 0_ R00V-0 *short_ *short_

12 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER PH / (GN) Monday, January, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER PH / (GN) Monday, January, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER PH / (GN) Monday, January, 0 IEX PEK-M (GN) IEX PEK-M (GN) U0H ougarpoint_rp0 U0H ougarpoint_rp0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L U0I ougarpoint_rp0 U0I ougarpoint_rp0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J

13 R R0 () M [:0] () M S#0 () M S# () M S# () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M S# () M RS# 0K_ () M WE# 0K_ (,,,) PLK_SM (,,,) PT_SM () M OT0 () M OT () M QSP[:0] () M QSN[:0] M 0 M M M M M M M M M M 0 M M M M M IMM0_S0 IMM0_S PLK_SM PT_SM M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN N /P /# S0# S# 0 K0 0 K0# 0 K 0 K# KE0 KE S# 0 RS# WE# S0 0 S 0 SL 00 S OT0 0 OT M0 M M M M M 0 M M QS0 QS QS QS QS QS QS QS 0 QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q R-IMM0_H=._ST ddr-c-0-0p GMK0000 I SOKET R ST SO-IMM(0P,H.) M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q[:0] () V () PM_EXTTS#0 (,) R_RMRST# () SMR_VREF_IMM E-SIT-. V R PM_EXTTS#0.VSUS.P/0V/0G_ 0K_ SMR_VREF_Q0 SMR_VREF_IMM N V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 R-IMM0_H=._ST ddr-c-0-0p GMK0000 I SOKET R ST SO-IMM(0P,H.) 0.V_R_VTT (,,).VSUS (,,,,,) V (,,,,0,,,,,,,,,,,,,,,,,,,,,) R_VTTREF (,,) 0.V_R_VTT Place these aps near So-imm0. VREF Q0 M Solution V.VSUS U/.V/XR_ 0.V_R_VTT U/.V/XR_ *0.U/0V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_.VSUS.VSUS V PT_SM PLK_SM U0 0 S SL *SUT&R VS O.S GN R *0K_ MEMHOT_IMM# Q *N00 SYS_SHN# (,,,) 0 U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ SMR_VREF_IMM 00 U/.V/XR_ 0U/.V/XR_ *0U/.V/XR_ 0.U/0V/XR_.U/.V/XR_ R_VTTREF R *0_ R K/F_ SMR_VREF_Q0 R0 K/F_ R_VTTREF R *0_ R 0K_ SMR_VREF_IMM R0 0K_ 0P/0V/XR_ RESS: H lose R socket N,N *0U/.V/XR_ 0U/.V/XR_ SMR_VREF_Q0 0.U/0V/XR_ 0U/.V/XR_.U/.V/XR_ V 0.U/0V/XR_.U/.V/XR_ Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom R IMM0-ST (.H) ate: Monday, January, 0 Sheet of

14 V R R 0K_ 0K_ () M [:0] () M S#0 () M S# () M S# () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M S# () M RS# () M WE# (,,,) PLK_SM (,,,) PT_SM () M OT0 () M OT () M QSP[:0] () M QSN[:0] M 0 M M M M M M M M M M 0 M M M M M IMM_S0 IMM_S M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN N /P /# S0# S# 0 K0 0 K0# 0 K 0 K# KE0 KE S# 0 RS# WE# S0 0 S 0 SL 00 S OT0 0 OT M0 M M M M M 0 M M QS0 QS QS QS QS QS QS QS 0 QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q[:0] () () PM_EXTTS#0 (,) R_RMRST# () SMR_VREF_IMM. V.VSUS PM_EXTTS#0 N0 V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# SMR_VREF_Q SMR_VREF_IMM VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 R-IMM_H=.0_RVS R--00-RVS-0P GMK00000 I SOKET R SOIMM(0P,H.0,RVS) 0.V_R_VTT 0.V_R_VTT (,,).VSUS (,,,,,) V (,,,,0,,,,,,,,,,,,,,,,,,,,,) R-IMM_H=.0_RVS R--00-RVS-0P GMK00000 I SOKET R SOIMM(0P,H.0,RVS) Place these aps near So-imm. VREF Q M Solution.VSUS 0.V_R_VTT SMR_VREF_IMM.VSUS 0 U/.V/XR_ U/.V/XR_ 0.U/0V/XR_ U/.V/XR_ U/.V/XR_ 0 0 U/.V/XR_ U/.V/XR_.U/.V/XR_ R K/F_ U/.V/XR_ 0 U/.V/XR_ SMR_VREF_Q R_VTTREF R *0_ SMR_VREF_Q 0U/.V/XR_ 0U/.V/XR_ 0 0U/.V/XR_ *0U/.V/XR_ 0 0.U/0V/XR_.U/.V/XR_ R0 K/F_ 0U/.V/XR_ 0U/.V/XR_ V 0U/.V/XR_ 0.U/0V/XR_ 0 0U/.V/XR_.U/.V/XR_ *0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom R IMM-RVS (.0H) ate: Monday, January, 0 Sheet of

15 LV ack light V (,,,,0,,,,,,,,,,,,,,,,,,,,,) VPU (,,,0,,,,,,,) V (,,,) V (,,,,,,,,) (,,,,,,,) VSUS (,,) VPU (,,,,,,) V V LV () INT_ISP_ON R 0K_ R 0K_ LV_ON VPU Q N00W R 00K_ Q PTEU VPU V Q0 O0 R 0U/.V/XR 0.0U/V/XR_ Q N00W For ES INT_TXLLKN INT_TXLLKP INT_EILK INT_EIT For RF E-SIT- S *0.U/0V/XR_.P/0V/XR_ 0 00P/0V/XR_ () INT_EILK () INT_EIT () INT_TXLOUTN0 () INT_TXLOUTP0 () INT_TXLOUTN () INT_TXLOUTP () INT_TXLOUTN () INT_TXLOUTP () INT_TXLLKN () INT_TXLLKP S *0.U/0V/XR_.P/0V/XR_ 00P/0V/XR_ For EMI For EMI For ES LV V S R0 0_ R 0_ R 0_ R 0_ R 0_ R 0_ R 0_ R 0_ 0 () LOGO_LE_# VSUS INT_EILK INT_EIT INT_TXLOUTN0_R INT_TXLOUTP0_R INT_TXLOUTN_R INT_TXLOUTP_R INT_TXLOUTN_R INT_TXLOUTP_R INT_TXLLKN_R INT_TXLLKP_R () () *0.U/0V/XR_.U/.V/XR_ LOGO_LE_# M_V USP_R USP-_R VJ_PWM ISPON GFX_PWR_SR USP- USP LV-0SFYG N G_ G_0 R R G_ G_ G_ ML *LWHN00SQL INT_EILK INT_EIT USP-_R USP_R V LVS (.") (0x00, x) *short_ *short_ *P/0V/NPO_ *P/0V/NPO_ V close to N R.K_ FOR ES U IO IO GN *PJSR0 R.K_ M_V R0 0K_ R *.K_ LOGO_LE_# For ES (,) LI# S *0.U/0V/XR_ R00V-0 0.U/0V/XR_ R00V-0 R 00K_ ISPON *P/0V/NPO_ *lamp-iode_ For ES () INT_LVS_LON () INT_PST_PWM R.K_ R 0K_ *U/0V/XR_ E-SIT- R *short_ VJ_PWM Q PTEU L_K_OFF () GFX_PWR_SR LOGO_LE_# For EMI 00P/0V/XR_ E-SIT- R *short_ MER V ontrol (0) _ON Q HTEUPT R 0K_ R0 0K_ 00P/0V/XR_ V Q OS U/.V/XR_ R *0_ M_V 0.U/0V/XR_ *P/0V/NPO_ 0.U/V/XR_ 0.U/V/XR_ *0U/V/XS_ Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev L/MER ate: Monday, January, 0 Sheet of

16 (,,,0,,,,,,,) VPU (,,,,0,,,,,,,,,,,,,,,,,,,,,) V (,,,,,,,,) V For ES E () RT_R_ON L LM0SN VG_RE_L () RT_G_ON L LM0SN VG_GRE_L () RT ON L LM0SN VG_LU_L VG_RE_L VG_GRE_L 0 0 VG_LU_L.P/0V/OG_.P/0V/OG_.P/0V/OG_.P/0V/OG_.P/0V/OG_.P/0V/OG_ VPU V (,) LI# () HSYN E-SIT- () VSYN () RTLK () RTT V S S *0.U/0V/XR_ *0.U/0V/XR_ RT@-0 R *.K_ R *.K_ N V E-V-0 V R /F_ HMI_TX N R /F_ HMI_TX- HMI_TX SHELL 0 () HMI_TX R /F_ HMI_TX R /F_ HMI_TX- HMI_TX- Shield () HMI_TX- HMI_TX - () HMI_TX R /F_ HMI_TX0 V R /F_ HMI_TX0- R R HMI_TX- Shield () HMI_TX-.K_.K_ HMI_TX0 - () HMI_TX0 R /F_ HMI_LK 0 R /F_ HMI_LK- HMI_TX0-0 Shield () HMI_TX0- HMI_LK 0- GN () HMI_LK 0 K () INT_HMI_SL R R.K_ HMI_LK- K Shield GN () HMI_LK- Q K- FV0N E Remote V HMI LK N HMI T LK T V V F HMI_V GN HP_ET V () INT_HMI_S Q FUSEV_POLY HP ET N00K-T-E Q SHELL FV0N SP@HMI HMI_LF.K_ HMI_TX HMI_TX- HMI_TX0 HMI_TX0- HMI_TX HMI_TX- HMI_TX HMI_TX- HMI_TX HMI_TX- HMI_LK HMI_LK- For ES U V 0 0 GN *Rlamp0M_G U 0 0 V GN HMI_LK HMI_LK- HMI_TX0 HMI_TX0- HMI_TX- *Rlamp0M_G R U *00/F_ Q R HMI T HMI T HMI_TX0- N00K-T-E 0K/F_ HMI LK 0 0 HMI LK HMI_LK HMI_V V GN HMI_V HP_ET HP_ET R0 *00/F_ *Rlamp0M_G HMI_LK- Layout note:place close to HMI onn EMI reserve for HMI HMI_TX HMI_TX HMI_TX- HMI_TX0 R *00/F_ R *00/F_ () HMI_HP V R 0K_ Q N00K-T-E V R 0K_ HP_ET HMI_V 0P/0V/XR_ For EMI Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom <oc> RT/HMI ONN ate: Monday, January, 0 Sheet of E

17 LN: R-L-R LNV.V_REG_ LNV LNV R *.K_ PIE_REQ_LN# 0U/.V/XR_ 0U/.V/XR_ U/.V/XR_ VPU Q O0 () LK_PIE_LNP () LK_PIE_LNN () LN_ON LNV () PIE_RXP_LN () PIE_RXN_LN () PIE_TXP_LN () PIE_TXN_LN R 0_ (,,,,,,) PLTRST# (,) PIE_WKE# LNV_R LNV Trace width>0mil, Trace length<00mil.v_reg_ 0mil 0 U/.V/XR_ 0 0.U/0V/XR_ *0U/.V/XR_ 0.U/0V/XR_.V_REG_ 0.U/0V/XR_ U/.V/XR_ 0mil 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R R () PIE_LKREQ_LN# *.K_ *.K_ R0 R Y 0 LN_REST# PIE_WKE#_R E-SIT- PIE_RXP_LN_ PIE_RXN_LN_ *R0V-0 PIE_REQ_LN# R LNV 0.U/0V/XR_ 0.U/0V/XR_ MHZ *short_ LN_REST# *short_ PIE_WKE#_R.K/F_ R R0 RSET *.K_ *.K_ XTL XTL U REFLKP REFLKN 0 TX_P TX_N RX_P RX_N PERSTn WKEn 0 0.U/0V/XR_ RIS SMLK SMT XTLO XTLI R-L-R V VT_REG/KRn theros V_REG VL VL_REG VL VL VL VL R VH VH VH_REG TRXP0 TRXN0 TRXP TRXN TRXP TRXN 0 TRXP TRXN LE_LINK0/00n LE_Tn LKREQn/LE VT MI_0 MI_0- MI_ MI_- MI_ MI_- MI_ MI_- RJ_LINKUP# RJ_TIVITY# LE T LX L LX 0 0mil VT TEST_RST TESTMOE GN GN GN GN GN GN GN GN GN GN 0 R R R R0 R R R R 0mil./F_./F_./F_./F_./F_./F_./F_./F_ 0 *000P/0V_ 0 *000P/0V_ EMI Reserved.uH 000P ==> EMI Reserved U/0V/XR_ *000P/0V_ 0.U/0V/XR_ *000P/0V_ 0.U/0V/XR_ *000P/0V_ 0.U/0V/XR_ *000P/0V_ 0.U/0V/XR_ 0.U/0V/XR_ 0U/.V/XR_ 000P/0V/XR_ RJ_TIVITY# R.K/F_ P/0V/NPO_ P/0V/NPO_.V_REG_.V_REG_.V_REG_ 0mil U/.V/XR_ 0.U/0V/XR_ 0 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ Tramsformer Layout:ll termination signal should have 0 mil trace T- MX- T MX LFE-R T- T 0 TT TT L PY00T-0Y-N_ MX- MX MT MT LN_MX0- LN_MX0 LN_MT0 LN_MT LN_MX- LN_MX R R VT /F_ /F_ LNT RJ onnector MI_0 MI_ MI_- MI_- U IO IO GN REF IO IO TVLST00 U0 IO IO GN REF IO IO TVLST00 MI_ U/.V/XR_ TR_V_ 000P ==> EMI Reserved MI_0- MI_0 *000P/0V_ 0.U/0V/XR_ *000P/0V_ 00 0.U/0V/XR_ MI_- MI_ MI_0- MI_- MI_ U, U Reserve for Surge and cable ES E-V- LNV LNV LNV RJ_TIVITY# EMI:close RJ *0.U/0V/XR_ R 0_ E-V-0 RV *VRISTOR_ *0.U/0V/XR_ N R 0_ LN_GLE RJ_LINKUP# LE_GRE_P LE_GRE_N GREEN LE LN_MX- LN_MX RX- LN_MX- RX LN_MX- RX0- GN LN_MX TX- LN_MX TX GN LN_MX0- RX0 LN_MX0 TX0- GN TX0 GN Orange LE LE_YEL_P 0 LE_YEL_N MI_- T- MX- LN_MX- MI_ T MX 0 LN_MX *000P/0V_ LN_MT R /F_ 0.U/0V/XR_ TT MT *000P/0V_ LN_MT R /F_ 0.U/0V/XR_ TT MT MI_- T- MX- LN_MX- MI_ T MX LN_MX U ISN R M/F_ 000P/KV/NPO_ RV VRISTOR_ E-V-0 E-V-0 For ES reserved SR *0_ *0.U/0V/XR_ EMI:close RJ RV0 *VRISTOR_ JM-N-F RJ onnector E-V-0 Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ustom LN_R-L-R ate: Monday, January, 0 Sheet of

18 Note: To support Wake-on-Jack or Wake-on-Ring, the OE VUX_. pins must be powered by a rail that is not removed unless power is removed. V_. pin is output of internal LO. o NOT connect to external supply. 0U/.V/XR_ V_.V V Layout Note: Path from V to LPWR_.0 and RPWR_.0 must be very low resistance ( <0.0 ohms). Place bypass caps very close to device. V (,,,,0,,,,,,,,,,,,,,,,,,,,,) V (,,,,,,,,) E Z_ITLK_UIO_R FOR EMI () V_V H udio us Z_RST#_UIO () Z_ITLK_UIO () Z_SYN_UIO () Z_SIN0 () Z_SOUT_UIO R0 *P/0V/NPO_ E-SIT- *short_ U/V/XR_ 0.U/0V/XR_ X_VIO U/V/XR_ 0.U/0V/XR_ GN FILT_.V 0U/.V/XR_ E-V- E-V- 0.U/0V/XR_ FOR EMI R0 0_ Z_ITLK_UIO_R R 0_ R00 _ Z_SIN0_ R0 0_ 0 FILT_.V U GN 0U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0U/.V/XR_ RESET# IT_LK SYN ST_IN ST_OUT FILT_. 0.U/0V/XR_ V_V VUX_. V_IO V_. V_HP FILT_. V_. V_V LPWR_.0 RPWR_.0 LSS_V 0.U/0V/XR_ LSSREF E-V- SENSE_ 0 SENSE 0.U/0V/XR_ 0.U/0V/XR_ 0U/.V/XR_ 0U/.V/XR_ V_V R.K/F_ R R0 R 0.U/0V/XR_. 0U/.V/XR_ V V Mount R (0K) Vendor suggestion 0K/F_.K/F_ *0K/F_ SENSE_MI SENSE_HP L0 NH0KF-T0 0 GN 0U/.V/XR_ 0 0. U/0V/XR_ 00 0.U/0V/XR_ V_V V L NH0KF-T0 0 SENSE_HP SENSE_MI GN Q R0 N00K-T-E Q R N00K-T-E 0K/F_ E-V- 0K/F_ 0.U/0V/XR_ GN SENSE_HP R K/F_ E-V- IGITL_MI S *0.U/0V/XR_ HPOUT_R MI_LK PORT_R R V R 0_ 0 HPOUT_L.K_ MI_T MI_T R 0_ MI_LK PORT_L GN GN MI_LK MI_/ VEE VEE 0U/.V/XR_ R *short_ FLY_N 0 For EMI N FLY_P 0.U/0V/XR_ U/V/XR_ V_.V R K_ R *0_ MI-VREF ONN_IGITL_MI MI_T P/0V/NPO_ S *0.U/0V/XR_ P_EEP 0 MI_LK P/0V/NPO_ INT Speaker () For ES reserved R R R R EEP 0.U/0V/XR_ From E VOLMUTE# V For ES reserved S *0.U/0V/XR_ P EEP ONTROL K0HS0 K0HS0 K0HS0 K0HS0 *00P/0V/XR_ EEP R0 _ R R *0K/F_ *0K/F_ *00P/0V/XR_ SPIF P/0V/NPO_ For RF SPK_R_OUT SPK_R-_OUT SPK_L_OUT SPK_L-_OUT *00P/0V/XR_ U *P P/0V/NPO_ *00P/0V/XR_ V_V T 0 P_EEP 0 E-SIT- ONN_SPEKER N lose to codec TSETFU 0.U/0V/XR_ P_EEP N_S GPIO0/EP# GPIO/SPK_MUTE# X0-Z SPK_L LEFT From E PEEP_ () Z_SPKR () From S SPK_R SPK_R- SPK_L SPK_L- SPK_L- SPK_R- LEFT- RIGHT- SPK_R RIGHT ES Reserved EMI Reserved GN GN GN GN GN GN PORT_R PORT_L _IS _IS PORT_R 0 PORT_L N_R N_L EP_GN SR SR MI_R MI_L E-V-0 R0 0 0 *0_ *0_ *short_ GN GN 000P/0V/XR_ 000P/0V/XR_ 000P/0V/XR_ *SHORT00 000P/0V/XR_ 000P/0V/XR_ E-V-0 0 HP-OUT-L_ 0 *00P/0V/XR_.U/.V/XR_.U/.V/XR_ GN Z_ITLK_UIO HP-OUT-R_ GN MI-VREF GN Z_SIN0_ FOR EMI EXT_MI_L_ EXT_MI_MV Port onfiguration Port : Headphone jack (jack shared with S/PIF) Port : Internal analog mono or stereo MI. Port : Microphone jack Port G: Internal stereo speakers Port J: Optional Internal stereo digital mic Port H: S/PIF (jack shared with headphone) L *0.0uH *00P/0V/XR_ R0 0_ R0 0_ L *0.0uH *P/0V/NPO_ *00P/0V/XR_ E-V- T0 *P GN L *0.0uH *P/0V/NPO_ HPOUT_L HPOUT_R R R0 /F_ /F_ HP-OUT-L_ HP-OUT-R_ External MI/ GN Headphone out combo R *K_ Q SSN 0 0U/.V/XR_ L 0_ L 0_ R *K_ E-V- 00P/0V/XR_ 0 R U/0V/XR_ V GN GN 00P/0V/XR_ 0 0K_ R GN R HP-OUT-L_ HP-OUT-R_ R0 *0K/J_ VL S 0 (.V,00p)_ RV RV E-V- SENSE_HP EXT_MI_L_ E EXT_MI_L_ EXT_MI_MV Sense For MI/ Headphone out combo K_ U/0V/XR_ VL S 0 (.V,00p)_ 00/F_ RV GN Quanta omputer Inc. GN PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev UIO (X0, SPK) N OMO_JK Monday, January, 0 ate: Sheet of VL S 0 (.V,00p)_ 0

19 V (,,,,0,,,,,,,,,,,,,,,,,,,,,) H V (,,,,,,,,) N PLE ST OUPLING PS LOSE TO onnector urrent rating: (MX) GN - GN - GN.V.V.V 0 GN GN GN V V V GN RSV GN V 0 V V ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ 0 V_H V_H R 0.0U/V/XR_ 0.0U/V/XR_ 0.0U/V/XR_ 0.0U/V/XR_ H_ETET# () *Short_ ST_TXP0 () ST_TXN0 () ST_RXN0 () ST_RXP0 () V V E-SIT- R *short_ urrent rating: (MX) E-SIT- R *short_ V_H 0U/0V/XR_ 0U/0V/XR_ *.U/.V/XR_ 0.U/0V/XR_ V_H 0 0U/.V/XR_ 0 0.U/0V/XR_ ONN_H Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev ST ate: Monday, January, 0 Sheet of

20 TPS table USPWR 0P/0V/XR_ 0.U/0V/XR_ 0U/.V/ESR_ US onnector 0 E-SIT- R *short_ N US USP- USP ML *LWHN00SQL USP-_R USP_R V - GN GN GN GN GN V_S.U/.V/XR_ US0PWR R E-SIT- *short_ *0P/0V/OG_ *0P/0V/OG_ U IO IO US_ON *PJSR0 GN USPWR () 0.U/0V/XR_ 0 mils (Iout=.) USPWR R K/F_ US_O0_# I current limit is. U IN OUT GN N PGN ILIM0 ILIM ILIM_SEL /FULT TPS0/ EN/S TL TL TL M_IN P_IN 0 M_OUT P_OUT USP- USP USHR_ON () US_0 () E-V- USP- () USP () () () USP0- USP0 0 0P/0V/XR_ 0.U/0V/XR_ E-SIT- R0 *short_ *LWHN00SQL ML R0 *short_ E-SIT- 0 0U/.V/ESR_ USP0-_R USP0_R *0P/0V/OG_ *0P/0V/OG_ U IO IO N V GN - GN GN GN GN US_ON *PJSR0 GN US US0PWR USPWR E-SIT- () V_S 0 U/0V/XR_ US_ON# U EN GN OUT OUT OUT O PL0XI-TRG 0 mils (Iout=) US0PWR US_O0_# () () () USP- USP () IN_LE# For EMI E-SIT- R ML R E-SIT- 000P/0V/XR_ *short_ *LWHN00SQL *short_ USP-_R USP_R N E-V-0 US T connector onnector-fp/ff VPU V_S U/0V/XR_ U EN GN OUT OUT OUT O PL0XI-TRG 0 mils (Iout=) USPWR US_O_# () 000P/0V/XR_ V_S (,) VPU (,,,,,,,,,,) 000P/0V/XR_ Quanta omputer Inc. () US_ON# PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev US x ate: Monday, January, 0 Sheet 0 of

21 (,,,,,,) PLTRST# () PIE_LKREQ_R# V E-SIT- R0 R R 0_ *short_ *short_ V_R PLTRST#_R V (,,,,0,,,,,,,,,,,,,,,,,,,,,) Note: R U 0.U/0V/XR_.K/F_ RREF RREF V_IN LK_REQ# PERST# EEO EES EESK GPIO/EEI 0 MS_INS# S_# SP SP S_# S_WP S/MM SP S_ SP S_ SP S_ SP S_ SP SP SP SP SP SP0 SP SP SP SP SP S_WP MS MS_S MS_ MS_0 MS_ MS_ MS_LK () () PIE_TXP PIE_TXN PIE_TXP PIE_TXN HSIP HSIN SP SP () LK_PIE_R REFLKP SP.U/0V/XR_ () LK_PIE_R# V () PIE_RXP () PIE_RXN V PIE_RXP 0.U/0V/XR_ PIE_RXN 0.U/0V/XR_ ard_v 0.U/0V/XR_ V 0 PIE_RXP_ PIE_RXN_ GN 0 REFLKN V HSOP HSON GN V ard_v V_IN ard_v RTS0 SP0 SP SP SP 0 SP SP V_S GN S_ V_S_R GN S R R0 0_ V_S.U/0V/XR_ R0 0_ S_ 0.U/0V/XR_ 0U/0V/XR_ 0.U/0V/XR_ 0 X_# V_ GN SP SP SP SP S_ S_0 S_LK S_M S_ V_ GN S R S_M_R S_LK_R R0 0_ R0 0_ R 0_ S_ S_M S_LK 0.U/0V/XR_ *.U/0V/XR_ *P/0V/NPO_ S_0_R R 0_ S_0 V L V S R R 0_ S_ *0_ IN R REER R~R, close to chip pin It is recommended that mismatch trace length between LK and T trace is 00 mils with maximum V_S N S-T S-M GN S-V S-LK GN S-T0 S-T S-T S- 0 S-WP SHIEL-GN SHIEL-GN SHIEL-GN SHIEL-GN S_ S_M S_LK S_0 S_ S_ S_# S_WP V_S Memory ard Power Supply 0.0U/V/XR_ 0 0.U/V/XR_ 00m R 0_ 0U/.V/XR_ ard_v Use 00 type and Trace width = 0 mil" at ard_v R REER SOKET FHMR0 sdcard-css--h-n-p Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev GF ard Reader ate: Monday, January, 0 Sheet of

22 Miniard WLN connector.v_wln.v_wln.v N V (,,,,0,,,,,,,,,,,,,,,,,,,,,).V (,,) V_S (,,,,0,,,,) PI-Express TX and RX direct to connector () MINIR_PME# () 0EX () 0EX () PIE_LKREQ_WLN# () LK_PIE_WLNN () LK_PIE_WLNP (,,) () () () () SERIRQ PIE_RXN PIE_RXP PIE_TXN PIE_TXP (0,) T_ON MINIR_PME# E-SIT- R0 T *short_ WKE# RESERVE_ RESERVE_ LKREQ# GN REFLK- REFLK GN UIM_ UIM_ GN PERn0 PERp0 GN GN PETn0 PETp0 GN RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_0.V_ GN0.V_ UIM_PWR UIM_T 0 UIM_LK UIM_RESET UIM_VPP GN W_ISLE# 0 PERST#.VUX GN.V_ SM_LK 0 SM_T GN US_- US_ GN0 0 LE_WWN# LE_WLN# LE_WPN#.V_ GN 0.V_ WLN_OFF_R# USP-_ USP_ R E-SIT- R R R R T E-SIT- *short_ *short_ *short_ *Short_ *Short_ LP_FRME# (,,) LP_0 (,,) LP_ (,,) LP_ (,,) LP_ (,,) PLTRST# (,,,,,,) PLK_EUG () LP_RQ#0 () USP- () USP () V_S S--0 R0 *0K_ (,) PIE_WKE# Q *PTEU@N MINIR_PME# WLN_OFF_R# R R00V-0 *0_ WLN_OFF# (0) USP-_ USP_ U IO IO GN *PJSR0.V_WLN.V_WLN V.V.V_WLN Place caps close to connector. close to N R 0_ 0.0U/V/XR_ 0.U/0V/XR_ 0 0U/.V/XR_ *P/0V/NPO_ close to N 0.U/0V/XR_ 0.0U/0V/XR_ 0.U/0V/XR_ 0.0U/0V/XR_.U/.V/XR_ *P/0V/NPO_ Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev WLN ate: Monday, January, 0 Sheet of

23 SIM ard ONN V (,,,,0,,,,,,,,,,,,,,,,,,,,,).V (,,) UIM_VPP UIM_T N GN V VPP RST I_O LK N/ N/ T ET 0 SHIEL SHIEL ONN_SIM UIM_PWR UIM_RESET UIM_LK SIM_ET V R *0K_ T E UIM_RESET UIM_LK U M-0SO UIM_VPP UIM_PWR UIM_T Layout Note: UIM_RESET,UIM_LK,UIM_T routting as short as possible P/0V/NPO_ P/0V/NPO_ P/0V/NPO_ U/0V/XR_ P/0V/NPO_ Miniard WWN connector.v_wwn N.V_WWN.V () MINIR_PME# () PIE_REQ_WWN# () LK_PIE_WNN () LK_PIE_WNP WKE# RESERVE_ RESERVE_ LKREQ# GN REFLK- REFLK GN.V_ GN0.V_ UIM_PWR UIM_T 0 UIM_LK UIM_RESET UIM_VPP UIM_PWR UIM_T UIM_LK UIM_RESET UIM_VPP () () () () PIE_RXN PIE_RXP PIE_TXN PIE_TXP PI-Express TX and RX direct to connector UIM_ UIM_ GN PERn0 PERp0 GN GN PETn0 PETp0 GN RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_ RESERVE_0 S--0 GN W_ISLE# 0 PERST#.VUX GN.V_ SM_LK 0 SM_T GN US_- US_ GN0 0 LE_WWN# LE_WLN# LE_WPN#.V_ GN 0.V_ USP-_ USP_ R R R R R0 T *Short_ *short_ *short_ *short_ *short_ E-SIT- WWN_OFF# (0) PLTRST# (,,,,,,) PLK_SM (,,,) PT_SM (,,,) USP- () USP () USP-_ USP_ U IO IO *PJSR0 GN V.V.V_WWN Place caps close to connector..v_wwn V 0 0.0U/0V/XR_ P/0V/NPO_ *P/0V/NPO_ P/0V/NPO_ 0.0U/0V/XR_ P/0V/NPO_ 0.0U/0V/XR_ *P/0V/NPO_ R 0_ close to N close to N Quanta omputer Inc. PROJET /M NOTE INTEL HURON RIVER Size ocument Number Rev WWN ate: Monday, January, 0 Sheet of