GIGABYTE GA-6OXT Reference Schematics

Size: px
Start display at page:

Download "GIGABYTE GA-6OXT Reference Schematics"

Transcription

1 E GIGYTE G-OXT Reference Schematics Revision :.0 TITLE OVER SHEET INTEL PIII SOKET-0 GMH (INTEL EP ) SRM SOKET (IMM,IMM,IMM) GP SLOT IH (INTEL 0) LOK SYNTHESIZER PI SLOTS ( PI,PI,PI,PI,PI ) FWH ( SST SL00 ) IE ONNETORS (IE,IE) UZZER & FRONT PNEL & WOL & STR LE OE ( RELREK 0 ) UIO PHONE JK & FRONT UIO NR SOLT LP ( IT/X ) & SR OM & LPT PORTS & FLOPPY H/W MONITOR & FN PS ONNET & FRONT SMUS & IR/IR & US TX POWER & STR LO & VUL & _ORE - ONVERTER HISTORY JUMPER SETTING LR_MOS - - IOS_WP - - OE_EN - - LER MOS NORML WRITE PROTET NORML ENLE ISLE SHEET,,,,,,0,,,, 0 0 GPO/GNT- GPI/PIRQF- GPI/PIRQH- ** GPI ** GPI ** GPI ** GPI ** GPI ** GPI GPI/PIRQG- IH GPIO FUNTION PULL UP/OWN ** GPI0/REQ- PRI_WN- PULL UP.K TO GPO/GNT- GPI/PIRQE- GPI/REQ- GPO GPO ** GPO0 ** GPO GPO GPO ** GPIO ** GPIO ** GPIO ** GPIO NOT USE NOT USE GREEN UTTON GP/IMM OVER VOLTGE REV. I REV. I REQ- PIRQF- PIRQG- LPPME- SMRT R REER NOT USE GNT- NOT USE NOT USE GP OVER VOLTGE.V GP OVER VOLTGE.V NOT USE NOT USE REV. I IOS WRITE PROTET IMM OVER VOLTGE.V IMM OVER VOLTGE.V PULL UP.K TO PULL UP.K TO PULL UP.K TO PULL UP.K TO PULL UP.K TO PULL UP.K TO VUL PULL UP.K TO PULL UP.K TO VUL PULL UP.K TO VUL PULL UP.K TO VUL PULL UP.K TO VUL PULL.K TO (N'T PULL OWN).ecause IOS ddress ecode Incorrect : FF PULL.K TO PULL.K TO PULL.K TO VUL LP I/O GPIO FUNTION PULL UP/OWN ** GP0/LKRUN- STR FUNTION PULL OWN.K TO GIGYTE ORP. OVER Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0 E

2 G-OXT.0 SOKET 0 / GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H[0..] H[..] VI[0..] H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H0 H VI0 VI VI VI RS0- RS- RS- HREQ0- HREQ- HREQ- HREQ- HREQ- H[0..] (,) VI[0..] (,) RS0- (,) RS- (,) RS- (,) HREQ0- (,) HREQ- (,) HREQ- (,) HREQ- (,) HREQ- (,) H[..] (,) VORE VORE VORE VORE U SK0/GF/ W T N M U S T J S P Q M Q L N U H R P H L G F G K E E F J F 0 E K H H N L H0 L H K0 N L K L N E Z G J E F Y K Z H H K K H H L M M H Z V M H L K G Y U Q L G M J E M0 J E M J E M J E F0 0 M J F M J F M0 0 L K F T P K F E M E W S N J F J M J E 0 M J E M J E M0 J 0 F M J F M J K F0 0 M H Z V R M L J L H0 F K K K0 L L L F N N H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# RS#0 RS# RS# REQ#0 REQ# REQ# REQ# 0 PWRG VI VI VI VI REQ# RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV0 RSRV RSRV RSRV RSRV RSRV RSRV H# RSRV RSRV 0 0.U//Y/V 0.U//Y/V/X 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V/X 0.U//Y/V/X S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V S.U//Y/0V/X S.U//Y/0V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.U//Y/V R 0K/

3 R0 // MIL WITH GTLREF lose to PU VMOS 0.U//Y/V R 0// 0.U//Y/V 0.U//Y/V U Z E F K R V K K GTLREF VORE M H F X T P K F H V R H H F K Y R 0// R // 0.U//Y/V HS- lose to PU R //X VMOS () PWR RN 0/PR RN0 0/PR PWR TK R 0/S/X PURST- FERR- TMS TI TO R 0/ R 0/ R.K/ FLUSH- PI IREQ- PI0 () IRY- () PI0 () PI () PI_PU () PUHLK PWR () G TI TO R 0/ TK TMS FLUSH- IREQ- R // PI0 PI N TI N TO N TRST# L TK K TMS J G E E N N N E E E F0 G G L N N N Q Q Q S J L J G PREQ# PRY# P# P# PM0# PM# RSRV RSRV0 RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV0 RSRV RSRV RSRV RSRV NHTRL RSRV RSRV RSRV RSRV PI0 PI PILK V/MOS 0P//N/0V/X P//N/0V/X W LK K PWRGOO H R REST# K/ X RESET# EGTRL PUPRES# V/ V/ VREF0 VREF VREF VREF VREF VREF VREF VREF YN_OE LKREF/LK# NR# PRI# TRY# EFER# LOK# RY# HITM# HIT# SY# S# FLUSH# H N N N K0 N L L L N E J SEL0# J SEL# N R0# THRMP THRMN THERMTRIP# 0M# SLK# SLP# SMI# LINT0/INTR LINT/NMI INIT# FERR# IGNNE# IERR# PLL PLL RSRV0 RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV0 RSRV RSRV L L H E G H0 J M L G G E W U S U U V W W X Y E E R S X SLEWTRL RTTTRL NR- (,) PRI- (,) HTRY- (,) EFER- (,) HLOK- (,) RY- (,) HITM- (,) HIT- (,) SY- (,) HS- () 00_- (,) _00- (,) R0- () 0M- () SLK- () PUSLP- () SMI- () INTR () NMI () HINIT- (,) FERR- () IGNNE- () L.U//Y/0V E U//V/ UH//S R 0/ R 0/ 0.U//Y/V R / TMPIN (,) VORE VORE () PURST- PURST- R / R / 0P//N/0V (,) VI (,) F F X T P F H Z V R M H K F X T P K F J L N Y R 0//X Y R K/ SK0/GF/ 0.U//Y/V.U//Y/0V/X R 0// R 0// VORE 0.U//Y/V 0 0.U//Y/V Size ocument Number Rev ustom.0 0.U//Y/V/X 0 0.U//Y/V 0.U//Y/V/X 0.U//Y/V 0.U//Y/V/X GIGYTE ORP. SOKET 0 / G-OXT 0.U//Y/V 0.U//Y/V ate: Wednesday, October, 00 Sheet of 0

4 H[0..] H[..] H[0..] (,) H[..] (,) H0 H H H RP 0 H0 H H H H H H H RP 0 H H0 H H (,) PRI- (,) HREQ- (,) HREQ0- (,) HREQ- RP 0 PRI- HREQ- HREQ0- HREQ- RS- HLOK- HREQ- EFER- RS- (,) HLOK- (,) HREQ- (,) EFER- (,) /0PR /0PR /0PR H H H H RP0 0 H H H H RP RP H 0 HITM- H H (,) HITM- 0 HTRY- H H (,) HTRY- HIT- RS- H H H (,) HIT- (,) RY- RY- SY- RS0- RS- (,) SY- (,) RS0- (,) /0PR /0PR /0PR H0 H H H RP 0 H H H H0 H H H H RP 0 H H H H /0PR /0PR R 0/ IRY- IRY- () H H H0 RP 0 H H H0 H H0 H H H RP 0 H H H0 H R 0/ R0- R0- () /0PR /0PR H H H H RP 0 H H H H H H H H RP 0 H H H H /0PR /0PR RP RP H0 0 H 0 H H H HREQ- H H H H H H H H H NR- /0PR /0PR HREQ- (,) NR- (,) 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V.U//Y/0V/X 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V S.U//Y/0V/X S0 0.U//Y/V/X GIGYTE ORP. 0 TERMINTOR Size ocument Number Rev ustom G-OXT.0 ate: Wednesday, October, 00 Sheet of 0

5 Place ap close to GMH MIL WITH lose to N/ G-OXT.0 GMH / GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of H0 H H H H H H H H H H0 H H H H H H H H H H0 H H H H H H H H H H H H H H H0 H H H H H0 H H H H H H H H H H H H H H H0 H H H H H0 H H H H H H H H H H H H H H H0 H H H H0 H H H H H H H H H H0 H H H H[0..] H[..] PURST- HS- PIRST- GMHHLK () PIRST- (,,,,) PURST- () HLOK- (,) EFER- (,) HS- () NR- (,) PRI- (,) SY- (,) RY- (,) HIT- (,) HITM- (,) HTRY- (,) HREQ0- (,) HREQ- (,) HREQ- (,) HREQ- (,) HREQ- (,) RS0- (,) RS- (,) RS- (,) H[0..] (,) H[..] (,) HS HETSINK/V/LUE S0 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0.U//Y/V R / U SGMH U 0 H L M G N M J J K L F F E F F E F F F F E E F 0 F 0 0 F0 E E F F F E F F E K R P T R N P R U P T T P T R V Y V W U V W W U Y Y U Y W V M N M L N K L H W Y Y E E E E E E0 E E E E E0 0 P P P P P P R R R R R R R R R R T T T T T T T GTLREF GTLREF HTLK RESET# PURST# HLOK# EFER# S# NR# PRI# SY# RY# HIT# HITM# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# HTRY# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# HREQ#0 HREQ# HREQ# HREQ# HREQ# RS#0 RS# RS# H# P//N/0V/X R // R.// R 0// S P//N/0V/X 0.U//Y/V/X 0.U//Y/V

6 For Support Tualatin HOST FREQ. HIGH=00 LOW= HOST FREQ. HIGH= LOW=00/ HIGH=NON-U LOW=U G-OXT.0 GMH / GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M[0..] SM_QM0 SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM SM_M SM_WE- SM_S- SM_M SM_M[0..] (,,0) SM_M () SM_S- () SM_KE () SM_M- (0) SM_S- (0) SM_KE (0) SM_M (,,0) SM_M- (0) SM_S- () SM_M0 (,,0) SM_M (,,0) SM_S (,,0) SM_M- () SM_S0- () SM_M () SM_M- () SM_S- () SM_M () SM_M- (0) SM_S0- () SM_KE () SM_M (,,0) SM_S- () SM_KE (0) SM_M (,,0) SM_M (,,0) SM_KE0 () SM_S- () SM_RS- (,,0) SM_M- () SM_S- (0) SM_S- (,,0) LK_WR () SM_M () SM_M- (0) SM_S- () SM_M0 (,,0) SM_S- (0) SM_WE- (,,0) SM_M (,,0) SM_S0 (,,0,) SM_S- (0) SM_M (,,0) SM_M- () SM_KE () SM_QM[0..] (,,0) F (,) _00- (,) 00_- (,) VIMM VIMM VIMM VIMM R0 0K/ R0 0K/ P//N/0V/X R0.K/ U SGMH F E G0 F0 0 F E E F G F G E F G J K E G E E F F G H J F E E E0 E E E E0 F F F F E E F F 0 E E E F G0 F G E F0 F F G G G H H H L L L L M M M M M M M N N N N N N N N N P SM0 SM SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM SM0 SM VUL SM SM# SM# SM# SM# SM# SM# SM# SM# SS0 SS SS0# SS# SS# SS# SS# SS# SS0# SS# SS# SS# SRS# SS# SWE# SKE0 SKE SKE SKE SKE SKE SLK RESV SQM0 SQM SQM SQM SQM SQM SQM SQM SROMP SM VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL VUL SS# SS# 00 0.U//Y/V 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V RN 0/PR RN 0/PR R 0K/ Q N0/SOT RN 0/PR RN 0/PR RN 0/PR RN 0/PR R0.K/ S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V RN 0/PR RN 0/PR RN 0/PR R 0.// RN 0/PR RN 0/PR RN 0/PR

7 ON 0 MIL Place HUREF Generation ircuit in middle of GMH and IH G-OXT.0 GMH / GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of G0 G G G G G G G G G G0 G G G G G G G G G G0 G G G G G G G G G G0 G SL_STLL SL_STLL HUREF GMH_GPREF G[0..] () GFRME- () GEVSEL- () GIRY- () GTRY- () GSTOP- () GREQ- () GGNT- () PIPE- () ST0- () ST0 () ST () ST- () SST () SST- () RF- () WF- () ONN_GPREF () OTLK () HUREF () HLST () HLST- () GMHV () GE0- () GE- () GE- () GE- () GPR () ST0 () ST () ST () HL0 () HL () HL () HL () HL () HL () HL () HL () HL () HL () HL0 () S0 () S () S () S () S () S () S () S () GMH_GPREF () VQ VQ VQ VQ R K// R.K/ R // 0 0.U//Y/V R / 0.U//Y/V R 0.// 0.U//Y/V 0 0.U//Y/V 0.0U//X/0V R 0.// S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V 0 0.U//Y/V 0.U//Y/V R.K/ S P//N/0V/X S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V 0.0U//X/0V L NH//S 0 0.0U//X/0V 0 0.U//Y/V 0 0.U//Y/V 0.0U//X/0V 0.U//Y/V U SGMH E F E F F0 0 F E E F 0 K J K J L J0 L K K M M M M N N N T T U T U T V U V V V W W W W Y H N T Y R P P P P R E M L U V Y J J R P 0 Y0 F F E E F H H H G F E E H G F H0 Y Y E F F K0 Y L M U N R U0 U W0 E F G J K M P T V G Y V W W W W Y Y Y Y0 Y Y F F G G G G P H H J J J J K K K L L L L L L T U U K V V V0 F E E LKREF L LTVT0 LTVT LTVT LTVT LTVT LTVT LTVT LTVT LTVT LTVT0 LTVT LNK# TVLKIN/SL_STL LKOUT0 LKOUT TVVSYN TVHSYN LTVL LTV G0/LQM0 G/LM G/LM G/LM G/LM G/LM G/LM G/LM G/LM0 G//LM G0/LQM G/LM G/LM G/LM G/LM G/LM G/LM G/LM G/LM G/LM G0/LM G/LM G/LM0 G/LM G/LKE G/LM G/LS# G/LM G/LTLK G/LM0 G0/LTLK0 G/LM GE#0/LM GE#/LM0 GE#/LM GE#/LRS# GFRME#/LM0 GEVSEL#/LM GIRY#/LM GTRY#/LM GSTOP#/LS# GPR/LM GREQ#/LM GGNT# PIPE#/LM ST0 ST0# ST ST# SST SST# ST0/LM ST/LQM ST/LM RF#/LM0 WF# GPREF GROMP OLOK RLOK LTVT IWSTE IREF VSYN HSYN RE GREEN LUE HLK HL0 HL HL HL HL HL HL HL HL HL HL0 HUREF HLST HLST# HOMP S0/LM S/LM S/LQM S/LM S/LM S/LWE# S/LM S/LGM_FREQ_S VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ R0.K/ S 0.U//Y/V U//Y/0V P//N/0V/X R.K/ E U//V/ RN.K/PR R 0// R 0// R.K/ 0.U//Y/V 0.U//Y/V S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V S 0.U//Y/V R K// R // 0 P//N/0V/X 0P//X/0V S 0.U//Y/V R //X 0P//X/0V

8 G-OXT.0 IMM GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_KE0 SM_M SM_KE SM_M SM_M0 SM_M SM_M SMT SM_S0 SMLK SM_S SM_S0- SM_S- SM_S0- SM_S- SM_WE- SM_S- SM_RS- MEMLK0 MEMLK MEMLK MEMLK SM_M[0..] SM_M[0..] SM_QM[0..] SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_QM SM_QM SM_QM SM_QM0 SM_QM SM_QM SM_QM SM_QM SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SMT (,0,,,) SMLK (,0,,,) SM_WE- (,,0) SM_S- (,,0) SM_RS- (,,0) SM_M[0..] (,,0) SM_M[0..] (,,0) SM_QM[0..] (,,0) SM_S0 (,,0,) SM_S (,,0) SM_KE0 () SM_KE () SO_PU (,0) SM_S0- () SM_S- () SM_S- () SM_S0- () MEMLK0 () MEMLK () MEMLK () MEMLK () VIMM VIMM VIMM VIMM 0 0.U//Y/V R.K/ 0.U//Y/V 0.U//Y/V 0.U//Y/V IMM SR/GF Q0 Q Q Q Q Q Q Q Q /WE0 U /S /RS0 /S0 U /RS /RS /S /RS /S 0 0(P) Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q S0 S S S SL /RS /S N N U N N N U N U KE0 N KE 0 U K0 U K U K U K U U QM0/S0 QM/S QM/S QM/S QM/S QM/S QM/S QM/S 0 N N N/OE0 N/OE N/WE N N N N N N N N R 0K/

9 G-OXT.0 IMM GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of SM_M0 SM_M SM_M SM_M SM_M- SM_M- SM_M- SM_M- SM_KE SM_M SM_KE SM_M SM_M0 SM_M SM_M SMT SM_S0 SMLK SM_S SM_S- SM_S- SM_S- SM_S- SM_WE- SM_S- SM_RS- MEMLK MEMLK MEMLK MEMLK SM_M[0..] SM_M[0..] SM_QM[0..] SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM0 SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SMT (,0,,,) SMLK (,0,,,) SM_WE- (,,0) SM_S- (,,0) SM_RS- (,,0) SM_M[0..] (,,0) SM_M[0..] (,,0) SM_QM[0..] (,,0) SM_S0 (,,0,) SM_S (,,0) SM_KE () SM_KE () SM_M- () SM_M- () SM_M- () SM_M- () SM_S- () SM_S- () SM_S- () SM_S- () MEMLK () MEMLK () MEMLK () MEMLK () SO_PU (,0) VIMM VIMM VIMM 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0.U//Y/V IMM SR/GF Q0 Q Q Q Q Q Q Q Q /WE0 U /S /RS0 /S0 U /RS /RS /S /RS /S 0 0(P) Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q S0 S S S SL /RS /S N N U N N N U N U KE0 N KE 0 U K0 U K U K U K U U QM0/S0 QM/S QM/S QM/S QM/S QM/S QM/S QM/S 0 N N N/OE0 N/OE N/WE N N N N N N N N

10 G-OXT.0 IMM GIGYTE ORP. ustom 0 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of SM_M0 SM_M SM_M SM_M SM_M- SM_M- SM_M- SM_M- SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM SM_QM0 SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M0 SM_M0 SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M SM_M[0..] SM_M[0..] SM_QM[0..] SMT (,,,,) SMLK (,,,,) SM_WE- (,,) SM_S- (,,) SM_RS- (,,) SM_S0 (,,,) SM_S (,,) SM_KE () SM_KE () SM_M- () SM_M- () SM_M- () SM_S- () SM_S- () SM_S- () SM_S- () MEMLK () MEMLK () SO_PU (,) SM_M- () MEMLK0 () MEMLK () SM_M[0..] (,,) SM_M[0..] (,,) SM_QM[0..] (,,) VIMM VIMM VIMM 0 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V IMM SR/GF Q0 Q Q Q Q Q Q Q Q /WE0 U /S /RS0 /S0 U /RS /RS /S /RS /S 0 0(P) Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q S0 S S S SL /RS /S N N U N N N U N U KE0 N KE 0 U K0 U K U K U K U U QM0/S0 QM/S QM/S QM/S QM/S QM/S QM/S QM/S 0 N N N/OE0 N/OE N/WE N N N N N N N N

11 PLE LOSE TO GMH G-OXT.0 GP SLOT GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of S[0..] ST[0..] G[0..] GTRY- SST- ST0 ST0- SST ST- ST SLOTRST- ONN_GPREF TYPEET- S G G G G S G G0 S0 G G G G G G G0 G G G G S GPERR- G S G0 G G G G G G S G G S G S GSERR- G0 G G G GMH_GPREF GSTOP- GPERR- ST0 ST ST GGNT- GREQ- WF- PIPE- RF- GIRY- GFRME- GEVSEL- GPR GSERR- S[0..] () ST[0..] () G[0..] () GE- () ST- () ST () GEVSEL- () TYPEET- () GREQ- () ST0- () ST0 () GPR () GSTOP- () ST0 () ONN_GPREF () GGNT- () PIRQ- (,,,) ST () GIRY- () ST () GTRY- () GE- () GE- () WF- () SST () GPLK () GFRME- () PIPE- () PIRQ- (,) RF- () GE0- () PIPME- (,) SST- () SLOTRST- (,,,) GMH_GPREF () VQ VQ VQ VQ V VUL VQ VQ RN.K/PR RN.K/PR 0 0.U//Y/V RN.K/PR RN.K/PR 0.U//Y/V R.K/ R.K/ R0 0/S/X 0 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V Q N00/SOT S G R 0K//X 0.U//Y/V GP UGP//O/GF OVRNT V V US -INT LK -REQ.V ST0 ST -RF RESERVE S0.V S S_ST S S.V _ST VQ /-E VQ -IRY UXV RESERVE.V -EVSEL VQ -PERR -SERR /-E VQ 0 VQ _ST0 VQ VREF_G V -TYPEET RESERVE US- -INT -RST -GNT.V ST RESERVE -PIPE -WF S.V S -S_ST S S 0.V -_ST /-E VQ 0 VQ -FRME.V -TRY -STOP -PME PR VQ /-E0 VQ -_ST0 VQ 0 VREF_G RESERVE RESERVE RESERVE RESERVE.V RESERVE UXV.V P//N/0V/X E 0U//V/F R 0K/ 0.U//Y/V 0.U//Y/V 0.U//Y/V R 0/S/X R.K/ R.K/ 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0.U//Y/V R 0// R 00// 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V R.K/ R.K/

12 ** IH PIN, Trace length can't Exceed 0." X trace width WITH HULINK TRE *This two parts must place near to IH S_IRQ HX/Orange/X (,,) _[0..] SERIRQ (,,) _E0- (,,) _E- (,,) _E- (,,) _E- (,,) EVSEL- (,,) FRME- (,,) IRY- (,,) TRY- (,,) STOP- (,,) PR (,,,,) PIRST- (,,) PLOK- (,,) SERR- (,,) PERR- (,) PIPME- () PRI_WN- () GNT- () IH (,,) GPI (,,) GPI () GPI (,) LPPME- () GSMI- () GPO0 () GPO (,) GPO (,) GPO _[0..] GPI GPI GPI GPI GPO _ _ R / 0P//N/0V/X Y W W Y Y W W Y Y Y V V U W U Y U U W0 T Y0 T 0 Y V W V W W W Y Y M L W N N N Y W L U E0# E# E# E# EVSEL# FRME# IRY# TRY# STOP# PR PIRST# PLOK# SERR# PERR# PME# GPI0/REQ# GPO/GNT# PILK GPI/PIRQE# GPI/PIRQF# GPI/PIRQG# GPI GPI GPI GPI GPO GPO GPO0 GPO GPO GPO GPIO GPIO ON 0 ON 0 0M# PUSLP# R FERR# IGNNE# INIT# INTR NMI SMI# 0 SLK# RIN# 0GTE PUPWRG HL0 HL HL HL HL HL HL HL HL HL HL0 HL HL_ST HL_ST# HLOMP HUREF PIRQ# PIRQ# PIRQ# PIRQ# IRQ IRQ PILK PI0 PI SERIRQ REQ0# REQ# REQ# REQ# REQ# GPI/REQ#/REQ# GNT0# GNT# GNT# GNT# GNT# GPO/GNT#/GNT# LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_LK LN_RSTSYN P P P N F N0 P N N R R T 0 P L M M R T R L G G H F F F G H HL0 HL HL HL HL HL HL HL HL HL HL0 HL HL[0..0] R0 0.// 0M- () PUSLP- () FERR- () IGNNE- () HINIT- (,) INTR () NMI () SMI- () SLK- () KRST- () 0GTE () PWR () PIRQ- (,,,) PIRQ- (,) PIRQ- (,,) IRQ () IRQ () SERIRQ () HL[0..0] () HLST () HLST- () HUREF () REQ0- () REQ- () REQ- (,) REQ- (,) REQ- (,) REQ- () GNT0- (,) GNT- () GNT- (,) GNT- (,) GNT- (,) GNT- () NR_RX0 () NR_RX () NR_RX () NR_TX0 () NR_TX () NR_TX () NR_LK () NR_RST () R R R RN 0K/PR/X 0/S/X 0/S/X 0/S/X GPI FOR GP/IMM OVER VOLTGE SUPPORT HIGH : ISLE LOW : ENLE VUL SERIRQ 0GTE GPO KRST- GPI GPI GNT- PIRQ- PIPME- PIRST- GPI GPI PI_IH () PI0 () PI () PIRQ- REQ- GNT- R0 R0 R0.K/ RN.K/PR RN.K/PR.K/.K//X P//N/0V/X IH_ HUREF 0.0U//X/0V S 0.U//Y/V GIGYTE ORP. IH / Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

13 RTV 0.0U//X/0V U//Y/0V VMOS VS REF 0 N/S R0 K/ P//N/0V R M/ R 0M/ X.K/0PPM N P/P RN K/PR P//N/0V RTV N P/P () GPO (,) LFRME- (,) THRMO- (,) SLP_S- () SLP_S- (0,) PWROK () PWRTN- (0) RI- () RSMRST- (,,0,,) SMT (,,0,,) SMLK (0) GPI R0.K/ () IHV () IHLK () USLK () USO- () _RST- (,) _SYN (,) _ITLK (,) _SOUT (,) _SIN0 () _SIN (0) SPKR (,) L0 (,) L (,) L (,) L () LRQ0- () USP0 () USP0- () USP () USP- () USP () USP- () USP () USP- RN K/PR RN RN RN RN GPO SUSTT- SUSLK GPI GPI GPI INTRUER RTRST- VIS R / R / _SIN0 _SIN () EES () EEI () EEO () EESK RN /PR /PR /PR /PR /PR U W GPO V GPO THRM# W SLP_S# SLP_S# R0 PWROK Y RSM_PWROK W PWRTN# RI# R V P R P Y W N W Y W Y 0 0 W Y0 Y W0 K K J J RSMRST# U Y SUSSTT# SUSLK SMT SMLK GPI/SMLERT# Y GPI M GPI/PIRQH# T INTRUER# T0 RTRST# T VIS U RTX T RTX LK M LK P0 LK _RST# _SYN _ITLK _SOUT _SIN0 _SIN SPKR Y L0/FWH0 W L/FWH L/FWH L/FWH Y LRQ0# W LRQ# LFRME#/FWH FS0/FWH USP0_P USP0_N USP_P USP_N USP_P USP_N USP_P USP_N O0# O# O# O# EE_S EE_IN EE_OUT EE_SHLK RT PU PU V VREF_SUS M0 K VREF VREF 0.U//Y/V PS# SS# PS# SS# P0 P P S0 S S PREQ SREQ PK# SK# PIOR# SIOR# PIOW# SIOW# PIORY SIORY P0 P P P P P P P P P P0 P P P P P E E F0 F E G F G G G0 H H J J K L0 M M L L K K0 J J0 H H0 S0 S S 0 S 0 S S S E0 S S S 0 S0 0 S S S S S SMLINK0 SMLINK VRMPWRG 0/TLOW U V0 U0 P0 P P S0 S S P0 P P P P P P P P P P0 P P P P P S0 S S S S S S S S S S0 S S S S S 0.U//Y/V R 0K/ PS- () SS- () PS- () SS- () P[0..] S[0..] PREQ () SREQ () PK- () SK- () PIOR- () SIOR- () PIOW- () SIOW- () PIORY () SIORY () P[0..] S[0..] SMLINK0 () SMLINK () PWROK (0,) VUL P[0..] () S[0..] () P[0..] () S[0..] () () GSMI- (,) GNT0- () GNT- (,) GPO (,) GPO () GPI (,) LPPME- SUSLK RI- SMT SMLK GPI GNT- INTRUER GPI FOR SMRT R REER SUPPORT HIGH : ISLE VUL LOW : ENLE GSMI- R.K/ GPI GPO GPI GPI GPO GPIO,, : HIGH REV:.0 SLP_S- SLP_S- GPO SUSTT- SMLINK0 SMLINK GPI RSMRST- PWROK R0.K//X R0.K//X R0.K//X R0.K//X R R R R R.K//X.K/ R R0 R0 R VMOS RN.K/PR RN.K/PR.K/.K/.K/ 0.U//Y/V.K//X.K//X.K//X.K//X R0 0K/ R0 K/ 0.U//Y/V VUL VS IH_ () RTV - : LER MOS - NORML S VUL RV-0/S R 0/ R 0/ VT () 0.U//Y/V 0.U//Y/V 0.U//Y/V USLK 0P//N/0V/X _ITLK 0 0P//N/0V/X U//Y/0V R0 K/ RTRST- S0 IHV 0P//N/0V/X VIS 0 R0 0.0U//Y/V K/ LR_MOS JPX/H/X 0.U//Y/V PWROK 0P//N/0V/X RV-0/S 0.U//Y/V 0.U//Y/V RN0.K/PR 0.U//Y/V T TR0 U//Y/0V R0 K//X GIGYTE ORP. IH / Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

14 .V/.V Power Sequencing ircuit G-OXT.0 IH US PORT GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of VUL VUL VORE VQ VIMM VUL VUL VUL VUL VUL VUL VUL N00/S Q N0/SOT/X Q N0/SOT/X S 0.0U//X/0V R0 0//X R0 0//X R0 0//X 0 N00/S N/S IT IT IT IT IT IT IT IT00 IT IT IT IT IT 0.0U//X/0V 0.U//Y/V 0.U//Y/V 0.U//Y/V IT IT U IH_ 0 0 E E E E J0 J J J J K K0 K K K K K L0 L L L L L M0 M M M M M N0 N N N N N P0 P P P J P P U IH_ R T U V V V V R P J H G F E E E E E F G H J V V E P V K L 0 V V V U T P P P P P P P P0 P P P P P P P P P P0 PX PX X X US US S S S PS PS 0.U//Y/V 0.U//Y/V 0 0.0U//X/0V 0 0.0U//X/0V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.0U//X/0V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.0U//X/0V E 0U//V/F 0.0U//X/0V 0.U//Y/V 0.U//Y/V 0.U//Y/V S 0.U//Y/V 0.0U//X/0V 0.U//Y/V IT IT IT IT IT0 IT IT0 IT0 IT S 0.U//Y/V R0 0/

15 () _PWG R 0//X Q FNN/SOT/X RN 0/PR KV F F00//S 0.U//Y/V FS FS0 FS RN.K/PR KV 0.0U//X/0V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.0U//X/0V 0.U//Y/V 0.U//Y/V S 0.U//Y/V/X S0 0.U//Y/V/X S 0.U//Y/V/X S 0.U//Y/V/X KV F 0.U//Y/V F0//S 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V IS0F Q mount FNN R mount 0 ohm RN unmount 0 ohm PR umount N umount N R0 unmount 0 ohm IS00F Q unmount FNN R unmount 0 ohm RN mount 0 ohm PR mount N unmount N R0 unmount 0 ohm FS R 0K/ KV KV R K/ R K/ 00_- (,) FS R 0K/ _00- (,) 0 P//N/0V X.M/P/ KV KV KV (,) _00- () GMHV () IHV () GPLK () LP () IH () PLK () PLK0 () PLK () PLK () FWH () PLK (,,,,) PIRST- (,,0,,) SMLK (,,0,,) SMT () MEMLK0 () MEMLK (,) SLP_S- R0 / R0 / R0 / RN RN RN RN RN RN RN P//N/0V RN R0 R 0K/ R 0/S/X R 0/S/X R 0/ R 0/ N/S/X /PR /PR /PR /PR /PR /PR /PR /PR 0//X GMH IH FS0 FS SPLK 0 0 U VREF X X REF V V-0 V- V- VV VPI FS0/PILK0 FS/PILK PILK PI PILK PILK PILK VPI PILK PILK PI P# SLK ST VSR SRM SRM0 SR REF0/FS VLPI IOPI VLPU PULK0 PULK LPU SR SRM0 SRM SRM VSR SRM SRM SRM SR SRM SRM SRM_F VSR MHZ/FS MHZ/FS V VSR SRM SRM SR IS00F FS LKWR FS FS R0 / R / R / R 0/ R / RN0 0/PR RN 0/PR R / R / R //X R / R 0/ R 0/ IHLK () PI_PU () PI_IH () PUHLK () GMHHLK () MEMLK (0) MEMLK (0) MEMLK0 (0) MEMLK (0) MEMLK () MEMLK () MEMLK () MEMLK () LK_WR () LP () OTLK () USLK () MEMLK () MEMLK () R 0K/ KV R K/ R.K/ Q N0/SOT SM_S0 (,,,0) () _PWG N/S GMH IH GMHV PUHLK GMHHLK IHV PI_PU PI_IH 0P//N/0V 0P//N/0V 0P//N/0V/X 0P//N/0V 0P//N/0V 0P//N/0V/X 0P//N/0V/X P//N/0V/X LKWR OTLK USLK PLK GPLK IH FWH LP LP 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X 0P//N/0V/X MEMLK0 MEMLK MEMLK MEMLK MEMLK MEMLK MEMLK MEMLK MEMLK MEMLK MEMLK0 MEMLK 0 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V 0P//N/0V For Support Tualatin PI_PU Q0 N0/SOT R 0// R.K/ TUL () (,) _00- Size ocument Number Rev ustom.0 R 0K/ R Q N0/SOT GIGYTE ORP. LOK GEN. G-OXT 0/S/X ate: Wednesday, October, 00 Sheet of 0 00_- (,)

16 G-OXT.0 PI SLOT / GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of GPI GPI PIRQ- PIRQ- SLOTRST- GNT- REQ- PIPM- 0 E- _0 _E- FRME- IRY- TRY- EVSEL- STOP- PLOK- PERR- SERR- PR _E- 0 _E0-0 K REQ_ PI _ GNT0- PI_0 PIPM- _0 _0 _ REQ _0 _ REQ0- _0 [0..] FRME- IRY- TRY- EVSEL- STOP- PLOK- PERR- SERR- PIRQ- GPI REQ_ REQ_ PIRQ- K PR SLOTRST- PIRQ- THRMO- REQ_ REQ_ PERR- (,,) SERR- (,,) STOP- (,,) PR (,,) _E- (,,) _E- (,,) _E- (,,) PLOK- (,,) _E0- (,,) FRME- (,,) TRY- (,,) IRY- (,,) PIRQ- (,,) PIRQ- (,,,) EVSEL- (,,) SLOTRST- (,,,) K (,) PI_0 (,) PI_ (,) GPI (,,) GPI (,,) PLK0 () PLK () _[0..] (,,) REQ0- () REQ- (,) REQ- (,) REQ- () REQ_ () REQ_ () GNT- (,) GNT- (,) GNT- () PIPME- (,) PIPM- (,) GNT- () PIRQ- (,) GNT0- (,) THRMO- (,) GNT- (,) REQ- (,) REQ- () -V V -V V VUL VUL V -V RN.K/PR 0 0.U//Y/V 0.U//Y/V E U//V/ PI PI0/O/GF TRST# V TMS TI V INT# INT# V LKRUN V(I/O) RESERVE UXV RST# V(I/O) GNT# PME# 0.V ISEL. 0.V FRME# TRY# STOP#.V SONE SO# PR.V /E0#.V 0 V(I/O) REQ# V V -V TK TO V V INT# INT# PRSNT# RESERVE PRSNT# RESERVE LK REQ# V(I/O).V /E#.V /E# IRY#.V EVSEL# LOK# PERR#.V SERR#.V /E# 0.V V(I/O) K# V V N/ N/ N/ N/ P//N/0V/X R 0/S/X RN.K/PR RN.K/PR 0.U//Y/V P//N/0V/X R0.K/ R0.K/ R0.K/ R0.K/ RN.K/PR 0.U//Y/V PI PI0/O/GF TRST# V TMS TI V INT# INT# V LKRUN V(I/O) RESERVE UXV RST# V(I/O) GNT# PME# 0.V ISEL. 0.V FRME# TRY# STOP#.V SONE SO# PR.V /E0#.V 0 V(I/O) REQ# V V -V TK TO V V INT# INT# PRSNT# RESERVE PRSNT# RESERVE LK REQ# V(I/O).V /E#.V /E# IRY#.V EVSEL# LOK# PERR#.V SERR#.V /E# 0.V V(I/O) K# V V N/ N/ N/ N/ R.K/ R.K/ RN.K/PR RN.K/PR

17 G-OXT.0 PI SLOT / GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of PIRQ- PIRQ- GPI GPI SLOTRST- PIPM- 0 0 E- _0 0 _E- FRME- IRY- TRY- EVSEL- STOP- PLOK- PI_0 PERR- PI_ SERR- PR E- 0 _0 _E0-0 0 REQ_ K REQ [0..] REQ- (,) PERR- (,,) SERR- (,,) GNT- (,) STOP- (,,) PR (,,) PLOK- (,,) FRME- (,,) TRY- (,,) IRY- (,,) K (,) REQ- (,) GNT- (,) PIRQ- (,,) PIRQ- (,,,) PLK () PLK () PIPM- (,) _E- (,,) _E- (,,) _E- (,,) _E0- (,,) SLOTRST- (,,,) EVSEL- (,,) PI_0 (,) PI_ (,) GPI (,,) GPI (,,) REQ_ () REQ_ () _[0..] (,,) -V V -V V VUL VUL V -V PI PI0/O/GF TRST# V TMS TI V INT# INT# V LKRUN V(I/O) RESERVE UXV RST# V(I/O) GNT# PME# 0.V ISEL. 0.V FRME# TRY# STOP#.V SONE SO# PR.V /E0#.V 0 V(I/O) REQ# V V -V TK TO V V INT# INT# PRSNT# RESERVE PRSNT# RESERVE LK REQ# V(I/O).V /E#.V /E# IRY#.V EVSEL# LOK# PERR#.V SERR#.V /E# 0.V V(I/O) K# V V N/ N/ N/ N/ PI PI0/O/GF TRST# V TMS TI V INT# INT# V LKRUN V(I/O) RESERVE UXV RST# V(I/O) GNT# PME# 0.V ISEL. 0.V FRME# TRY# STOP#.V SONE SO# PR.V /E0#.V 0 V(I/O) REQ# V V -V TK TO V V INT# INT# PRSNT# RESERVE PRSNT# RESERVE LK REQ# V(I/O).V /E#.V /E# IRY#.V EVSEL# LOK# PERR#.V SERR#.V /E# 0.V V(I/O) K# V V N/ N/ N/ N/ 0.U//Y/V 0.U//Y/V 0 0.U//Y/V E 0U//V/F/X 00 0.U//Y/V

18 - : WRITE PROTET - : NORML G-OXT.0 PI SLOT & FWH GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of 0 _0 0 PI_0 PI _0 0 _[0..] HINIT- FGPI FGPI PIRST- PIRST- FGPI FGPI I SET PET HINIT- L0 L L L FGPI LFRME- FWH VPP WPROT PERR- (,,) SERR- (,,) STOP- (,,) PR (,,) SLOTRST- (,,,) _E- (,,) _E- (,,) _E- (,,) PLOK- (,,) _E0- (,,) FRME- (,,) TRY- (,,) IRY- (,,) K (,) PIRQ- (,,) PIRQ- (,,,) PLK () PIPM- (,) EVSEL- (,,) REQ- (,) GNT- (,) GPI (,,) GPI (,,) _[0..] (,,) HINIT- (,) SET () PET () GPO () LFRME- (,) L (,) FWH () L (,) L (,) L0 (,) PIRST- (,,,,) SMLINK0 () SMLINK () PI_0 (,) PI_ (,) -V V VUL VMOS V -V P//N/0V/X U PLPFWH/LF VPP RST# FGPI FGPI FGPI FPGI0 WP# TL# I I I I0 FWH0 FWH FWH FWH RFU RFU RFU RFU RFU FWH INIT# I(VIL) FGPI LK IOS_WP JPX/H/X P//N/0V/X R.K/ R0.K/ R0 0K//X R0 0//X R0 0//X 0.U//Y/V 0 0.U//Y/V E 0U//V/F 0.U//Y/V 0 0.U//Y/V E0 0U//V/F/X R 0K/ R.K/ 0.U//Y/V P//N/0V/X PI PI0/O/GF TRST# V TMS TI V INT# INT# V LKRUN V(I/O) RESERVE UXV RST# V(I/O) GNT# PME# 0.V ISEL. 0.V FRME# TRY# STOP#.V SONE SO# PR.V /E0#.V 0 V(I/O) REQ# V V -V TK TO V V INT# INT# PRSNT# RESERVE PRSNT# RESERVE LK REQ# V(I/O).V /E#.V /E# IRY#.V EVSEL# LOK# PERR#.V SERR#.V /E# 0.V V(I/O) K# V V N/ N/ N/ N/ R 0/S/X 0 0.U//Y/V R 0K//X RN 0K/PR R 0K/ Q N0/SOT/X E

19 STU TRE LENGTH S SHORT S POSSILE R K/ R K/ IERST- IE- IETS- HLE- (0) R 0/ Q N0/SOT E N/S N/S (,,,,) PIRST- R0 0K/ Q N0/SOT E R0 K/ R 0/ Q N0/SOT E SLOTRST- SLOTRST- (,,,) () P[0..] PRIMRY IE ONNETOR P[0..] XX0/0/R 0 0.0U//Y/V () S[0..] IE RST- P P P P P P0 P 0 P P P P P P P P0 P () PREQ () PIOW- () PIOR- IEPU0 () PIORY 0 () PK- () IRQ () P PET () () P0 P () () PS- PS- () IE- 0 () SREQ () SIOW- () SIOR- () SIORY () SK- () IRQ () S () S0 () SS- SEONRY IE ONNETOR S[0..] RST- S S S S S S S S0 IETS- IE XX0/0/W S S S0 S S S S S IEPU 0.0U//Y/V SET () S () SS- () IERST- R / IERST- R / RST- RST- R K/ R.K/ PIORY IRQ R K/ R.K/ SIORY IRQ R 0K/ R.K/ R 0/ P PREQ IEPU0 R 0K/ R.K/ R0 0/ S SREQ IEPU GIGYTE ORP. IE ONNETOR Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

20 P Z UZZER/0/V//X Z N/S R0 / R0 / Q N/SOT P P R.K/ SPKR () () PWRLE E Q N0/SOT VS PWRLE VS HLE R00 0/ R.K/ R 0/ 0 F_PNEL GN N H P- P- P PW PW N N G- GN N H- SP- Z- Z SP RE RE N G 0 JPX/,0,,0,/H 0 0P//N/0V GPI () HLE- HLE- () SP- 0.U//Y/V RESET P R K/ Q N/SOT Q N/SOT R.K/ R.K/ EEP- () R.K/ R 0/S/X PWROK PWROK (,) () PWRTSW- PWRTSW- U//Y/0V 0 000P//X/0V R0 0K/ Q0 N0/SOT SOT PWOK PWOK (,,) P P G Q N0/SOT R0 0/ R 0K/ R 0/S/X SUSLE SUSLE () E () NRI- () NRI- N/S N/S R0 K/ E U//V//X RI- RI- () Q N0/SOT E IMM LE VIMM VS 0.U//Y/V/X R 0/ WOL WOLX 0.U//Y/V/X R0 0K/ R 0K/ RI- Q0 N0/SOT E 0.U//Y/V/X RI- () LE LE/Y/S R 0K/ LE LE/Y//X RM_LE JPX/H/X GIGYTE ORP. PNEL & STR LE & RI Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet 0 of 0

21 HP_OUTR HP_OUTL HP_OUTR () HP_OUTL () Q L0//TO/X G V V O I MONO_OUT MONO_OUT () SPIF HEER /X V E0 U//V//X 0.U//Y/V/X U0 0 (,) _SOUT (,) _ITLK (,) _SIN0 (,) _SYN () U_RST UV UV XTLIN XTLOUT R //X R //X 0 V XTL_IN XTL_OUT ST_OUT IT_LK ST_IN V SYN RESET# P_EEP N N TEST TEST TEST TEST TEST TEST N V MONO_OUT LINE_OUT_R LINE_OUT_L N N VR VR 0 FILT FILT N VREF V LINE_OUTR LINE_OUTL U_REF U_REF () V LINE_OUTR () LINE_OUTL () R UV.//X PHONE UX_L UX_R VIEO_L VIEO_R _L N _R MI MI LINE_IN_L LINE_IN_R 0 RELTEK 0/X.U//Y/V/X 000P//X/0V/X 000P//X/0V/X U//Y/0V/X U//Y/0V/X 0.U//Y/.V/X LINE_IN_R ().U//Y/.V/X LINE_IN_L () 0.U//Y/V/X X.M/0P//X XTLIN XTLOUT U//Y/0V/X 0.U//Y/V/X 0.U//Y/V/X MI () _R () () P//N/0V/X P//N/0V/X 0.U//Y/V/X 0.U//Y/V/X UX_R _L () UX_R () 0.U//Y/V/X UX_L UX_L () 0.U//Y/V/X PHONE PHONE () UV V 0.U//Y/V/X 0.0U//X/0V/X 0.U//Y/V/X 0.U//Y/V/X GIGYTE ORP. OE Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

22 W shunter -: close -: close G-OXT.0 PHONE JK ustom 0 Wednesday, October, 00 GIGYTE ORP. Size ocument Number Rev ate: Sheet of PHONE MONO_OUT INSE_R INSE_L RER_L RER_R INSE_L INSE_R FRONT_L FRONT_L MI MI MI FRO_MI FRO_MI FRONT_L RER_L RER_R PHONE () MONO_OUT () UX_L () UX_R () _R () _L () () LGPS () LGPS () LGPY () LGPX () LGPX () LGPS () LMSI () LGPS () LMSO () LGPY () MI () LINE_IN_L () LINE_IN_R () LINE_OUTL () LINE_OUTR () HP_OUTR () HP_OUTL () U_REF () PWOK (0,,) GV V VUL V 000P//X/0V/X Q N0/SOT/X R 0K//X _IN WFX//X 000P//X/0V/X 000P//X/0V/X 0 000P//X/0V/X 0 RN 0/PR/X RN 0/PR/X RN 0/PR/X RN 0/PR/X R 0K//X RN.K/PR/X RN.K/PR/X RN.K/PR/X RN.K/PR/X 000P//X/0V/X 000P//X/0V/X 0 000P//X/0V/X R.K//X UIO_ /GM/X 0.U//Y/V/X UIO_ /GM/X 0 000P//X/0V/X R0 K//X R K//X R0.K//X 000P//X/0V/X R 0//X UIO_ /GM/X 0 0.U//Y/V/X 00P//N/0V/X 00P//N/0V/X 0 00P//N/0V/X 00P//N/0V/X R0.K//X 0 0.U//Y/V/X E 00U//0V//X E 00U//0V//X 000P//X/0V/X E 00U//0V//X E 00U//0V//X UX_IN WFX/W/X 000P//X/0V/X N/S/X 0.U//Y/V/X 0 R0 0//X 0 0.U//Y/V/X GME /GM/X 0 RN.K/PR/X R.K//X 0.0U//X/0V/X 0.0U//X/0V/X 000P//X/0V/X 0.0U//X/0V/X 0.0U//X/0V/X R.K//X R 0//X 000P//X/0V/X 00P//N/0V/X 00P//N/0V/X P//X/0V/X R K//X R K//X U//Y/0V/X 000P//X/0V/X 000P//X/0V/X R 0//X R0 0//X TEL WFX/G/X R 00//X 0.U//Y/V/X R 00//X 000P//X/0V/X R.K//X F_UIO JPX/,/H/X 0 R.K//X 0.U//Y/V/X 0 SOT Q N/SOT/X SOT Q0 N/SOT/X

23 () NR_TX () NR_RST () NR_RX () NR_RX0 VUL -V 0 NR RESV RESV RESV RESV RESV LN_TX LN_RSTSYN LN_RX LN_RX0 RESV VUL US_O# -V.V NR RESV RESV RESV RESV LN_TX LN_TX0 LN_LK LN_RX RESV US US- V.UL V NR_TX () NR_TX0 () NR_LK () NR_RX () 0 0 () EEI EE_OUT EE_IN EEO () () EESK EE_SHLK EE_S EES () _SM _SM0 SM SM SM_0 SM_ SMT (,,0,,) SMLK SM_SL SM_S SMT (,,0,,) _RST- () PRI_WN- PRIMRY_N# _RESET# _RST- () RESV (,) _SYN R / _SYN _ST_IN _SIN () R / (,) _SOUT _SIN0 (,) R / _ST_OUT _ST_IN0 0 0 (,) _ITLK _ITLK NR/O/GF 0 V VUL 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 00P//N/0V/X PLESE ONNET GPI PIN VUL VUL U_RST R 0/S/X _RST- () U_RST _RST- () PRI_WN- R.K/ R 0K//X PRI_WN- - : ENLE - ISLE OE_EN R0 K//X N/S/X R0 K//X _SM0 _SM _SM _SIN0 _SIN R 0K/ R 0K/ R 0K/ R 0K/ R 0K/ JPX/H/X GIGYTE ORP. FWH Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

24 () - () RI- () TS- () TR- () RTS- () SR- () TX () RX () - () RI- () TS- U P0 P P P P P P P P[0..] ST- F- ERR- INIT- SLIN- K- P[0..] () ST- () F- () ERR- () INIT- () SLIN- () K- () PWRTN- VUL R0.K/ U//Y/0V () TR- () RTS- () SR- () TX () RX () FNIO () FNIO () FNIO (0) EEP- (,) VI (,) VI (,) VI (,) VI (,) VI0 () LGPS () LGPS () LGPY () LGPX () LGPS () LGPS () LGPY () LGPX () LMSO () LMSI () IRTX (,,,,) PIRST- () LRQ0- SRRST SRFET- SRIO SRLK LPP- PIRST TR# RTS# SR# SOUT SIN FN_T FN_TL FN_T/GP FN_TL/GP FN_T/GP FN_TL/GP WTI#/GP VI/GP VI/GP VI/GP VI/GP VI0/GP0 JS/GP JS/GP JSY/GP JSX/GP JS/GP JS/GP JSY/GP JSX/GP0 MII_OUT/GP MII_IN/GP IRTX/GP SRRST/GP SRFET#/GP SRIO/GP SRLK/GP LPP# LRESET# LRQ# TS# RI# # SIN SOUT SR# RTS# TR# TS# RI# # P P P P P P P P0 ST# F# ERR# INIT# SLIN# K# SERIRQ LFRME L0 L L L KRST# G0 PILK LKRUN#/GP0 LKIN ENSEL# MTR# MTR# RV# RV# WT# IR# STEP# HSEL# WGTE# RT# TRK0# INEX# WPT# USY PE SLT VIN0 VIN VIN VIN VIN VIN VIN VIN VREF TMPIN TMPIN TMPIN IRRX/GP SRPRES#/GP0 MLK MT KLK KT SLK/GP0 ST/GP RING#/GP PSON#/GP PNSWH#/GP PME#/GP PWRON#GP PSIN/GP IRRX/GP VT OPEN# H IRTX/GP SKHG# IT/VER X SRPRES- VS USY () PE () SLT () VIN0 () VIN () VIN () VIN () VIN () VIN () VREF () TMPIN () TMPIN () TMPIN (,) IRRX () MLK () MT () KLK () KT () PWRLE (0) THRMO- (,) SUSLE (0) PS_ON- () PWRTSW- (0) LPPME- (,) PWRTN- () SLP_S- (,) IRRX () VT () OPEN- () IRTX () SKHG- () FOR STR SELET L:ENLE H:ISLE GP0 R.K//X R.K//X R0.K//X R.K/ SRIO SRFET- () SERIRQ (,) LFRME- (,) L[0..] () KRST- () 0GTE () LP () LP L[0..] GP0 L L L L0 WPT- () INEX- () TK00- () RT- () WGTE- () SIE- () STEP- () IR- () WT- () RV- () RV- () MOTE- () MOTE- () ENSEL- () R0.K/ R0.K/ VT PIRST- LRQ0- LPP- 0.0U//Y/V P//N/0V/X RN 0K/PR VI0 VI VI VI R 0K/ VI SRIO SRPRES- SRFET- SRLK SMRT R SR 0 JPX//H/X SRRST R.K//X VS SLP_S- R 0K/ Q N0/SOT/X E PS_ON- () 0.U//Y/V 0.U//Y/V 0.U//Y/V VS 0.U//Y/V (PIN HOUSING) Size ocument Number Rev ustom.0 GIGYTE ORP. LP I/O G-OXT ate: Wednesday, October, 00 Sheet of 0

25 PRT PORT OM PORT G-OXT.0 OM & IR & LPT PORT &FLOOPY GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of P[0..] LPT LPT LPT0 LPT LPT P LPT LPT LPT ST- P P P LPT P0 LPT P LPT LPT P LPT0 LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT LPT - N- SR- NSR- RX NRX RTS- NRTS- TX NTX TS- NTS- TR- NTR- RI- NRI- NTS- NRX N- NTX NRI- NRTS- NTR- NSR- SR- TS- NRTS- NRX RTS- NTX RX NTR- RI- TR- - NRI- TX N- NTS- NSR- NSR- NRTS- N- NTS- NRI- NTR- NRX NTX NRTS- NSR- NRI- NRX N- NTR- NTX NTS- NTS- NTX NRI- NTR- NSR- NRX NRTS- N- LPT LPT F- LPT LPT LPT P P[0..] () INIT- () SLIN- () USY () PE () F- () ERR- () K- () P () ST- () P () SLT () - () SR- () RX () RTS- () TX () TS- () TR- () RI- () - () TS- () TR- () RTS- () SR- () RI- () RX () TX () NRI- (0) NRI- (0) RV- () MOTE- () SKHG- () WGTE- () WT- () RV- () RT- () IR- () SIE- () INEX- () MOTE- () TK00- () ENSEL- () WPT- () STEP- () V V -V -V 0.U//Y/V N 0P/P LPT LPT/P 0 0 N/S N 0P/P R 0/ RN /PR 0.U//Y/V N0 0P/P N 0P/P N 0P/P U TI G/TSSOP 0 0 R R R Y Y R Y V RY RY RY RY R -V RY V RN.K/PR RN0 /PR RN0 /PR RN0 /PR RN0 /PR RN 0/PR F XX// OM OM/P 0 0.U//Y/V N 0P/P N 0P/P RN.K/PR 0.U//Y/V U TI G/TSSOP 0 0 R R R Y Y R Y V RY RY RY RY R -V RY V 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.U//Y/V N 0P/P RN /PR RN /PR RN /PR RN /PR RN.K/PR R.K/ RN.K/PR 0P//N/0V OM OM/P

26 G-OXT.0 HRWRE MONITOR GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of VREF VREF VREF OPEN- () RTV () VREF () TMPIN () TMPIN () TMPIN (,) VIN () VIN0 () VIN () VIN () VIN () VIN () FNIO () FNIO () FNIO () VORE V VS V V V R0 M/ R 0K/ R 0K/ R 0K/ R.K/ R 0K/ 0.U//Y/V/X 0.U//Y/V/X 0 0.U//Y/V 0.U//Y/V/X 0 0.U//Y/V/X 00P//X/0V/X R0 0K/ R00 0K//X 00P//X/0V/X 0.U//Y/V/X U//Y/0V 00P//X/0V/X R0 0K/ 0.U//Y/V/X U//Y/0V V S PU_FN FNX/W R.K// R00 0K/ 0 0.0U//X/0V/X V S POWER_FN FNX/W/X SE_OPEN JPX/H/X RS HRK/X V S SYS_FN FNX/W R 0K/ R0 0K/ R 0K///X R 0K// R 0K/ R 0K/ RS HR00/X R 0K// R 0K/

27 VUL FUSE GV RER US PORT E 0U//V/F F FUSE/./V/ F F00.mm/IP 0 0.U//Y/V Q N00/SOT/X R0.K//X S G V () USP0 () USP () () USP- USP0- RN /PR RUSP- RUSP RUSP0- RUSP0 RUSP0 RUSP RUSP- RUSP0- FUSE US UP OWN 0 US/S//H 0.U//Y/V VS VS R0 K/ VS V R0.K/ N P/P FUSE 0.U//Y/V (0,,) PWOK VS R0 K/ - U LM/TO - U LM/TO FRONT US PORT R0 K/ 0.U//Y/V VUL [ ƒr ~fi Q SIV/PMOS/TSOP- VS S G G S Q0 N0/NMOS/TO E U//V/ FUSP- FUSP FUSE F_US 0 JPX/,/H FUSE FUSP FUSP- E U//V/ () USP- () USP () USP () USP- RN /PR FUSP- FUSP FUSP FUSP- FUSE RN.K/PR () MLK () MT () KLK () KT MSLK MST KLK KT () IRRX () IRTX 0.U//Y/V IR 0 JPX/H VS IRRX () IRTX () FUSE R0 0K/ USO- USO- () E 0 R0 0K/ 0U//V/F U//Y/0V N P/P RN PR N 0P/P MST MSLK KT KLK K/MS 0 MS K PS/P/S/ FUSE FUSE 0.U//Y/V/X 0 0.U//Y/V 0.U//Y/V GIGYTE ORP. K & PS MOUSE & IR & US Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

28 TX POWER ONNETOR OVQV OVQV.V.V PLEMENT SEPRTE SEMTEH PIN EFINE SEMTEH PIN EFINE G-OXT.0 TX ONN. & STR PWR GIGYTE ORP. ustom 0 Wednesday, October, 00 Size ocument Number Rev ate: Sheet of PS_ON- PWOK RSMRST- RSMRST- () PS_ON- () PWOK (0,,) PIN () GPO () GPO (,) SLP_S- () GPO (,) GPO0 () VUL V VS -V -V VS V VS -V VMOS VMOS VIMM VS VUL VS VIMM VIMM VIMM VQ VUL VUL VUL VUL V R ///X R 00///X 0 N/S/X N/S/X N/S/X Q0 P/TO E 0U//V/F N00/S N00/S R00 0/ R00 0/ RN 0/PR/X E 0U//V/F/X E 0U//V/F 0.U//Y/V.U//Y/0V N/S R 0K/ 0 0.U//Y/V R0 0K/ 0 0.U//Y/V 0.U//Y/V 0.U//Y/V N/S/X 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V 0.U//Y/V R00 0K//X R00.K//X POWER TX 0 0.V.V V V POK VS V.V -V PSON -V V V 0.U//Y/V 0 0.U//Y/V R.K//X 0.U//Y/V R00 ///X R000 00//X Q0 SSK/SOT R E 0U//V/F E 0U//V/F Q0 SLSK/SOT/X R Q0 0/TO/X R0.// R0 00// E 00U//0V//X E 0U//V/F 0.U//Y/V E U//V//X 0 0.U//Y/V E 0U//V/F E0 0U//V/F 0 0.U//Y/V R K/ Q 0/TO R.K//X R00 0// RN 0/PR/X R00 // R 0//X U//Y/0V RN 00/PR/X G S SOT Q0 N00/SOT R0.K//X R00 0K/.U//Y/0V SOT Q0 N0/SOT 0.U//Y/V R00 K/ 0.U//Y/V Q RL/SOT-/X N N REF N E U//V/ Q0 0/TO/X 0 0.U//Y/V U//Y/0V R0 K/ RN 0/PR/X

29 (,0) PWROK V TUL TUET HIGH TULTIN =.V LOW OPPERMINE =.V E 0U//V/F N/S FN0 R mount 00 ohm R mount 0 ohm R mount K ohm FN0 R mount 0 ohm R mount 0 ohm R mount.k ohm E 0U//0V//X R 0/ VQ S G R 00/ R K/ G P Q 0/TO TO- R 0.U//Y/V 0.0U//X/0V R 0//X 0.U//Y/V R 0K/ S 0//X (,) VI0 (,) VI (,) VI (,) VI (,) VI Q 0/TO G TO- 0 U//Y/V R 0/S/X VI0 VI VI VI VI R0 0/ U P 0 PGOO SS VI0 VI VI VI VI/VImV G F GPG GPF GPTYP U//Y/0V ILIM ROOP HIRV SW LORV VKG VKF VF FN0 P 0 R00 0/S/X R0 K/ R K/ R0./ GTE S SHORT S POSSILE R0./ TO- G TO- TO- G G S L0.UH//V/0/P Q NE/TO Q NE/TO S Q SI0S/SOT S 0. U//Y/0V L.UH//V/0/P R./ 0.0U//X/0V.U//Y/V U//Y/0V E 0U//V/F E 00U//.V/K/X.0V~.V/ E 00U//.V/P E 00U//.V/K E 00U//.V/K VORE E 00U//.V/K/X E 00U//.V/P E 00U//.V/K/X E 00U//.V/P E 00U//.V/P REF FOR FN0 R,R FOR FN0 W R FOR FN0 n W R K/ R 0/S/X Q0 R-L/SOT- E P G U//V//X E 0U//V/F E0 0U//V/F R 0/ R0 0/S/X E 00U//0V/ R 0K/ R K//X () PIN () TYPEET- TYPEET HIGH:VQ=.V TYPEET LOW:VQ=.V R K//X R K//X The Farest from PU R./ VORE TUL R0 K//X Q FNN/SOT/X R K/ G () V () _PWG R 0K/ Q N00/SOT VS VORE R 0K/ S G R K/ Q N0/SOT SOT R K/ TULTIN F N-HIGH OPPERMINE F -LOW S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V/X S.U//Y/0V/X R K/ 0 0.U//Y/V (,) F R 0/S/X TUL TUL () GIGYTE ORP. PWM Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet of 0

30 Model Name: G-OXT Version: 0..dd 0.uF bypass capacitor on U reference voltage pin.removed R K ohm for adjustment VORE feedback voltage.p color change to lue from Gold.dd L-0LUE-0 lue Thunder label.dd ME-OXT-00 English Manual Rev:.0.dd QE-OXT-00 English Quick Installation Rev:.0.el R-U00-00 Front US able with racket.r0 change to.k ohm from K ohm for VUL circuit.u change main source to 0T-00-0 TI LM from 0T-00- Fairchild K 0.U add second source 0T-00-0 Philips LM.U add 0H-00-0 IH FW0 Rev:0 SLF as main source.pi_pu waveform adjustment R change to ohm from ohm el pf capacitor el R0 0 ohm resistor hange R to 0 ohm % resistor from 0 ohm % resistor hange U to IS00F from RTM0-0R add N diode R,R add 0K ohm resistor R add K ohm resistor R add K ohm resistor 0 add 0.uF capacitor Q add N00 Q add N0. Power Improved el E uf V capacitor el E 00uF 0V capacitor E change to 0uF V from 00uF 0V capacitor dd S,S0 and location.dd EMI solution dd, location and both are mount 0pF capacitor hange F to 0LF ohm ead from 0 ohm ead.gme PORT circuit modify dd ~ location Removed N and N location el Q N00 el R0.K ohm resistor.huref voltage quality Improve dd S location and mount 0.uF capacitor.el Q0 second source 0GL-00-0 SL.PU Transient Improved change to uf from 0.0uF capacitor R0 add 0 ohm resistor el R K ohm resistor dd R0, R0 location and both are mount. ohm resistor hange R0 to K ohm from 0K ohm resistor.pilk0 clock Improved el pf capacitor 0.Solved Ring Indicate can't wakeup issue el E uf V capacitor._rst- signal quality Improved dd location. Power Improved dd S~S location and all are mount 0.uF capacitor Version:.0.udio precision Line-in record fail issue 0, change to.uf.v from uf 0V capacitor.rt too fast issue,0 change to pf from 0pF apacitor.el U Socket0 main source MP S-00- and second source FI S-00-.dd U Socket0 main source MP S-00-.el X X'TL second source Fujicom XH--00.F compatible issue hange R to 0 ohm from.k ohm resistor hange RN to 0 ohm PR from.k ohm PR resistor.udio precision Line-in record passband fail issue hange R,R to K ohm from 0K ohm resistor.front audio priority issue R,R0 trace cut off GIGYTE ORP. HISTORY Size ocument Number Rev ustom.0 G-OXT ate: Wednesday, October, 00 Sheet 0 of 0

GIGABYTE GA-8I848P Schematics

GIGABYTE GA-8I848P Schematics GIGYTE G-IP Schematics Revision.0 SHEET TITLE SHEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER SHEET OM & P MOIFY HISTORY LOK IGRM P_ P_ P_ SPRINGLE HOST SPRINGLE R SPRINGLE GP, HU, S, VG SPRINGLE PWR R, HNNEL R

More information

VIA Apollo ProMedia Board Schematics

VIA Apollo ProMedia Board Schematics VI pollo ProMedia oard Schematics 0TF TITLE SHEET No. OVER SHEET SOKET 0 PROESSOR, NORTH RIGE VT0/, SOUTH RIGE VT/, LOK SYNTHESIZER GTL+ US N PULL UP RESISTORS SRM IMM SLOTS / 0 PI SLOT & PI SLOT PI SLOT

More information

Model Name: 8I945GMF. Revision 1.0

Model Name: 8I945GMF. Revision 1.0 Model Name: IGMF SHEET TITLE Revision.0 SHEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER SHEET LOK IGRM OM & P MOIFY HISTORY P_LG_ P_LG_ P_LG_ P_LG_,E,F,G GMH-LKEPORT_HOST GMH-LKEPORT_RII GMH-LKEPORT_PI E, MI GMH-LKEPORT_INT

More information

EUCLID SPB. Model Name: 8I945GME. Revision 1.0 REAR AUDIO JACK DISCRETE POWER VCORE PWM_ISL6556 ATX, OTHERS POWER RTL8110S/RTL8100C FRONT PANEL

EUCLID SPB. Model Name: 8I945GME. Revision 1.0 REAR AUDIO JACK DISCRETE POWER VCORE PWM_ISL6556 ATX, OTHERS POWER RTL8110S/RTL8100C FRONT PANEL SHEET 0 0 0 0 0 0 0 0 0 0 0 Model Name: IGME TITLE Revision.0 SHEET TITLE OVER SHEET LOK IGRM OM & P MOIFY HISTORY 0 P_LG_ P_LG_ P_LG_ P_LG_,E,F,G GMH-LKEPORT_HOST GMH-LKEPORT_RII GMH-LKEPORT_PI E, MI

More information

MS Version 0A 06/21/2001 Update. CPU: Willamette/Northwood mpga-478b Processor. System Brookdale Chipset:

MS Version 0A 06/21/2001 Update. CPU: Willamette/Northwood mpga-478b Processor. System Brookdale Chipset: over lock iagram GPIO Spec. lock Y & T IE ONNETORS MS- Version // Update INTEL (R) rookdale hipset Willamette/Northwood pin mpg- Processor Schematics mpg- INTEL PU Sockets - INTEL rookdale MH -- North

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_

More information

MS INTEL (R) Brookdale Chipset System Brookdale Chipset: On Board Chipset: (OPTION) Standard: 2 Channel S/W Audio-Realtek ALC201A

MS INTEL (R) Brookdale Chipset System Brookdale Chipset: On Board Chipset: (OPTION) Standard: 2 Channel S/W Audio-Realtek ALC201A over lock iagram GPO Spec. lock Y & T E ONNETORS MS- Version NTEL (R) rookdale hipset. Willamette/Northwood pin mpg- Processor Schematics mpg- NTEL PU Sockets NTEL rookdale MH -- North ridge NTEL H --

More information

Cover Sheet. Block Diagram DDR SLOT DDR TERMINATOR AGP SLOT PCI SLOTS LAN CONTROLLER

Cover Sheet. Block Diagram DDR SLOT DDR TERMINATOR AGP SLOT PCI SLOTS LAN CONTROLLER over Sheet lock iagram MIN LOK EN & R LOK UFFER MS- VERSION: SIS / HIPSET Willamette/Northwood pin mp- Processor Schematics mp- INTEL PU Sockets SIS / NORTH RIE R SLOT R TERMINTOR - - SIS SOUTH RIE - PU:

More information

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103 core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S

More information

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown

More information

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1. R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H

More information

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14 A ISIONS ZONE LTR ESRIPTION ATE APPROVE A INITIAL RELEASE --_0:0 J 0 0 0,,,, AF JP PAR [:0] ON PIV 0 SO LAV EN LK PHYS M LK STAT_A M0 M R R R R R R R 0K J J AR AR[:0] AR AR AR AR0 AR AR[:0] AR AR AR AR0

More information

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10 I U N R 00K RSIN* RST S N.0u Y LK TP RP K L TP USY INT0 INT RISMINT P.0 P. P. P. P. P. P. RY OL RX0 TX0 T P.0 P. P. P. S* S* S* S* RROR* SLK U LKIN LKOUT LKOUT LKIN LKOUT OSOUT 0 OSOUT L L RSIN* L 0 0

More information

MS-6524 SIS 645/650 CHIPSET Willamette/Northwood 478pin mpga-b Processor Schematics

MS-6524 SIS 645/650 CHIPSET Willamette/Northwood 478pin mpga-b Processor Schematics Last Schematic Update ate: // MS- SIS / HIPSET Willamette/Northwood pin mpg- Processor Schematics PU: Willamette/Northwood mpg- Processor System rookdale hipset: SIS / (North ridge) + (South ridge) On

More information

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion

More information

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface.

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface. S J TXR0 TXR TXR TXR[:0] TXR TXR LK TX[:0] TX0 TX TX0 TX TX TX TX TX TX TX TX TX TX TX TX TX R 0K R 0K J J0 PIV R 0K TXPR R0. H/E0 H/E H/E TXLV TXSO J J HRST HLK HPERR HGNT HISEL HEVSEL HSTOP HTRY HIRY

More information

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector. R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument

More information

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0 Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP. . NV.V 00PF 00PF 00PF 0.UF 0.UF 0.UF 0.UF 0UF 0UF 0 0.UF 0.UF.V TO- -pin package Semtech Z, Unisem US0 00 NV O- RG-PWR-IN.V@ /- 0mV 0UF 00PF 00PF 0 00PF 0UF 00PF 0UF 0 0.UF 0 00PF 0.UF 0 O0 U POWR SNS

More information

PCIextend 174 User s Manual

PCIextend 174 User s Manual PIextend 7 User s Manual Preliminary M6- February Sycard Technology 8-F Miraloma Way Sunnyvale, 98 (8) 79- (8) 79- FX PIextend 7 User s Manual Page. Introduction Sycard Technology's PIextend 7 PI extender

More information

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115 PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.

More information

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2 SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_

More information

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V

More information

QUANTA COMPUTER INC.

QUANTA COMPUTER INC. QUNT OMPUTER IN. PGE ontent PGE ontent 0 0 0 T PGE OVER T LOK IGRM NW/PS (HOST US) NW/PS (POWER/N) MH (Host bus) MH (GP bus & HU I/F) GMH (PWR & GN) GMH R- & R- IH-M(PU,PI,IE) IH-M (US,HU,LP) IH-M(POWER&GN)

More information

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N P REVISION REOR J SP88 0 - RE N_JK P 90-00_-POS TP # - Remove these components to stack north # - Populate these components to stack north Use k Resistors or adjust as needed Header - Molex 90-0 PITORS,

More information

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7 Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM

More information

Renesas Starter Kit for RL78/G13 CPU Board Schematics

Renesas Starter Kit for RL78/G13 CPU Board Schematics Renesas Starter Kit for RL/G PU oard Schematics REV REF TE RWN Y 0.0 raft.0.0 TES.00 Release.0.0 YOI.0 Release 0.0.0 YOI PGE ESRIPTION INEX RL/G Microcontroller Switches, LEs, RESET, PSU E, Serial Port

More information

PTN3356 Evaluation and Applicaiton Board Rev. 0.10

PTN3356 Evaluation and Applicaiton Board Rev. 0.10 E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,

More information

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient

More information

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO

More information

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN

More information

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0

More information

Model Name: 8I945AE-AE Revision 1.1

Model Name: 8I945AE-AE Revision 1.1 Model Name: IE-E Revision. HEET TITLE HEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER HEET LOK IRM OM & P MOIFY HITORY P_L_ P_L_ P_L_ P_L_,E,F, MH-LKEPORT_HOT MH-LKEPORT_RII MH-LKEPORT_PI E, MI MH-LKEPORT_INT V

More information

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP MU ROOTIS / ORO MU_NRESET R_[0..] R_[0..] R_ R_ R_ R_ R_ R_0 R_0 R_ R_ R_ R_ R_ R_ OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I OTG_S_O OTG_S_PWR OTG_S_I OTG_S_N OTG_S_P OTG_S_O OTG_S_VUS UT_USER UT_USER SW_USER

More information

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V JK_P JP V V L 0u/N F FUSE() FUSE E 0uF/V E. V L 0u/N V 00nF 00nF V, R 00K 00nF U MP IN EN SS OMP 0nF S SW F 0.nF R K SW L u R.K_% R 0K_% V E 0uF/V V,,, ST-V V 00nF.uF 00P SS W ST-V E 0uF/V E 00nF TO U

More information

VISE (MS-6715) Intel (R) Springdale (GMCH) + ICH5 Chipset Intel Northwood & Prescott mpga478b Processor

VISE (MS-6715) Intel (R) Springdale (GMCH) + ICH5 Chipset Intel Northwood & Prescott mpga478b Processor over Sheet lock iagram Revision History - ntel mpg PU - Signals ntel mpg PU - Power ntel Springdale - Host Signals ntel Springdale - Memory Signals ntel Springdale - GP & LT Signals ntel H - P & E & Signals

More information

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1 isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty

More information

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766 OMMON_H_V MT (LQFP) V emo oard for Sanyo Slim H PUH INX & PO, ST F, SVO & MPG - MT MMOY - SM, FLSH/POM VIO OUT UIO WM NM TYP VI igital V SUPPLY V igital.v MT FV Servo.V MT LO_V Laser iode.v F V PIKUP H

More information

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE: R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS

More information

Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160

Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160 Service Service Service W-V0 0-0 Product Service Group udio Service Information lready published Service Informations: ORRTION TO SRVI MNUL elow are corrections to the circuit diagram parts list: OMI OR

More information

HF SuperPacker Pro 100W Amp Version 3

HF SuperPacker Pro 100W Amp Version 3 HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project

More information

Intel 100MHz Pentium(R) II processor/440gx AGPset Dual-Processor Customer Reference Schematics

Intel 100MHz Pentium(R) II processor/440gx AGPset Dual-Processor Customer Reference Schematics Revision.0 Intel 00MHz Pentium(R) II processor/0gx GPset ual-processor ustomer Reference Schematics TITL PLTFORM OMPONNTS IVISION 00 PRIRI ITY R. FM- FOLSOM, 0 PG OVR SHT LOK IGRM SLOT ONNTOR,,, LK SYNTHSIZR

More information

PCnet-FAST+ Am79C PQFP

PCnet-FAST+ Am79C PQFP NOTE: Place bypass caps close to power pins. EEPROM Pnet-FST+ m 0 PFP EEPROM Revision ate rawn omments 0 S Initial Release. NetPHY-LP LT Reference esign 0// S // // RF NetPHY-LP_LT_ Wednesday, ugust, NetPHY-LP

More information

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5. Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P

More information

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2 --00_: RV;E,F,G,H,J,K,L,M,N,P,R V;H,H,J,J,K,K,L,L,M,M,N,N,P,P V;,,,,,,,E,E,F,F,G,G SMOE MOE S EXP EXP EXP0 HIPI HIIPI HIPI HIPI0 EXTFILTER GN_ GN_0 IN- IN+ EN- EN+ VREF V_ES N RY PLK PULK LK SYN SYN SYN

More information

PCB NO. DM205A SOM-128-EX VER:0.6

PCB NO. DM205A SOM-128-EX VER:0.6 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V

More information

MS-7037 Intel (R) Springdale (GMCH) + ICH5 Chipset Intel Northwood & Prescott mpga478b Processor

MS-7037 Intel (R) Springdale (GMCH) + ICH5 Chipset Intel Northwood & Prescott mpga478b Processor MS-0 ntel (R) Springdale (GMH) H hipset ntel Northwood & Prescott mpg Processor PU: ntel Northwood/Prescott -.G & bove System hipset: ntel Springdale - GMH (North ridge) ntel H (South ridge) On oard hipset:

More information

3JTech PP TTL/RS232. User s Manual & Programming Guide

3JTech PP TTL/RS232. User s Manual & Programming Guide JTech PP-00 TTL/RS User s Manual & Programming Guide Revision. J Tech o., Ltd. Fu-Hsing N. Rd., F Taipei, Taiwan Tel: +--00 9 info@jtech.com.tw JTech (J Eng.), Inc. E. Valley lvd., Suite ity of Industry,

More information

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used! JP RS_SELET V For max ROUT is low when RIN is disconnected enabling the MX (RS-) This will not work if MX is used! V On Front Panel -F (To Pg.) RS- RE_ RE_ RV_Y RV_Z 0.uF V U MXUK STR U- H G U MX 0 Y Z

More information

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2 VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN

More information

Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09

Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09 Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with

More information

A[0..14] A[0..15] D[0..7] A[0..15] D[0..7] D[0..7] R/W I/O Phi0 MAP R/W R/W. I/O Phi0 MAP. Phi0 MAP. ROMDIS Phi2. ROMDIS Phi2. Id: 1/

A[0..14] A[0..15] D[0..7] A[0..15] D[0..7] D[0..7] R/W I/O Phi0 MAP R/W R/W. I/O Phi0 MAP. Phi0 MAP. ROMDIS Phi2. ROMDIS Phi2. Id: 1/ Power power.sch udio SOUN_OUT audio.sch Phi P[0..] P[0..] Phi P[0..] P[0..] PU Phi P[0..] P[0..] [0..] [0..] I/O MP ROMIS Phi [0..] [0..] I/O MP ROMIS Phi UL [0..] [0..] VI_S MP ula.sch LUE RE SYN M[0..]

More information

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1. Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT

More information

Am186CC and Am186CH POTS Line Card

Am186CC and Am186CH POTS Line Card RVISION HISTORY RV. T INITILS.0 // JSK m and mh POTS Line ard Reference esign NOT: The purpose of this design is to illustrate how to connect some of the M digital blocks together. It is not intended to

More information

All use SMD component if possible

All use SMD component if possible R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off

More information

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use

More information

POWER Size Document Number Rev Date: Friday, December 13, 2002

POWER Size Document Number Rev Date: Friday, December 13, 2002 R0 [ /W 0 0.00uF/00V - D0 KP0M L0 L D0 N 0 00uF/00V 0 0.uF R0 M [ /W R0 M [ /W R0 M [ /W R0 M [ /W 0 0.00uF/KV D0 PS0R 0 0uF R0 00K [ W D0 FR0 R0 0 [ /W O O T0 O,, POWER X'FMR 0, D0 DQ0 R [ /W 0.00uF/00V

More information

Cover Sheet 1 Block Diagram 2 GPIO SPEC. AMD K8 -> 754 PGA Socket 4,5,6 Clock Synthesizer

Cover Sheet 1 Block Diagram 2 GPIO SPEC. AMD K8 -> 754 PGA Socket 4,5,6 Clock Synthesizer MS- VER:0 *M PG K-Processor (R 00) *VI KM00 *VI VTR(GP X / VLink X) *Winbond THF LP I/O Page over lock iagram GPIO SPE M K -> PG Socket,, lock Synthesizer System Memory R IMM & *VI VT0L 0/00 ase-t LN *US.0

More information

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT LTER YLONE III EP evelopment & Education OR SHEMTI ONTENT PGE TOP MEMORY OVER PGE, TOP SRM,FLSH 0 ~ 0 0 ~ 0 ISPLY VG, LE, SEGMENT 0 ~ 0 IN/OUT LOK, PS, RS, UTTON, SWITH, ONNETOR,S R 0 ~ FPG yclone II EP

More information

CONTENTS: REVISION HISTORY: NOTES:

CONTENTS: REVISION HISTORY: NOTES: ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry

More information

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

Cover Sheet Block Diagram. Clock Synthesizer. 462PGA Socket KT133(VT8363)---North Bridge. System Memory AGPPRO 4X SLOT PCI Connectors

Cover Sheet Block Diagram. Clock Synthesizer. 462PGA Socket KT133(VT8363)---North Bridge. System Memory AGPPRO 4X SLOT PCI Connectors // Update Version over Sheet lock iagram Page Size : "*." Layer: Stack:omponent/Gnd/Power/Solder MS- Micro-TX lock Synthesizer PG Socket KT(VT)---North ridge,,, mils trace impenence Ohms ielectric ~. Prepreq

More information

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE

More information

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History 0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00

More information

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMENTL TO THE INTERESTS OF NLOG EVIES.

More information

Power. Video out. LGDC Subsystem

Power. Video out. LGDC Subsystem Power LE_UX# LG Evaluation System: Mainboard Revision: P Reference I: 00 # Video out LG Subsystem _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I/O ISP_LK I[..0] ISP_[..0]

More information

M13 M14 FQP FFP VC1 VC2 VC3 MIX ATNEXPOT ADSR1 BM-VCF FAH1 FAW1 H W ATNEXPOT LFO FAH2 FAW2 H W +10VR FFP BP FQP FAH1 FAW1 FAH2 FAW2 R2 100K M15

M13 M14 FQP FFP VC1 VC2 VC3 MIX ATNEXPOT ADSR1 BM-VCF FAH1 FAW1 H W ATNEXPOT LFO FAH2 FAW2 H W +10VR FFP BP FQP FAH1 FAW1 FAH2 FAW2 R2 100K M15 MP_ MP_ MIIV JP HEE JP V0 V V V S_0 S_ S_0 S_ MIILK STTSTOP ESET SMP_ SMP_ HEE JP 0V 0V 0V 0V 0V 0V 0V 0V HEE X 000 JP9 000 MII VP VP 9 0 POTSLE POTH POTL POTSLE POTSLE POTH POTL POTSLE 9 0 HEE X 000 HEE

More information

SVS 5V & 3V. isplsi_2032lv

SVS 5V & 3V. isplsi_2032lv PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf

More information

U1-1 R5F72115D160FPV

U1-1 R5F72115D160FPV pf R NF_ X MHz, pf ON_XTL ON_EXTL R R NF_,,,, R NF_ R NF_ R R,,,, M M M_LK M_LK SEMn TI TMS TK TRSTn K R K R K R K R EXTL XTL M M M_LK M_LK TESTM SEMn TI TMS_WTX TK_WSK TRSTn_WRX U- RFFPV VREF VREFVSS

More information

MSP430F16x Processor

MSP430F16x Processor MSP0x Processor V_. V_ V_. U Vcc Vcc R 0K SW, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T /RST/NMI 0.u P UTTON_

More information

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2. +.0V IN J PJ-0 _ONN VUS JP JUMPERT VUS_FP 00 F FERRITE_E..V U TPS0 GN F TGN PF R.K % VP. R K %.V /.V ORE.V I/O U TPS0 JP VP JP HR VP_GL U TPS0 R.K LM0EM -. JP HR VORE_GL VORE. GN F TGN 0 PF R.K % R K %.

More information

35H MPa Hydraulic Cylinder 3.5 MPa Hydraulic Cylinder 35H-3

35H MPa Hydraulic Cylinder 3.5 MPa Hydraulic Cylinder 35H-3 - - - - ff ff - - - - - - B B BB f f f f f f f 6 96 f f f f f f f 6 f LF LZ f 6 MM f 9 P D RR DD M6 M6 M6 M. M. M. M. M. SL. E 6 6 9 ZB Z EE RC/ RC/ RC/ RC/ RC/ ZM 6 F FP 6 K KK M. M. M. M. M M M M f f

More information

Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.

Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5. lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI

More information

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs VR core and power 00v.0 Power supply, reset circuit, reference voltage and power indicator. Port 00v.0 nalogue and digital inputs with options for FET outputs Port 00v.0 igital inputs with optional FET

More information

3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)

3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1 header). Also used on IO Matrix (IOMx) NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This

More information

Power. I/O Extensions. CPU Extensions. JADE-D Subsystem

Power. I/O Extensions. CPU Extensions. JADE-D Subsystem XXSvideo- Revision: P. Power WI V_ORE_PG WI V_ORE_PG Reference I: 00 # WI PU Extensions HOST_SPI[..0] SPI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] MEM_RY VIN0_[..0] HOST_SPI[..0] S PI_0[..0] PU_[..] PU_[..0]

More information

CD300.

CD300. 00 Service Information www.laney.co.uk 9 9 -V J R9 N N N R R K K U/0V I R K U/0V R R R K K K N N R0 V U/0V 0 U/0V R 0K R 0K U/0V W 00K R9 M I R 00 U/0V 9 W W0K R 0K R K 0 0 R K W W0K K R0 MP K U/0V R 0K

More information

XIO2213ZAY REFERENCE DESIGN

XIO2213ZAY REFERENCE DESIGN XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE

More information

LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND

LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND R White R Red _TX_Q_P J 0-0 0 _TX_I_P _TX_I_N _TX_Q_P _TX_Q_N L _TX_I_P _TX_I_N.R -d ttenuator.r.r 00pF_0V JP SM _TX_Q_P _TX_Q_N _TX_Q_P _TX_Q_N GN VV VV VV_TX VV VV VV_TX Modulator L L PowerSupply J POWER

More information

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL UIO-OUT& U&.SH Sirius-Tx- +V-SY Sirius-Rx- -S -SL - S MU MU.SH M&M M&M.SH M ST M-SMETER E-PLL +V- +V- T-IN T-IN T-LK +V-STY +V-STY T-OUT ate: -Sep-00 Sheet of ile: :\aa\t. rawn y: RS-Tx RS-Rx R- STYUS

More information

H-LCD700 Service Manual

H-LCD700 Service Manual H-L00 Service Manual FULT ESIPTION: SOUN onfirm the volume isn t in silent mode before check. heck I0 () plug has audio output or not Speaker damaged heck I0 has supply V or not heck power heck I0 () plug

More information

Power USB I/F. USB->Uart AX309. Power LED :25:33 I:\AX\AX309\2.0\1_POWER.SchDoc VBUS VBUS D- D+ Fuse VCC GND D3V3 U

Power USB I/F. USB->Uart AX309. Power LED :25:33 I:\AX\AX309\2.0\1_POWER.SchDoc VBUS VBUS D- D+ Fuse VCC GND D3V3 U X0.0 0-- :: I:\X\X0\.0\_POWER.Schoc ate: R K Power LE LE SW SW V P P P V V F Fuse U SRV0- VUS P M RX TX LE RX LE TX R K R K VUS - I J US->Uart US I/F E 00uF/V OUT IN = U -. V E 00uF/V OUT IN = U -. V E

More information

Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N

Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N NOTES: ISION LOK. Unless otherwise stated: Resistors are mw, % tolerance. apacitors are V, % tolerance.... J Port and Net Name scopes for this project are: Port NOT Global (connected via Sheet Symbols)

More information

DNI TP25 ORG DNI 0.1UF 12V 47UF DNI DNI WHT DGND1 LM1117MP-3.3/NOPB +V_MTR +V DNI OUT1 OUT ADJ DNI 0.1UF R10 10K DGND 47UF DNI DNI EXLVL DGND DGND

DNI TP25 ORG DNI 0.1UF 12V 47UF DNI DNI WHT DGND1 LM1117MP-3.3/NOPB +V_MTR +V DNI OUT1 OUT ADJ DNI 0.1UF R10 10K DGND 47UF DNI DNI EXLVL DGND DGND TP RN V_ORE N_ N TP LKORY_ N_ LKORY S S_ TP RE TP LU EUT_ VP SLK SLK V V_E VIOLET TP VP XTL XTL R LKORY_ RN R TP LKORY_ N_ TP LKORY_ N_ LKORY S S_ RE TP LU EUT_ TP VP SLK V V_E VIOLET TP VP XTL XTL RN

More information

XO2 DPHY RX Resistor Networks

XO2 DPHY RX Resistor Networks PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX

More information

U100. cgen_by BYPASS. cgen_cp CLK_FPGA_P (OUT0A) OUT0 CLK_FPGA_N (OUT0B) OUT0 (OUT1A) OUT1 (OUT1B) OUT1 (OUT2A) OUT2 U10 DS90LT012AH (OUT2B) OUT2

U100. cgen_by BYPASS. cgen_cp CLK_FPGA_P (OUT0A) OUT0 CLK_FPGA_N (OUT0B) OUT0 (OUT1A) OUT1 (OUT1B) OUT1 (OUT2A) OUT2 U10 DS90LT012AH (OUT2B) OUT2 9 0 TX nternal Reference loop filter for internal V vco_cp R.0 vco_vtune loop filter for VX vcxo_cp R0 0 vcxo_vtune V_TX: 0 0u VTX Vcc X UT /TU V_TX: R 0 0n p cgen_int_ref p vcxo_clk R 0 refer Ref ode

More information

CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H

CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H

More information

LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3

LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3 MU THERMISTOR- MU LI_RX LI_TX LI_RX LI_TX MX_TX MX_RX MX_/RE MX_E MX_TX MX_RX MX_/RE MX_E MX_LI +.V_MU R 0K R 0K R R R R LE_POWER_STGE - Out GN J LE- -V LE Power Stage LE_POWER_STGE - Out GN J LE- -V LE

More information

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0. 0 #E0 GPIOK #MWR #MR #FWE HOSI KEYI0 GPIO0 HOSO V V VREFI KEYI GPIO GPIO_ V KEYO GPIO #E OUTR MIIN VMI GPIO_0 #LON V #HOL 0 0 #E KEYO GPIO 0 KEYO0 GPIO GPIO_ GPIO_0 #MR #MWR V V V V TSEL #E #E0 V HOSI

More information

AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index

AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index XM0-EV-RTLE- SMK0 emo oard Schematic Index Page : Schematic Index (This Page) Page : RTLE GigaPHY MHz rystal RJ- Transformer Page : Host Interface onnector Power Page : History Page : X0 EEPROM Note:.Please

More information

RETICLE 2 NORTH SW2 DPDT SOUTH. LM339A TxD1 Out 11 U2D DEC PULSE 1 FOCUSER-2 3.0V 17 CCD EAST U2A AUX -6 FOCUSER-2 FOCUSER SW1 DPDT

RETICLE 2 NORTH SW2 DPDT SOUTH. LM339A TxD1 Out 11 U2D DEC PULSE 1 FOCUSER-2 3.0V 17 CCD EAST U2A AUX -6 FOCUSER-2 FOCUSER SW1 DPDT J KYP PWR J TX0\ RTIL RX0\ U V V NORTH V- NORTH/SH LM J RS V MIS XMIT LX00 XMIT LX00 RV MIS RV U SH V LM RN V V 0K J U LN 0 RX0\ 0 V TTRY LM Tx Out TX0\ Rx In Tx Out RTIL 0 Rx In U 0 V LM 0 PULS FOUSR-

More information

SCHEMATIC REV. DRAWING NO. 9268CE01C REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O REV JP# * SEE ASSEMBLY INSTRUCTIONS

SCHEMATIC REV. DRAWING NO. 9268CE01C REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O REV JP# * SEE ASSEMBLY INSTRUCTIONS THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMTL TO THE INTERESTS OF NLOG EVIES.

More information

A L A BA M A L A W R E V IE W

A L A BA M A L A W R E V IE W A L A BA M A L A W R E V IE W Volume 52 Fall 2000 Number 1 B E F O R E D I S A B I L I T Y C I V I L R I G HT S : C I V I L W A R P E N S I O N S A N D TH E P O L I T I C S O F D I S A B I L I T Y I N

More information

[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST

[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST 0 [] [] [] [] [] [] [] [] [] [] [] [] MOSI MISO SK 0 H H N_MS TMS RX TX SL J P_MOSI P_MISO P_SK P_ P_IO0 P_IO P_IO P_ P_ 0 P0_GN P_NT P_GN/NT P_RXL/SS P_TXL P_IO P_(SL) P_(S) P_ P_0 0 P0_ P_ P_IO P_R+

More information

nrf52840-mdk V1.0 An Open-Source, Micro Development Kit for IoT Applications using the nrf52840 SoC Revision History Function Description Page Rev.

nrf52840-mdk V1.0 An Open-Source, Micro Development Kit for IoT Applications using the nrf52840 SoC Revision History Function Description Page Rev. nrf0-mk V.0 n Open-Source, Micro evelopment Kit for IoT pplications using the nrf0 So Revision History Function escription Page Rev. escription Title Sheet V.0 The First Release Power Supply US.0 Hub PLink

More information

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST N Updata /N P. R.K R 00 R 00 R.K P_SL P_S V R K SF_E U PMVF00 E SO WP VSS V HOL SK SI SF_LK V 0.UF/V SF_E SF_LK P_SL P_S SL S V SL' S' SF_E SF_LK P_SL P_S SL S V SL' S' U T 0 V WP SL S SL' S' 0.UF/V R

More information

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by: Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and

More information