VISE (MS-6715) Intel (R) Springdale (GMCH) + ICH5 Chipset Intel Northwood & Prescott mpga478b Processor

Transcription

1 over Sheet lock iagram Revision History - ntel mpg PU - Signals ntel mpg PU - Power ntel Springdale - Host Signals ntel Springdale - Memory Signals ntel Springdale - GP & LT Signals ntel H - P & E & Signals ntel H - Other Signals lock - S S0 & FWH & Manual LP /O - LP udio - roadcom M0 R System Memory & R System Memory & GP X/X Slot & P Riser ard P Slots & & VSE (MS-) ntel (R) Springdale (GMH) H hipset ntel Northwood & Prescott mpg Processor PU: ntel Northwood/Prescott -.0G & bove System hipset: ntel Springdale - GMH (North ridge) ntel H (South ridge) On oard hipset: OS -- FWH EEPROM ' odec -- LP Super /O -- LP LN -- SR nterface LOK -- S0 / Y0 H/W Monitoring -- M0 Main Memory: R00 * (Max G) Version 0 0//00 Updated T//00 E & Video onnectors US & LN onnectors H/W Monitor & FN Expansion Slots: P. SLOT * GPX/X SLOT * TX & Front Panel GP & MEMORY & US Regulator ontroller _ & Regulator & VR Thermal ntersil PWM: ontroller: HP river: HP0 * VRM 0 - ntersil HP HP 0 PULL UP/ OWN RESSTORS GPO Regulators System : FN MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen OVER SHEET Size ocument Number Rev VSE (MS-) 0 ate: Monday, October, 00 Sheet of 0

2 VRM 0 ntersil -Phase PWM ntel mpg Processor lock iagram /MHz@./.G/s FS GP.V onnector nalog Video Out X/X w/fast Write MHz@.G/s Springdale bit R /MHz@./.G/s R MM Modules MHz@M/s HT Link E Primary E Secondary US Port 0 UltraM //00/.MHz(W)/0MHz(R)@./00M/s H P NTRL P R/T MHz@M/s P Slot P Slot P Slot US Port US Port US Port US Port US Port US Port US 0MHz@0M/s MHz@.M/s LP us LP SO SMS LP US Port ' odec ' Link.MHz@.M/s Flash Keyboard Floopy Parallel Serial GG LN P Mouse M0 MHz@M/s MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen LOK GRM Size ocument Number Rev 0 VSE (MS-) ate: Monday, October, 00 Sheet of 0

3 Revision nitial ver: 0E0 on 0//00 Schematic nitial on July. Revision change list from ver: 0E0 to ver: 0E on 0/0/00 Sheet : Modify some txts. Sheet : Modify some txts. Sheet : Move Lan connector to page. Sheet : Modify some block for customer request, detail list on below: () Modify v US power supplier. () Modify V main power circuit. () Modify GMH voltage supplier. () dd GMH reference voltage circuit. Sheet : Modify some block for customer request, detail list on below: () Modify V standby power supplier. () hange _R to LP. () dd lan magnetic circuit. () Modify Lan connector. () dd.v standby voltage. Revision change list from ver: 0E to ver: 0E on 0/0/00 Sheet : hange _FS to capacitors termination on pin and. Sheet : hange _R to capacitors termination on pin E,E,,R and R. Sheet : hange some bulk caps from 00uF to 0uF. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () elete GP and GP on pin U and pin T0 on H. () dd HSS_ on pin V on H. () elete US, US-, US, and US-. () hange FRONT_US_ET# from pin to pin on H. Sheet : Modify some block for customer request, detail list on below: () Modify clock generator library. () hange P clock label. () dd strapping resistors. Sheet : elete some caps on _R. Sheet : elete some caps on _R. Sheet : elete some GP termination resistors. Sheet 0: hange P clock label. Sheet : Modify some block for customer request, detail list on below: () elete ports US, and one US power. () Removed LN connector to here. Sheet : Modify some block for customer request, detail list on below: () hange from GP to on pin 0 of F_P. () hange from to HSS_ on pin of F_P. () hange from GP to HSS_0 on pin of F_P. () hange from to HSS_ on pin of F_P. () Pull _S to pin on H. Sheet : Modify some block for customer request, detail list on below: () hange R from Kohm to. () hange R from 0 ohm to. () hange some bulk caps from 00uF to 0uF. Sheet : elete R,R0,R, and R. Revision change list from ver: 0E to ver: 0E on //00 Sheet : Modify clock generator library. Sheet : Modify some block for customer request, detail list on below: () hange SERL PORT connector to 0 pin center-keyed shrouded header. () dd T G. () hange label PS_ON to PS_ON#. Sheet : Modify some block for customer request, detail list on below: () elete Q,Q,Q0,Q,Q,Q. () Modify this page same as reference schematic. Sheet : Exchange pin 0 and pin on MM and MM. Sheet : Exchange pin 0 and pin on MM and MM. Sheet : Modify some block for customer request, detail list on below: () dd ohm series resistors on ata :0 on Primary E. () dd ohm series resistors on ata :0 on Secondary E. () elete U, WZ0. Sheet : Modify some block for customer request, detail list on below: () elete Q, R, R,and R. () hange label PS_ON to PS_ON#. () elete U, WZ0. Sheet : hange Q from N0 to N00. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () ll TESTH pull up resistors change from ohm to ohm. () elete OPTMZ label. Sheet : Modify some block for customer request, detail list on below: () elete E and E. () hange L and L from.uh to 0uH. Sheet : Modify some block for customer request, detail list on below: () Separate from _FS and add 0.uF cap to on pin. () hange from 0.uF to 0.uF. Sheet 0: Modify some block for customer request, detail list on below: () dd pins header to pin T0. () hange pin and to O# signal. () hange label O# to O#. () hange label O# to O#. () dd label _VREF and _SWNG to pin F and F. () elete R on pin G0. Sheet : Modify some block for customer request, detail list on below: () dd 0.uF cap to pin F. () dd 0.uF cap to pin Y, and. () dd 0.uF cap to pin F and F. Sheet : Modify some block for customer request, detail list on below: () hange R0 from 0ohm to 0Kohm. Sheet : Modify some block for customer request, detail list on below: () hange R and R from 00ohm to 0ohm. () hange R from Kohm to.kohm. Sheet : Modify some block for customer request, detail list on below: () dd ohm resistor to _SN0. () hange R from 0ohm to ohm and add pf cap. () hange R and R0 from.kohm to 00ohm. () hange R0, R0, R0, R0 from.kohm to.kohm. () dd divide Kohm pull down resistor to OUT_R and OUT_L signals. () elete. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () dd two ohm divide resistors in R_VREF. () hange 0ohm to ohm on Rterm array resistors. () dd two divide ohm resistors pin. Sheet : Modify some block for customer request, detail list on below: () dd two ohm divide resistors in R_VREF. () hange 0ohm to ohm on Rterm array resistors. () dd two divide ohm resistors pin. Sheet 0: Modify some block for customer request, detail list on below: () dd pins header for support Prochot latch. Sheet : Modify some block for customer request, detail list on below: () hange R and R from.kohm to.kohm. Sheet : Modify some block for customer request, detail list on below: () dd one usb power circuit to seperate port 0, and,. () hange R and R from Kohm to 0Kohm. () hange R0 and R from Kohm to 0Kohm. () hange from 0pF to 000pF. Sheet : Modify some block for customer request, detail list on below: () hange R0 from 0ohm to ohm. Sheet : Modify some block for customer request, detail list on below: () hange T-T from 00uF to 0uF. Sheet : Modify some block for customer request, detail list on below: () hange label O# to O#. () dd some divide resistors to _VREF and _SWNG signals. () hange R from 00ohm to 00ohm and add a 00ohm resistor pull to voltage. () elete R. and TP_ direct connect to Vccp. () hange PM# from ohm to ohm. () hange R0 from 0ohm to 00ohm. () dd two 0ohm resistors to support TP or US_TP port. () hange R from ohm to ohm. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () dd 00 ohm resistor from OOT to _V and change R to 0Kohms. () hange R and R to V_SW_TRL# signal. Sheet : Modify some block for customer request, detail list on below: () dd Northwood F network and Prescott F network to VRM controlled by OOT. () hange 0ohm to ohm on Rterm array resistors. () hange R0,R,R,and R0 from.kohm to.kohm. Sheet : dd teo 0Kohm pull down resistors to RSMRST# and H_G signals. Revision change list from ver: 0E to ver: 0E on 0/0/00 Sheet : Modify some block for customer request, detail list on below: () hange R from HPLK to LNPLK signal. () hange R from FWHPLK to PLK0 signal. () hange R from LNPLK to PLK signal. Sheet : elete,0,,,, and. Sheet : hange all component from 00 to 00. Sheet : hange all component from 00 to 00. MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen REVSON HSTORY - Size ocument Number Rev VSE (MS-) ate: Monday, October, 00 Sheet of 0 0

4 Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : hange some caps of north side to not install. Sheet : Modify some block for customer request, detail list on below: () dd LP_RQ# label on pin R on H. () hange pin Y from NTRUER# to HOO_SENSE#. Sheet : Modify some block for customer request, detail list on below: () Remove R and R. onnect FWH RST# signal directly to PRST#. () elete R,Q,Q, and R. () hange R from 0 ohm to.k ohm. () dd one resistor to SE_PLK signal and share with SO_PLK. () elete NT# LOK. Sheet : Modify some block for customer request, detail list on below: () hange pin to R_V. () hange pin to M_PT_ET#. () hange pin to SE_TPM_PRES. () hange pin to M_PT_ET#. () hange pin to F_M. () dd pin 0 to V_N. Sheet : hange all component from 00 to 00. Sheet 0: Modify some block for customer request, detail list on below: () hange TP resistors from.kohm to.kohm. () dd a.kohm pull down resistor to PRST#. Sheet : dd Security header. Sheet : hange & ischarge Residual Voltage same as reference schematic. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Support M0. Sheet 0: Modify some block for customer request, detail list on below: () elete T. () hange T from intall to not install. Sheet : elete and R. Sheet : hange R,R,R, and R from ohm/0 to.ohm/00. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : hange Label from _S to VS. Sheet : Modify some block for customer request, detail list on below: () hange Label from PRST# to PRST_H#. () hange all pull high resistors of clock generator from V to. Sheet : Modify some block for customer request, detail list on below: () hange Label from _S to VS. () hange pin to GP and add a.kohm resistor to on GP. () dd a label SYSMG_NT on pin. () hange pin to M_PT_ET#. () hange pin to SE_TPM_PRES. Sheet : Modify some block for customer request, detail list on below: () elete R, R,,,,. () hange R & R to 0 ohm. () hange & to.uf. () hange R0 & R to.k. () dd 0.uF and.k in series to pin of Front udio Header. () dd label bias circuit to pin of Front udio Header. () dd ohm from OUT_L to junction of & R0. Sheet : hange Label from _S to VS. Sheet : hange Label from _S to VS. Sheet : hange Label from _S to VS. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () hange H/W monitoring circuit. () hange Fan circuit. Sheet : hange Label from _S to VS. Sheet : hange Label from _S to VS. Sheet : hange Label from _S to VS. Sheet : hange Label from _S to VS. Sheet : hange Label from _S to VS. Revision change list from ver: 0E to ver: 0E on 0/0/00 Sheet : hange PU Symbol - pin F=GTLREF, pin F0=GTLREF, pin =GTLREF, pin =GTLREF0. Sheet : Modify some block for customer request, detail list on below: () isconnect U pin E (GMH) directly to VREF. () dd a.uf cap to this pin E. Sheet : Modify some block for customer request, detail list on below: () hange R & R from K to 0K. () dd pullup resistor from SEL0 to. () dd pullup resistor from SEL to. Sheet : hange F, F & F0 to be the same as F, F & F. Sheet : Modify some block for customer request, detail list on below: () hange Q0 & Q to epletion Mode JFETs. () onnect R00 to -V. () hange R to a ohm RNET and connect in parallel to. () hange R0 to a ohm RNET and connect in parallel to. () Move R from rain of Q to Source. () hange R from 0 to ohms. () hange R from 0 to ohms. () hange R from 0 to ohms. Sheet : hange R & R0 to 0 ohms %. Revision change list from ver: 0E to ver: 0E on 0/0/00 Sheet : elete 0.uF caps on PU side. Sheet : hange R from.ohm to 0ohm. Sheet : Modify some block for customer request, detail list on below: () isconnect U pin R (GMH). () isconnect U pin L (GMH) and add single cap to it. Sheet : elete decoupling caps between _R and _R. Sheet : elete decoupling caps between _R and _R. Sheet : hange all arrary resistors from 00 to 00 on all E. Sheet : dd secondary transformer to support 0M and 00M N. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () isconnect PU pin, ERR# signal. () dd a pull down resistor to PU pin E, OPTMZ signal, and not install. Sheet : hange R from Kohm to.kohm. Sheet : dd RN to support SUS_,, voltage for H. Sheet : Modify some block for customer request, detail list on below: () hange net GP to PS_ETET. () dd net FN_M to pin U0. () hange net GP to PRO_HOT#. () hange R0 to 0Kohm, not install,and a resistor to. () elete net RT_X. Sheet : Modify some block for customer request, detail list on below: () hange net TRMTRP# to SO_TRMTRP#. () elete R, and change net V_N to OMM ET#. Revision change list from ver: 0E to ver: 0E on 0//00 Sheet : Modify some block for customer request, detail list on below: () Swap net R_V and FN_LMP. () elete R, and change net V_N to OMM ET#. Sheet : Modify some block for customer request, detail list on below: () hange R to.kohm. () dd a 0pF cap to and, not install. () dd a uf caps to MONO_L and MONO_L_R. () dd a uf caps to MONO_R and MONO_R_R. () hange R0 and R to 0ohm. () hange from 00pF to 0.0uF. Sheet : hange net R_VREF to R_VREF. Sheet : hange net R_VREF to R_VREF, and add two resistors. Sheet : Modify some block for customer request, detail list on below: () Modify H/W monitoring and FN controller. () hange U pin from _R to No onnect. Sheet : dd PROHOT# LE. Sheet : Modify some block for customer request, detail list on below: () elete R and R0. () hange to 0.0uF. () hange Q pin and pin to _STR. () hange Q pin and pin to. () hange Q pin to PHSE_V. () hange Q pin to PHSE_V. () hange Z to. () hange U pin and to _STR. Sheet : Modify some block for customer request, detail list on below: () dd VR THERML LOK. () dd H SUS_,, and voltage regulatot to support this version fail chipset. Sheet : Modify some block for customer request, detail list on below: () elete R, ERR#. () hange net GP to PS_ETET. () hange net GP to PRO_HOT#. () dd Thermtrip Translation lock. () hange RN pin to No onnect. () elete,, and R00. () elete net RT_X. Revision change list from ver: 0E to ver: 0EE on 0//00 Sheet : hange U pin from PREQ# to R_. elete R. Sheet : Modify some block for customer request, detail list on below: () hange U pin G from R_ to STLE#. () hange U pin U from RSER# to No onnect. () hange U pin T from R_0 to N_ENLE#. () hange U pin V from SO_PME# to P_PME#. () hange U pin F from H_FN_OVR to R_0. Sheet : hange R and R to Kohm. Sheet : Modify some block for customer request, detail list on below: () hange U pin from OMM ET# to R and add pull up to. () hange R from VS to. MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen REVSON HSTORY - Size ocument Number Rev VSE (MS-) ate: Monday, October, 00 Sheet of 0 0

5 Revision change list from ver: 0E to ver: 0EE on 0//00 Sheet : Modify some block for customer request, detail list on below: () hange U pin from PLE to SUSLE. () hange U pin from SUSLE to PLE. () hange U pin from SO_PME# to R#. () hange U & U from to T. Sheet : hange U pin from RSER# to No onnect. elete R. Sheet : Modify some block for customer request, detail list on below: () dd K pull up from E_RST# to. () dd K pull up from E_RST# to. Sheet : elete U. Sheet : hange T and T to V part. Sheet : hange Q and Q to FV0N. Sheet : dd U for support sata led on front panel. Sheet : Modify some block for customer request, detail list on below: () dd R ohms from TRMTRP# to P. () hange R0 from TRMTRP# to H_TRMTRP#. Revision change list from ver: 0EE to ver: 0EF on 0//00 Sheet : Modify some block for customer request, detail list on below: () hange K to on OM. () elete F. () hange U pin from SO_PME# to R#. () hange U & U from to T. Sheet : hange U pin from RSER# to No onnect. elete R. Revision change list from ver: 0EF to ver: 0E0 on 0//00 Sheet : Modify some block for customer request, detail list on below: () hange E,,,0,,,,,,and E to not install. () hange E,,,,,,,,,,, and E to not install. Sheet : Modify some block for customer request, detail list on below: () hange U pin H from PRQ#H to PRQ#E. () hange U pin from PGNT# to PGNT#0. () hange U pin J from PREQ# to PREQ#0. Sheet : Modify some block for customer request, detail list on below: () hange GP pin from PRQ# to PRQ#. () hange GP pin from PRQ# to PRQ#. () hange U pin from PRQ# to PRQ#F. () hange U pin from PRQ# to PRQ#G. () hange U pin from PRQ# to PRQ#. () hange U pin from PRQ# to PRQ#. Sheet 0: Modify some block for customer request, detail list on below: () hange P pin from PGNT#0 to PGNT#. () hange P pin from PREQ#0 to PREQ#. Sheet : hange N_ESEL to N_SEL. Sheet : hange T to not install. Revision change list from ver: 0E0 to ver: 0E on 0/0/00 Sheet : Modify some block for customer request, detail list on below: () U pin P should connect to U pin. () U pin N should connect to U pin. () U pin should connect to U pin P0 (EE_T). () U pin should connect to U pin M0 (EE_LK). Sheet : dd SMUS isolation block. Revision change list from ver: 0E to ver: 0E on 0/0/00 Sheet : Modify some block for customer request, detail list on below: () hange SMLK to SM_LK. () hange SMT to SM_T. Sheet : Modify some block for customer request, detail list on below: () hange SMLK to SM_LK. () hange SMT to SM_T. Sheet : Modify some block for customer request, detail list on below: () hange SMLK to SM_LK. () hange SMT to SM_T. Sheet : dd some caps between and. Sheet 0: dd some caps on and. Sheet : Modify some block for customer request, detail list on below: () hange SMLK to SM_LK. () hange SMT to SM_T. Revision change list from ver: 0E to ver: 0E0 on 0//00 Sheet : hange U to install and R to not install. Sheet 0: dd pin 0 to. Sheet : hange RN to not install. Sheet : Modify some block for customer request, detail list on below: () dd RSMRST# pull high resistor. () dd PWRTN# pull high resistor. () hange R to R0 to install. Sheet : dd H pull down resistor. Sheet : Modify some block for customer request, detail list on below: () hange RSLT to SLT. () hange RPE to PE. Sheet : Modify some block for customer request, detail list on below: () dd two resistors to V_P voltage. () elete Z. Sheet : dd some caps on _R voltage. Sheet : dd some caps on _R voltage. Sheet : hange LN connector to popular pins. Sheet : Modify some block for customer request, detail list on below: () hange FN circuit. () hange _STR circuit. () hange Q0 to TO-. () hange circuit some components to not install. Sheet : Move _VS voltage. Sheet : hange Q to N0. Revision change list from ver: 0E0 to ver: 0E on 0//00 Sheet : hange pull high strapping to pull down. Sheet : hange some component to fix audio solution. Sheet : hange some components to fix VRM solution. Sheet 0: dd two mini jumpers to support front panel. MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen REVSON HSTORY - Size ocument Number Rev 0 VSE (MS-) ate: Monday, October, 00 Sheet of 0

6 H/W Project Leader : ndy hen PU SGNL LOK VSE (MS-) 0 ntel mpg - Signals MRO-STR Nt'L O., LT. 0 Monday, October, 00 Size ocument Number Rev ate: Sheet of HRS# H#0 H# H# OMP H# H# PM# H#0 H# H# H#0 H# H# H# TESTH HREQ#0 PM# V H# H# H#0 H# H# H# H# H# H#0 H# HREQ# HREQ# V H# H# H#0 H# H# H# H# OMP0 PM# H# H# H# H# TESTH HREQ# H# H# H# V H# H# H# H# H# H#0 H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# HREQ# H# H# H# H# H# H# HRS#0 H# H# H# H# H# H# H# HRS# GTLREF V H# H# H# H# H# H# H# H# H#0 V H# PM# H# H# H# H# TESTH TESTH0 PM#0 PM# H# H# H# H# H# TESTH TESTH V0 H# H# H# H# H# H# H#0 H# H# TESTH TESTH0 OPTMZ P R.RST R.RST 0p_XR {VOLTGE} R R0 R R R R R R R PU NORTH/PRES Y W V U T W R V T U P U T R P P R T N N N M N M M L M L K L K K E Y Y Y W Y W V V U V U U U T T T T R R P R N N M N M P N M H K J L M H G L F E F F G E H J H G E E E E E F0 F Y H J J K J U 0 0 F F F G F V H P L L K K J R L W P J F W R K E E W Y E G P V V Y W H H J G G G F E E E F E F F F E # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # R# _SENSE _SENSE TP_LK TP_LK0 # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# V# V# V# V# V0# GTLREF0 GTLREF GTLREF GTLREF PM# PM# PM# PM# PM# PM0# REQ# REQ# REQ# REQ# REQ0# TESTH TESTH TESTH TESTH TESTH TESTH TESTH TESTH TESTH0 LK# LK0# RS# RS# RS0# P# P0# R0# OMP OMP0 P# P# P# P0# ST# ST0# STP# STP# STP# STP0# STN# STN# STN# STN0# LNT/NM LNT0/NTR TESTH TESTH0 0# # # # ERR# MERR# FERR# STPLK# NT# NT# RSP# SY# RY# TRY# S# LOK# NR# HT# HTM# PR# EFER# TK T TO TRST# THERM THERM THERMTRP# PROHOT# TMS GNNE# SM# 0M# SLP# RESERVE0 PWRGOO RESET# TESTH TESTH RESERVE VPWRG RESERVE RESERVE RESERVE SEL0 SEL /SKTO# V# OOTSELET OPTMZE/OMPT# HR#0 (,) HSTN# () PU_LK# () PU_LK () HRS#[0..] () V_G () HSTN# () NTR () HSTP# () HSTP# () NM () HSTP#0 () HSTN# () HST#0 () HST# () HREQ#[0..] () HSTP# () _SENSE () _SENSE () HSTN#0 () H#[..] () SEL0 (,) HT# () HTM# () H#[0..] () HEFER# () THERMP# () PU_G (,) HPR# () THERMN# () PURST# (,) FERR# () HS# () SEL (,) HSY# () HNR# () STPLK# () HNT# () HTRY# () HLOK# () 0M# () HRY# () SKTO# () TRMTRP# (,) PROHOT# (,,) SM# () SLP# () GNNE# () H#[0..] () V[0..] (,) TP_T () TP_TMS () TP_TRST# () TP_TK () TP_TO () GTLREF (,) PM# () PM# () PM# () PM# () PM# () PM#0 () TP_R# () OOT (,)

7 P PU VOLTGE LOK (,) V Voltage is from.v to.v. t is derived from.v. t should be able to source 0m. t drives the power logic of SEL[:0] and V[:0]. V to VG delay time is from ms to 0ms. V to VG deassertion time is ms for max. V_G U VN EN VOUT POK SN0-0m R.KST t must rout to the enable pin of PWM and K-0. VG to Vccp delay time is from ms to 0ms. VG rising time is 0ns. _V u-00_yv Near regulator Near processor.v 0m _V PU_OPLL t must close bulk caps. t support current if 00m. L L 0uH-00-00m 0uH-00-00m P PU E0 E E E E E0 E E F F F F F F F F F F 0 0 E0 E E E E E0 E F F F F F F F F 0 E E u-0_xr.v E 0u-0_YV 0V voltage drop should be less than 0mV V -VPRG -OPLL Y Y Y Y W W W W V V V V U U U U T T T T R R R R P P P P N N N N M M M M L L L L K K K 0 E E E E E E E E E F F0 F F F F F0 F F E E E E E E E E E E E F0 F F F F F F F F F G G G G H H H H J J J J K NORTH/PRES PU EOUPLNG PTORS P P P P P P P P 0u/.V properly in further P E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E X_u-0_XR E X_u-0_XR E X_u-0_XR E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E u-0_xr E X_u-0_XR E0 X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E0 X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E0 X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E X_u-0_XR E 0u-.V E0 0u-.V Solder side Place these caps within socket cavity Place these caps within north side of processor Place these caps within south side of processor MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen ntel mpg - Power Size ocument Number Rev VSE (MS-) ate: Monday, October, 00 Sheet of 0 0

8 H/W Project Leader : ndy hen VSE (MS-) 0 ntel Springdale - PU Signals MRO-STR Nt'L O., LT. 0 Monday, October, 00 Size ocument Number Rev ate: Sheet of H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# HREQ#0 HREQ# HREQ# HREQ# HREQ# HRS#0 HRS# HRS# HROMP H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H#0 H# H# H# H# _PLL _FS SEL SEL0 _FS _FS H_SY# PWRG H_SY# H_G PWRG H_G _GP R 0RST R KST R0.KST R KST R.KST 0p_XR 0.u_YV {VOLTGE} U ntel Springdale 0 L E K 0 J E0 J F F J G F E H K E F G0 J G 0 E F J L J K E L E G G E E K L0 L L E F 0 G G H H H H H0 H H H H0 H H 0 E 0 0 E E0 E G0 F E F J L G G F F E E J G E K J L J F F E K G G0 L E K J H0 G E E 0 E0 0 L L L K G F E N N P0 P R T T T T U U U0 V V V0 W W N0 W0 Y Y Y Y Y0 E E F J J J J J K K K K L L L M0 M M M T0 L0 L F F F F F0 F F F G J0 J J J J J0 J J J J K K K K K H K H H E F F F E F0 F E M F F J N P R R R K0 K K K K L M M M M M M0 M N N L L 0 R L L H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H_ST0# H_ST# REQ0# PR# NR# HLOK# S# HREQ0# HREQ# HREQ# HREQ# HREQ# HT# HTM# EFER# HTRY# SY# RY# RS0# RS# RS# HLKN HLKP PURST# PWROK RSTN# PROHOT# SEL0 SEL HROMP HSWNG HVREF H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# NV_0# NV_# NV_# NV_# H_STP0# H_STN0# H_STP# H_STN# H_STP# H_STN# H_STP# H_STN# _PLL _FS _FS _FS _FS H_SY# 0.u_YV U SZ0 R H#[0..] () H#[..] () HNR# () HS# () HSY# () HTRY# () HRY# () HTM# () HT# () HPR# () HLOK# () HEFER# () HRS#[0..] () HREQ#[0..] () HR#0 (,) HSTP# () HSTP#0 () HSTN# () HSTN#0 () HST#0 () HST# () HSTP# () HSTN# () HSTP# () HSTN# () PROHOT# (,,) H#[0..] () SEL0 () SEL () GTLREF (,) PRST_H# () PURST# (,) MH_LK () MH_LK# () _FS () _PLL () HSWNG () PWRG () H_G () PWRG ()

9 H/W Project Leader : ndy hen ts current is.. VSE (MS-) 0 ntel Springdale - Memory Signals MRO-STR Nt'L O., LT. 0 Monday, October, 00 Size ocument Number Rev ate: Sheet of M_ M_ M_ M_ M_0 M_ M_0 M_ M_ M_ M_ M_ M_ MQM_0 MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQS_ MQS_ MQS_0 MQS_ MQS_ MQS_ MQS_ MQS_ MQM_0 MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQS_0 MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_0 MQ_0 MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_0 MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MKE_ MKE_ MKE_0 MKE_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_0 MQ_ MQ_ MQ_0 MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MKE_ MKE_ MKE_0 MKE_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ XROMP SMVREF XOMPH XOMPL YROMP VREF YOMPL YOMPH _R R R_ R _R R R _R _R 0.0u_XR 0.0u_XR 0.0u_XR 0.0u_XR 0.0u_XR 0.0u_XR 0.0u_XR 0.0u_XR 0.u_YV 0.u_YV 0 0.u_YV U ntel Springdale R R R E M M N P L R P P P P R R R J0 E L E L F K G E L K L K J J J E E0 G K L K J E K H G F J J F E0 0 Y E 0 W0 U T V U R P R0 K L0 R R P L K0 H F G N M J G K F G E P0 P M N M0 L0 L P P M L P L N P M P M L N P L P P P P P M M N M N H G F H G E V V U U T T K K T P L L J H E F K J G F L0 N M0 P0 N M N M M M M N N N U T V W W W W G J E K G L F L J F L J0 E L L E Y G G E J U M J F G G H U0 L J0 G G0 F G N N J0 H K L N N0 R R P Y Y W Y J L K N L0 L L N P P J N N L M P P M E H P P M P0 F W M H N P P M0 F V M H K K P N N N K K M L P P K N L E L L P P P N N _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SKE_0 SKE_ SKE_ SKE_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_ SQ_0 SQ_ SQ_ SQ_ SKE_0 SKE_ SKE_ SKE R _R _R _R _R _R _R _R _R _R _R _R _R SS_0# SS_# SS_# SS_# SRS_# SS_# SWE_# SM_0 SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_0 SM_ SM_ SM_ SM_ SM_ SM_ SM_ S_0 S_ SM_0 SM_ SM_ SM_ SM_ SM_ SM_ SM_ SQS_0 SQS_ SQS_ SQS_ SQS_ SQS_ SQS_ SQS_ SMLK_0 SMLK_0# SMLK_ SMLK_# SMLK_ SMLK_# SMLK_ SMLK_# SMLK_ SMLK_# SMLK_ SMLK_# SMYROMP SMYOMPVOH SMYOMPVOL SMVREF_ SS_0# SS_# SS_# SS_# SRS_# SS_# SWE_# SM_0 SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_0 SM_ SM_ SM_ SM_ SM_ SM_ SM_ S_0 S_ SM_0 SM_ SM_ SM_ SM_ SM_ SM_ SM_ SQS_0 SQS_ SQS_ SQS_ SQS_ SQS_ SQS_ SQS_ SMLK_0 SMLK_0# SMLK_ SMLK_# SMLK_ SMLK_# SMLK_ SMLK_# SMLK_ SMLK_# SMLK_ SMLK_# SMXROMP SMXOMPVOH SMXOMPVOL SMVREF R _R.u_YV {VOLTGE} 0 MRS_# () M_[0..] () MS_# () MWE_# () M_ () M_0 () MRS_# () MS_#0 () M_0 () MS_# () MS_# () M_ () MWE_# () MS_# () MS_# () MS_# () MS_# () MS_# () MS_#0 () MQM_[0..] () MQS_[0..] () MLK_0 () MLK_#0 () MLK_# () MLK_ () MLK_ () MLK_# () MLK_# () MLK_ () MLK_# () MLK_ () MLK_# () MLK_ () MLK_# () MLK_# () MLK_# () MLK_ () MLK_0 () MLK_ () MLK_ () MLK_ () MLK_# () MLK_#0 () MLK_ () MLK_# () MQM_[0..] () MQS_[0..] () M_[0..] () MQ_[0..] () MQ_[0..] () MKE_[0..] () MKE_[0..] () M_[..] () M_[..] () _R () XROMP () XOMPH () XOMPL () YROMP () YOMPH () YOMPL () VREF () _R_ () _R_ ()

10 H/W Project Leader : ndy hen.v@0m VSE (MS-) 0 ntel Springdale - GP & HLink & LN Signals MRO-STR Nt'L O., LT. 0 0 Monday, October, 00 Size ocument Number Rev ate: Sheet of G G G G_E# G_E# _GP GSET G G G HL G ST0 HL0 HL HL G G G S0 GSWNG HL HL G G G0 G S S _GP_ HL HL G G G G_E#0 S S HL0 S S HL S GROMP HL G G _ROMP ST ST RF# G0 G G WF# G0 G G G _GP_ G HL_OMP G G0 _ G G G G_E# _GP _GP _GP _GP _GP _ R RST R.RST 0.0u_XR R.RST 0.0u_XR 0.0u_XR 0.0u_XR 0.0u_XR R.RST 0.0u_XR T 0u-V L 00nH-00m U ntel Springdale N P G R M P G F H E G H G H G F E G G K H F 0 F G E H G J J G F F F G K G K L L L J H J H H E E E E 0 W0 W W V Y Y W Y V W U T T T R P P P M Y W U V V N M N N N R0 R U V W H R P R R U U0 U T T U M M E E0 E E E E E E E E M M M M G0 F F F0 F F F F F F F0 F G G G G G G0 G G G G G G M M M M M M M N0 N N N N H F F K K K K0 K K K K H0 H H H H0 J J J J J R R R R P P P P0 P R R R T T V V V Y Y Y0 Y Y N0 N N N N N0 N R R R R0 R R K L L U U U U V V V V0 V V V V V0 W W W W Y Y Y Y Y 0 L L Y J J J K K K K J J L L L G Y 0 H H H0 H H H 0 K0 K K 0 Y0 T T T T0 T T T0 T T T P RESERVE RESERVE RESERVE RESERVE EXTTS# REFLK _LK _T VSY HSY LUE LUE# GREEN GREEN# RE RE# REFSET 0 0 STRF STRS _ROMP _SWNG _VREF H0 H H H H H H H H H H0 H_STRS H_STRF H_ROMP H_SWNG H_VREF G0/VO_HSY G/VO_VSY G/VO_ G/VO_0 G/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G0/VO_ G/VO_ G/VO_0 G/VO_LKNT G/VO_FLSTL G/M_T G/VO_VSY G/VO_HSY G/VO_LNK# G/VO_0 G0/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G/VO_ G/VO_0 G0/VO_NTR# G/VO_FLSTL GE0/VO_ GE/VO_LNK# GE GE/VO_ GSTF0/VO_LK GSTS0/VO_LK# GSTF/VO_LK GSTS/VO_LK# GREQ GGNT GST0 GST GST GRF GWF GFRME/MV_T GRY/MLK GTRY/MV_LK GEVSEL/MT GSTOP/M_LK GPR/_ETET GLKN GS0#/_0 GS#/_ GS#/_ GS#/_ GS#/_ GS#/_ GS#/_ GS#/_ GSSTS GSSTF _H _LO GROMP/VO_ROMP GVSWNG GVREF RESERVE _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP _GP GGNT# () G[0..] () S[0..] () ST[0..] () G_E#[0..] () _ST0 () _ST#0 () _ST () _ST# () GREQ# () RF# () WF# () MH_ () S_ST () S_ST# () GTRY# () GPR () GFRME# () GSTOP# () GRY# () GEVSEL# () HL[0..0] () V () VL () RT_ () RT_G () RT_R () RT_VSY () RT_HSY () OT_ () HL_STRF () PPE# () _LO () GP_REF () GSWNG () HL_STRS () HL_VREF () _VREF () _SWNG () HL_SWNG ()

11 H/W Project Leader : ndy hen H ecoupling apacitors H Pull-Up / own Resistors ll caps be placed less than 00mils. Solder Solder Solder VSE (MS-) 0 ntel H - P & E & Signals MRO-STR Nt'L O., LT. 0 Tuesday, October, 00 Size ocument Number Rev ate: Sheet of _SN _SN PGNT# S P P P PGNT# PREQ# S P P0 0 0 P P PREQ#0 P P S S PGNT# _E#0 S P _E# S P S S0 PREQ# PREQ# 0 S P _SN PGNT# 0 S P PREQ# _E# S S S0 P _SN PGNT#0 S S P0 PGNT# PREQ# _E# S P SOUT SY SUS_ SUS_ SUS GP _GP _GP _GP VS VS VS VS _VS R R R 0K R 0K 0 0.0u_XR 0.u_YV {VOLTGE} 0.0u_XR 0 U ntel H F G H K L M0 N0 P R V W W W 0 G G E F0 F K0 K K L P R0 R H J K M N N E F F W R W W W E F Y F F Y Y Y Y Y Y 0 0 Y 0 W W W V V0 Y Y Y Y0 W0 Y J J G K H H J J K F M H L G K G G L P H N N E P N F P F P E J N M M E L E F K L L V N V E E E E E E E0 E E F F E E E E F F F K U V W W0 W LN_/SUS_ LN_/SUS_ LN_/SUS _S _S _S _S S _S _S _S SUS_ SUS_ SUS_ SUS_ LN_/SUS_ LN_/SUS_ P0 P P P P P P P P P P0 P P P P P P0 P P PS# PS# POR# POW# PORY PREQ PK# RQ S0 S S S S S S S S S S0 S S S S S S0 S S SS# SS# SOR# SOW# SORY SREQ SK# RQ /E0# /E# /E# /E# FRME# RY# TRY# EVSEL# STOP# PR PERR# SERR# PLOK# PME# PLK PRST# PRQ# PRQ# PRQ# PRQ# PRQE#/GP PRQF#/GP PRQG#/GP PRQH#/GP REQ0# REQ# REQ# REQ# REQ#/GP0 REQ#/GP0 REQ#REQ#/GP GNT0# GNT# GNT# GNT# GNT#/GPO GNT#/GPO GNT#/GNT#/GPO _SN0 _SN _SN _RST# _SOUT _SY _T_LK SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS S _S _S RN 0u-00_YV P_PME# (,,0) SERR# (,,0) S_ () PR (,,0) PGNT#[0..] (,,0,) RY# (,,0) [0..] (,,0,) P_OW# () S_OR# () PRQ# (,0) S_S# () P_ () FRME# (,,0) P_REQ () PREQ#[0..] (,,0,) P_ () PRQ#E (,0) P_S# () S_ () TRY# (,,0) PRQ# (,0) EVSEL# (,,0) S_0 () LOK# (,0) PRST_H# (,,,) P_K# () S_OW# () PRQ#F (,0) P_ORY () P_OR# () RQ () P_S# () PRQ# (,0) RQ () STOP# (,,0) S_K# () PRQ# (0) P_0 () PRQ#H (0) _E#[0..] (,,0) S_ORY () PERR# (,,0) S_S# () PRQ#G (,0) S_REQ () _SN0 () _TLK () _RST# () _SOUT () _SY () H_PLK () S[0..] () P[0..] () PGNT# (0) PREQ# (0) R_ ()

12 PROHOT_LTH () (,) SO_SM# (,) PS_ETET () S_PME# () PRO_HOT# () FU_ET# FN_M () HSS_0 () HSS_ () HSS_ () PSWR (,) N_ENLE# () STLE# () (0) HL[0..0] R 00 () EE_O () US () US- () US0 () US0- () US () US- () US () US- () US () US- () US () US- () O# () O# () O# (,) FRONT_US_ET# () O# R () US_ () HL (0) HL_STRF (0) HL_STRS () H_OMP () H_SWNG () H_VREF () H_.RST HL0 HL HL HL HL HL HL HL HL HL HL0.V () VREF 00mV lose of H. U LN_RST# EE_O US_S 0.0u_XR 0.0u_XR 0 E 0 0 F H0 H J0 H M M N M0 L J K G K J N L0 L N LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX ntel H W LN_RST# E0 LN_LK 0 LN_RSTSY EE_N EE_OUT 0 EE_S EE_SHLK USP0P USP0N USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN O0# O# O# O# O#/GP O#/GP0 O#/GP O#/GP USRS USRS# LK H0 H H H H H H H H H H0 H H_STF H_STS HROMP H_VSWNG HREF LK VREF VREF _S E VREF_SUS VT RT _GP STPLL STPLL _GP USPLL P R R T V_PU_O V_PU_O V_PU_O R U Y W W GPUSY#/GP GP GP GP GP U T0 U R U0 F STP_P#/GPO SLP_S#/GPO STP_PU#/GPO0 _STT#/GPO PUPERF#/GPO SSMUXSEL/GPO LKRUN#/GPO W V W T G F GPO GPO GPO GPO GPO GPO G G0 G H H H J J J K K K K0 K K L0 L L L L L L L M M M M M M M M N N N N N0 P P0 P P P P P P R R T T T U V V W W Y Y Y Y Y0 Y T T SUS_STT# TLOW# SUSLK THRM# THRMTRP# ST0RXP ST0RXN STRXP STRXN ST0TXP ST0TXN STTXP STTXN STRSP STRSN LK00P LK00N L0 L L L LFRME# LRQ0# LRQ#/GP SERRQ SMLK SMT SMLNK SMLNK0 0M# FERR# GNNE# NT# NTR NM SM# PU_SLP# STPLK# RN# 0GTE PSLP# PRSLPVR PWRTN# PWROK PUPWRG/GPO VGTE/VRMPWRG SYS_RESET# RTRST# RSMRST# SLP_S# SLP_S# SLP_S# NTERVEN NTRUER# LNKLERT# SMLERT#/GP LK RTX 0 0 Y Y T R R U T U R F V U R R U R V P T P T R P0 Y P R0 U W U 0 Y V F0 E ST_S LP_0 LP_ LP_ LP_ PWROK RSMRST# NTERVEN R R0 R Y.KHz-.pF-0PPM RT_XO RTX R# SPKR SUS_STT# () TTLOW# () SUSLK (,) THERM# () H_TRMTRP# () ST_RX0 () ST_RX#0 () ST_RX () ST_RX# () ST_TX0 () ST_TX#0 () ST_TX () ST_TX# ().RST ST_00 () ST_00# () LP_FRME# (,,) LP_RQ#0 () LP_RQ# () SERRQ (,,) SMLK (,) SMT (,) SM_LNK (0,) SM_LNK0 (0,) 0M# () FERR# (,) GNNE# () HNT# () NTR () NM () SM# () SLP# () STPLK# () KRST# (,) 0GTE (,) PWRTN# () RSTTN# () RT_RST# () RSMRST# (,) SLP_S# (,) SLP_S# (,) SLP_S# () 0K VT K HOO_SENSE# (,) LNK_LERT# () SM_LERT# () p-npo 0V R0 0M p-npo R# (,) SPKR () LP_[0..] (,,) R H_G (,) PU_G () VRM_G () H_ () PWRTN# RSMRST# R.K R 0 Support nternal SUS_ regulator install R0. MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen ntel H - Other Signals Size ocument Number Rev VSE (MS-) VS ate: Monday, October, 00 Sheet of 0 0

13 F T 0u-V LE (,,,) SM_LK (,,,) SM_T V 0 lock Generator - Y0 U PU0 0 PU_V PU0# PU PU# PU_ PU PU# SR_V SR SR# SR_ 0 V_V V_ P_V P_ P_V P V _ REF_V REF_ V SLK ST S0 / Y0 0 V_0 V_ MOE#/V_ VH/V_ FS_/P_F0 FS_/P_F FS_E/P_F P0 P P P P P OT_M US_M Trace length less than 0.inchs FS_/REF0 FS_/REF X X _G# 0 RST#/PWR_N# REF MHLK MHLK# PULK PULK# TPLK TPLK# ST00 ST00# MH GPLK H LNPLK PLK PLK0 PLK PLK PLK HPLK FWHPLK SOPLK OT US FS_SEL0 FS_SEL PLL_X PLL_XO V_G# PWR_N# REF R R R0 R R R R0 R R R R R R R R R R R R R0 R R R R 0K R R R R 0K p_npo Y M-pf-HS- p_npo R0 R0 K RST MH_LK MH_LK# PU_LK PU_LK# TP_LK TP_LK# ST_00 ST_00# MH_ GP_LK H_ FWH_PLK OT_ US_ MH_LK () MH_LK# () PU_LK () PU_LK# () TP_LK () TP_LK# () ST_00 () ST_00# () MH_ (0) GP_LK () H_ () LN_PLK () P_LK (0) P_LK0 (0) P_LK (0) P_LK () P_LK () H_PLK () SO_PLK () SE_PLK () OT_ (0) US_ () SEL0 () SO_ () _ () H_ () SEL () SEL0 SEL PU_LK PU_LK# MH_LK MH_LK# TP_LK TP_LK# ST_00 ST_00# MH MH (NPTH) (NPTH) R R R0 R0 R0 R0 R R R R K K EM HF filter capacitors, located close to PLL lock Generator Power own lock V_G#.RST.RST.RST.RST.RST.RST.RST.RST Q N0S MH MH (NPTH) (NPTH) VG R R K X_K Mounting Holes R.K MH MH PLK LNPLK PLK0 PLK MH_ H_ GP_LK OT_ US_ (NPTH) (NPTH) R.K R.K R.K R.K p_npo p_npo p_npo p_npo p_npo G_0MS () V_G () MH MH (NPTH) (NPTH) Firware Hub (FWH) OS PROTET LOK () PRST_H# () HOO_SW_ET () RSER_ET# () RSER# () OS_WP# (,,) LP_0 (,,) LP_ (,,) LP_ FWH_VPP TL# R.K RSER# OS_WP# TL# FGP OS VPP RST# FGP FGP FGP FGP0 WP# TL# OS_Mbit LK FGP (VL) NT# FWH RFU 0 RFU FWH0 RFU FWH RFU FWH RFU FWH FWH_PLK OL_ONN OL_ONN () NT# R.K LP_FRME# (,,) LP_ (,,) HGH LOW R.K TL# OS Update onfig. Un_protected Protected efault JOS YJ0 Optics Orientation Holes FM FM FM FM FM FM FM FM FM FM FM0 FM FM FM FM FM FM Simulation SM J SM J FWH ecoupling apacitors FWH Strapping Resistors FWH_VPP Q NS00S HOO_SW_ET OS_WP# R.K R.K V R.K FWH_VPP_EN Q NS00S Place ap. as lose to every pin of FWH< 0 mil. RSER# OL_ONN FGP R.K R.K R0 K MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen Y0 & FWH Size ocument Number Rev VSE (MS-) ate: Monday, October, 00 Sheet of 0 0

14 (,,) LP_[0..] () PRST_H# () SO_PLK (,,) SERRQ () LP_RQ#0 (,) LP_FRME# () RSMRST# () PWTN# () PWRTN# () PS_ON# () PWRG (,) G_0MS () G_0MS# () SLP_S# () SLP_S# () SO_SM# (,,0) P_PME# () R# () V_SW_UX () V_SW_MN# () V_SW_TRL# () SO_TRMTRP# () SUSLE () PLE (,,0) PRST# () PRST# () E_RST# () E_RST# () M_EV_ET# () M_POWER_ON# () TET0 () TET () M_PT_ET# () SKTO# () SE_TPM_PRES () HOO_LOK# () HOO_UNLOK# () SYS_FN () PU_FN () NS VN R.K LP_0 LP_ LP_ LP_ PWRTN# PS_ON# PWRG G_0MS G_0MS# SO_TRMTRP# VS P# M_EV_ET# M_POWER_ON# R_V M_PT_ET# SYSOPT GP SKTO# SE_TPM_PRES HOO_LOK# HOO_UNLOK# F_M OMM ET# R_V0 MR# R KST V R.KST () SLP_S# () V_US_UX () V_US_MN# F 0-00m VP 0.0u_XR MR# VN LP SUPER /O LP U LRESET# LLK SERRQ LRQ# LFRME# LP_P# L0 L L L RSMRST# PWRTN_N#/GP 0 PWRTN_OUT#/GP PS_ON#/GP PWRGOO 0 PWRG_0M/RQ/GP 0 PWRG_0M#/RQ0/GP PS_EN/FN_TH/GP SLP_S#/GP SLP_S#/GP O_SM#/GP PME_N#/GP O_PME#/GP V_SW_UX/WOL#/GP V_SW_MN#/EVENT#/GP S_V_TRL#/EVENT#/GP THERMTRP#/GP OLOR/GP0 LNK_GR/GP GPRST#/GP0 GPRST#/GP GPRST#/GP0 GPRST#/GP R/GP GP GP0/P GP/P GP/P RNG#/GP SYSOPT/GP NTRUER#/GP PUO#/GP PUO#/GP HLOK#/GP HUNLK#/GP WO/GP RQ/GP FN_TH/GP FN_TH/RQ/GP FN_TH SMS LP G0/GP 0 MR# KRST#/GP KT 0 VN KLK 0 VN MST MSLK 00 US_PWR#/ROFF/RQ/GP0 0 V_US_UX/RQ/GP LK_M 0 0 V_US_MN#/RQ/GP SUSLK RVEN0/GP0 RVEN/OHK#/GP NEX# MTR#0 S#/GP S#0 MTR#/GP R# STEP# WT# WGTE# TRK0# WP# RT# HE# SKHG# P0 P P P P P P P SLT PE USY K# SLN# NT# ERR# F# ST# RRX/GP RTX/GP R# RX TS# # SR# TX RTS# TR# R#/GP0 RX/GP/RRX TS#/GP #/GP SR#/GP TX/GP/RTX RTS#/GP TR#/GP VTR VTR VT _ 0 RVEN0 NEX# MO# S# S# MO# R# STEP# WRT# WE# TRK0# WP# RT# HE# SKHG# PR0 PR PR PR PR PR PR PR SLT PE USY K# SLN# PNT# ERR# F# RST# R# SN TS# # SR# SOUT RTS# TR# R# R# () SN TS# # SR# SOUT RTS# TR# it0 of 0xF0 of evice setup 0. KT# KLK# MST# MSLK# 0 u-00_yv SYSMG_NT () OS_WP# () FN_LMP () R# () 0GTE () KRST# () SO_ () SUSLK () VS VT N# NSR# NRTS NSOUT NSN NTR TS# NR# MST# MSLK# KT# KLK# U 0 N# RN NSR# RN NSN RN TS# RN RN RTS# SOUT N TR# N N K# USY PE SLT F# ERR# PNT# SLN# PR0 PR PR PR PR PR PR PR RST# 0 SERL PORT T-SOP0 N 0p_NPO N 0p_NPO U R R R R R R R R RRP RRP RRP RRP RRP RRP RRP RRP RRP P SZ L RN.K V ROUT ROUT ROUT ROUT F F F F ROUT N# NSN NSOUT NTR RRN RRN RRN RRN RRN RRN RRN RRN RRN U_ # SR# SN TS# PRN0 PRN PRN PRN PRN PRN PRN PRN ST# NSR# NRTS TS# NR# PS KEYOR & MOUSE ONNETOR 0-00m 0-00m 0-00m 0-00m 0 0 LPT YNF-00- MS_T MS_K K_T K_K NS NRTS OUT NSOUT OUT NTR OUT 0 U_0 NS V- LPT_V 0 N 0p_NPO NR# () NR# () V -V R K NRTS NSR# TS# NR# N# NSOUT NSN NTR NS JKMS 0 MS K YMP- U 0 TS# RN NSR# RN NSN RN N# RN RN RTS# TR# N SOUT N N SERL PORT N 0p_NPO N 0p_NPO F T-SOP0 N# NSN NSOUT NTR PRLLL PORT ST# PRN0 PRN PRN PRN PRN PRN PRN PRN K# USY PE SLT U_ V ROUT TS# ROUT SR# ROUT SN ROUT # ROUT NRTS OUT NTR OUT NSOUT OUT 0 U_0 V- LPT YNF-00-0 F OM 0 PN* F# ERR# PNT# SLN# NSR# NRTS TS# NR# OMM ET# US_STR FS.-microSM0 POLY SWTH LP /O STRPPNG RESSTOR FLOPPY ONNETOR PSSWOR LER SKTO# () HOO_SENSE# OMM ET# HOO_LOK# HOO_UNLOK# M_PT_ET# M_POWER_ON# M_EV_ET# SO_TRMTRP# GP R SYSOPT SE_TPM_PRES R R 0M M R.K R.K R.K R.K R.K R.K R.K R.K R.K R R 0K 0K VT R R K K R_V0 R_V R_V0, R_V PULLOWN FOR NTL VERSON. PWRTN# G_0MS G_0MS# PWRG MR# E_RST# E_RST# V_US_UX V_US_MN# V_SW_TRL# R R0 X_.K X_.K R.K R0.K R.K R.K R.K R0 X_.K R R0 R R R K K K K K VS VS VS VS VS _S _S _S F RVEN0 F_M NEX# MO# S# S# MO# R# STEP# WRT# WE# TRK0# WP# RT# HE# SKHG# N-H-x-:.-K NEX# TRK0# WP# RT# SKHG# F_M R 0 R 0 R 0 R 0 R 0 R K PSW YJ0 WOR PSSWOR LER Function ON NORML OFF LER R 0 PSWR () MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen LP SUPER /O & ONNETORS Size ocument Number Rev VSE (MS-) ate: Monday, October, 00 Sheet of 0 0

15 () _ () _RST# () _SN0 () _SOUT () _SY () _TLK R R R R R R U_ X_p_NPO UX_L UX_R K K X_K X_.K _L R 0# # JS0 S_PF U V V R0 X_.K R0.K XTL_N XTL_OUT RESET# ST_N ST_OUT 0 SY T_LK P_EEP PHONE TEST TEST JS VEO_R VR / UXL UXR TEST TEST VEOL VEOR 0 OUTR TEST OUTL L R 0 V MONO M M LNL LNR LOUTR LOUTL VR VR FLT FLT VREF V N_R N_L 0 - HP_ROUT HP_LOUT U_ U_ U_ U_ U_0 U_ VR _VREF VR u-00_yv VR u-00_yv u-00_yv R R 0.0u_XR 0 R0.K R0.K R0.K R0.K 0p_XR OE NR 0p_XR NL 0p_XR 0p_XR 0p_XR 0 0p_XR LNE_N J PHONE_JK M_N V M_N_L 0.u_YV () FU_ET# VR S_PF UO OE REGULTORS R.KST M_S HP_R FU_ET# HP_L VR LML0-SOT N R.K 0.u-00_YV 0p_XR R0.K OUT FRONT UO M_N_R UO M M_ FPOUT_R RET_R ET# KEY FPOUT_L RET_L 0 FRONT_UO M_PWR FU_ET# 0.0u_XR R.K R0 R T 0u-V VR OUT_R OUT_L M_S RST HP_L RST OUT_L VR M_N 0 MN R0.K HP_LOUT T 00u-V R0 0 HP_L VR R 0.u-00_YV M_PWR R.K M R0 VR M_N R 0.u-00_YV M_PWR MN R.K R.K 0p_XR 0p_XR M M_N J PHONE_JK HP_ROUT T 00u-V R R 0 HP_R UX N OPPER F OUT_R OUT_L F p_XR F p_XR JS MONO_R MONO_L R0.K 0 u-00_yv u-00_yv HP_RO MONO_R_R MONO_L_R HP_LO LNE_OUT J PHONE_JK UX_R UX_L u-00_yv u-00_yv R0 R R.K R.K R0.K R.K UXR UXL UX YJ0-Y (White).mm N MONO_R MONO_L () SPKR R R 0K R R 0K 0K 0K MONO_RL R 00K R_SPKR u_XR R 0K 0 0.0u_XR u-00_yv MONO_O nternal Speaker SPKR_OUT R R 0K 0K MONO_OUT R KST R.KST VR V VOL_TRL 0 U V V S_ P_ T 0u-V MP_ MONO_OUT MONO_OUT- OUT OUT- 0 T0T(W) F NTL_SPK SP _R L u-00_yv u-00_yv u-00_yv R.K _R _G _L R.K R.K 0p_XR 0 0p_XR R.K R R.K G R0.K 0p_XR MRO-STR Nt'L O., LT. YJ0- (lack).mm H/W Project Leader : ndy hen UO - / Size ocument Number Rev VSE (MS-) L ate: Monday, October, 00 Sheet of 0 0

16 (,,0,) [0..] (,,0) _E#[0..] (,,0) FRME# (,,0) RY# (,,0) TRY# (,,0) EVSEL# (,,0) STOP# (,,0) PR (,,0) PERR# (,,0) SERR# (,0,) PREQ#0 () PGNT#0 () N_SEL (,0) PRQ#E (,,,0) P_PME# () LN_PLK () PRST# R.K _E#0 _E# _E# _E# LN_TRST# N M P P N M P N P N N M M M L L K E M L F F F G H H J J J H F U VS LN E#0 _E# _E# _E# K L P FRME# RY# TRY# EVSEL# STOP# PR PERR# SERR# REQ# GNT# SEL NT# PME# PLK P_RST# T TO TMS TK TRST# MEN VP VP VP VS roadcom M0 R 0 R F K L V_O V_O V_O V_O V_P E E G K L N P V_P V_P V_P V_P V_P V_P V_P V_P V_P V_P LN_ R 0 E H H H H J J J J J J0 K K K K K K0 M L L0 N P P P P PLL_V PLL_V VL V V V V V V V V V V V V V V V V V V V V V V V V V V E E E E E E F F F F F F0 G G G G G G G0 K H M M M L L N N N F V V F F VL VL H P V_PLL V_PLL LN_ J H H0 J J K K L L L L M M M N V_XTL PM- code 0 TR_0 TR_0- TR_ TR_- TR_ TR_- TR_ TR_- E E REG_SUP REG_TL REG_SEN 0 REG_SUP 0 REG_TL REG_SEN GPO0 GPO GPO SP00LE# SP0000LE# LNKLE TRFFLE SM_LK SM_T EELK EET /EEN /EEOUT VES VES VES H K J H G G G 0 M0 P0 N P P G 0 S# H SLK E SV VUX/PRSNT R S E0 SO G X N J TR_ TR_- TR_0 TR_0- TR_ TR_- TR_ TR_- TL TL WP# 00_LE# G_LE# TR_LE EE_LK R EE_T R EE_O EE_ R L_X V_S R VUX R R R0 R EE_S# EE_SLK R R0 0 X_K Y M-pF-0ppm-HS N0 L_XO R 0 XO XO TR_0 () TR_0- () TR_ () TR_- () TR_ () TR_- () TR_ () TR_- () K.KST.RST R.K VS LN_ LN_ LN_ LN_ VS 00_LE# () G_LE# () TR_LE () SMLK (,) SMT (,) K VS K VS K VS K VS 0 p_npo R 0K 0 p_npo LN_ VS LN EEPROM LN VOLTGE REGULTON f use Motorola MJH 0.inch square to dissipate the heat. TL Vf=0mV when d=0m TL EE_T EE_LK EE_O EE_ EE_LK EE_T Q MJH-TO Q MJH-TO PLL_V elete Voltage drop to prevent heat generate from P within.v Vce. emo board measure over 0degree within normal NWTEST in one client. LN PLL VOLTGE LOK m@ 0.W f use Motorola MJH.inch square to dissipate the heat. 00m@ 0.0W These transistors must away from the M0 with.inch. NOT NSTLL NSTLL 0 U S SK O X_T U0 0 SL S T F ORG WP WP# M0 U0,Q,Q,Z R,R,R,R U 0.u_YV T 0u-V T0 0u-V VS VS VS 0.0u_XR LN_ 0.0u_XR LN_ 0.0u_XR LN_ LOW_PWR R0 0 R 0 LKRUN# For 0M only R0 R LN VL VOLTGE LOK LN V VOLTGE LOK V F 0.u_YV LN_ VS 0.0u_XR LN ecoupling apacitors lose chipset, and trace length is less than 0mils. V_P 0 0.0u_XR 0 0.0u_XR LN_ 0 0.0u_XR 0 LN_ 0 0.0u_XR TR_ TR_- TR_ TR_- TR_0 TR_0- TR_ TR_- 00_LE# G_LE# R0 R R R R R R R.RST.RST.RST.RST.RST.RST.RST.RST R 0 R 0 LN_ VS VS VL 0 F 0.u_YV MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen roadcom M0 Size ocument Number Rev 0 VSE (MS-) LN_ ate: Monday, October, 00 Sheet of 0

17 R MM R MM R Terminational Resisitors () M_[0..] () M_0 () M_ () MS_#0 () MS_# () MRS_# () MS_# () MWE_# () MQS_[0..] () MQM_[0..] () MKE_0 () MKE_ (,,,) SM_LK (,,,) SM_T () MLK_ () MLK_# () MLK_0 () MLK_#0 () MLK_ () MLK_# _R _R M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_0 M_ MRS_# MS_# MWE_# MQS_0 MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQM_0 MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ SM_LK SM_T MM 0 0/P / / 0 / S0# S# /S# /S# RS# S# WE# QS0 QS QS QS QS QS QS QS QS QM0/QS QM/QS0 QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS ME0 ME ME ME ME ME ME ME KE0 KE SL S S0 S S K0/ K0#/ K/K0 K#/K0# K/ K#/ MM--K SGNLS _V POWER SP_V V V V V V V V V V 00 0 R.=00000 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q VREF WP 0 FETEN/ 0 /RESET# MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ R_VREF 0.u_YV-00 _R _R _R MQ_[0..] () () M_[..] R RST R RST 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 _R () MS_# () MS_# () MKE_ () MKE_ () MLK_ () MLK_# () MLK_ () MLK_# () MLK_ () MLK_# 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 _R _R M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M R M_0 M_ MRS_# MS_# MWE_# MQS_0 MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQM_0 MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ SM_LK SM_T MM 0 0/P / / 0 / S0# S# /S# /S# RS# S# WE# QS0 QS QS QS QS QS QS QS QS QM0/QS QM/QS0 QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS ME0 ME ME ME ME ME ME ME KE0 KE SL S S0 S S K0/ K0#/ K/K0 K#/K0# K/ K#/ MM--K SGNLS _V POWER SP_V V V V V V V V V V 00 0 R.=0000 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q VREF WP 0 FETEN/ 0 /RESET# MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ R_VREF 0.u_YV-00 _R MQS_ MQM_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQS_ R -00 MQM_ R -00 MQ_ R -00 MQ_ R0-00 MQ_ R -00 MQ_0 R -00 M_ M_ M_ M_ M_ RN -00 RN -00 RN -00 RN -00 _R _R RN -00 M_ M_ M_ M_ M_ M_ M_ M_0 M_0 MS_# MS_# MS_# MS_# MKE_0 MKE_ MKE_ MKE_ RN -00 RN0-00 RN -00 RN -00 RN -00 M_ M_ M_ M_ M_ R R R R R M_0 R -00 MRS_# R -00 MWE_# R00-00 MS_#0 R0-00 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQM_0 MQS_0 MQM_ MQ_ MQS_ MQ_ MQS_ MQ_ MQ_ MQ_ MQ_ MQ_ MQM_ MQM_ MQS_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQM_ MQ_ MQS_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQS_ MQM_ EOUPLNG PTORS _R _R _R 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 Place these decoupling capacitors close to _R termination resistors. One decoupling capacitor for each R-pack. MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen R MM & Size ocument Number Rev 0 VSE (MS-) RN -00 RN -00 RN -00 RN0-00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN0-00 RN -00 T 0u-.V T ate: Monday, October, 00 Sheet of 0 _R 000u-.V 0 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00

18 R MM R MM R Terminational Resisitors () M_[0..] () M_0 () M_ () MS_#0 () MS_# () MRS_# () MS_# () MWE_# () MQS_[0..] () MQM_[0..] () MKE_0 () MKE_ (,,,) SM_LK (,,,) SM_T () MLK_ () MLK_# () MLK_0 () MLK_#0 () MLK_ () MLK_# _R _R _R M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_0 M_ MRS_# MS_# MWE_# MQS_0 MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQM_0 MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ SM_LK SM_T MM 0 0/P / / 0 / S0# S# /S# /S# RS# S# WE# QS0 QS QS QS QS QS QS QS QS QM0/QS QM/QS0 QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS ME0 ME ME ME ME ME ME ME KE0 KE SL S S0 S S K0/ K0#/ K/K0 K#/K0# K/ K#/ MM--K SGNLS _V POWER SP_V V V V V V V V V V 00 0 R.=0000 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q VREF WP 0 FETEN/ 0 /RESET# MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ R_VREF 0.u_YV-00 _R _R _R MQ_[0..] () () M_[..] R RST R RST 0.u_YV u_YV-00 0.u_YV-00 0.u_YV u_YV u_YV-00 _R () MS_# () MS_# () MKE_ () MKE_ () MLK_ () MLK_# () MLK_ () MLK_# () MLK_ () MLK_# _R _R _R 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_0 M_ MRS_# MS_# MWE_# MQS_0 MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQS_ MQM_0 MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ MQM_ SM_LK SM_T MM 0 0/P / / 0 / S0# S# /S# /S# RS# S# WE# QS0 QS QS QS QS QS QS QS QS QM0/QS QM/QS0 QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS QM/QS ME0 ME ME ME ME ME ME ME KE0 KE SL S S0 S S K0/ K0#/ K/K0 K#/K0# K/ K#/ MM--K SGNLS _V POWER SP_V V V V V V V V V V 00 0 R.=000 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q VREF WP 0 FETEN/ 0 /RESET# MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ R_VREF 0.u_YV-00 _R MQ_ MQ_ RN MQM_0 MQS_0-00 MQ_ MQ_ RN MQ_ -00 MQ_ MQM_ MQ_ RN MQS_ -00 MQ_ MQ_0 R0-00 MQ_ R0-00 MQ_ R0-00 MQM_ R MQ_ R MQ_ R0-00 MQ_ R0-00 MQ_ R -00 MQM_ R -00 MQS_ R -00 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_0 M_ MS_# MS_#0 MS_# MS_# MKE_0 MKE_ MKE_ MKE_ RN -00 RN -00 RN -00 RN0-00 RN -00 RN -00 MS_# R -00 MRS_# R -00 MWE_# R -00 M_0 R -00 M_ R -00 M_ R -00 M_ R0-00 M_ R0-00 M_ R -00 M_ R -00 _R _R EOUPLNG PTORS Place these decoupling capacitors close to _R termination resistors. One decoupling capacitor for each R-pack. MRO-STR Nt'L O., LT. H/W Project Leader : ndy hen R MM & Size ocument Number Rev 0 VSE (MS-) MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQM_ MQ_ MQS_ MQ_ MQ_ MQS_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQM_ MQ_ MQ_ MQS_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_ MQ_0 MQ_ MQ_ MQ_0 MQ_ MQS_ MQM_ MQS_ MQM_ MQ_ MQ_ RN -00 RN -00 RN -00 RN -00 RN0-00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 RN -00 ate: Monday, October, 00 Sheet of 0 _R _R _R _R T 0.u_YV-00 0.u_YV u-.V 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV u_YV-00 0.u_YV-00 0.u_YV-00