Version 300. CPU: Willamette/Northwood mpga-478b Processor

Transcription

1 MS- Version 00 NTL (R) rookdale- hipset Willamette/Northwood pin mp- Processor Schematics PU: Willamette/Northwood mp- Processor System rookdale- hipset: NTL MH (North ridge) NTL H (South ridge) On oard hipset: xpansion Slots: OS -- FWH ' odec -- L0 LP Super /O -- WHF-W lock eneration -- S0F LN -- ntel T P. SLOT * Page over Sheet lock iagram Voltage istribution eneral SP lock S0F & T00 ONNTORS mp- NTL PU Sockets NTL rookdale- MH -- North ridge NTL H -- South ridge LP /O -- WHF-W R MM& and R Terminator Resistor P Slot V onnector P SLOT & & FWH & NR US onnectors 0 ' odec L0 & onnectors - O onnectors FN &.V Votlage Regulator W0 P ontroller VRM. -- PU Power Front Panel & TX onnectors RealTek 0L P Lan / M ontroller Manual Parts MOL onfig. OR onfig. Function RP Number MS ST MS Option:L MSM ST MSM Option:L cfg-st cfg-ln cfgm-st cfgm-ln ST STntel LN STM STMntel LN 0--0S 0--0S MS MRO-STR NT'L O.,LT. over Sheet 00 MS- ate: Monday, May, 00 Sheet of

2 lock iagram VRM NT & PWR-MN PLK MHZ P -Pin Processor T TRL R TL US T TRL R X'TL.MHZ PULK, PULK# 00/MHZ MHLK, MHLK# 00/MHZ MH_ MHZ OT_LK MHZ lock 0 enerator PLK MHZ H_ MHZ H_PLK MHZ FWH_PLK MHZ SO_PLK MHZ PLK0,,, MHZ LN_PLK MHZ SO_ MHZ H_ MHZ P / Slot P US / L H_.MHZ V onnector V US P 0 Pin _P.V MM_STR.V R US R R HU LNK US Primary UltraM /00 H_ MHZ H_PLK MHZ PLK0,,, MHZ P Slot P Slot P Slot Secondary H H_ MHZ H_.MHZ NR Slot ' Link / LN / PROM FW0 _S V P _S.V.V _S.V _P.V NT & PWR-MN P US LN_PLK MHZ RealTek 0L LN hip LP US Onboard ' odec US PORT LP SO SO_PLK MHZ SO_ MHZ FWH_PLK MHZ FirmWare Hub OS udio port US Port US Port US Port Mouse Floopy Parallel ame Port MS MRO-STR NT'L O.,LT. US Port US Port US Port Keyboard Serial, lock iagram MS- 00 Monday, May, 00 ate: Sheet of

3 Power elivery Map VS /-% TX P/S with Stby current V.V V -V /-% /-% /-% /-0% V voltage regulator VRM /0.V regulator Processor V.V 0m VccOR/Vtt.V-.V 0 MH VccOR.V. VccP.V 0m VccH.V 0m.V regulator.v Standby regulator VttFS.V-.V. VccSM.V..V Standby regulator.v regulator Memory Vdd/Vddq.V. Vtt.V. VccPO.V 0m Vcca_.V m H VccOR.V 0m VccH.V 0m.V Standby regulator Vccsus_.V m V_PU_O.V-.V m Vcc_.V 0m Vccsus_.V 0m K-0 Vcc.V 0m LP Super /O Vdd.V m NR onnector V.0.V.0 V 0..Vaux.0 -V 0. Vual 0. P Slot (per slot) V.V V.Vaux -V P Slot V.0.V.0 V.0.Vaux 0..V.0 US Vdd V.0 FWH Vdd.V m MS MRO-STR NT'L O.,LT. Power elivery Map 00 MS- ate: Monday, May, 00 Sheet of

4 eneral SP H PO Pin Type Function PO 0 PO PO PO PO RQ# (multifunction pin) RQ# (multifunction pin) Pull up through.k ohms (PRQ#) Pull up through.k ohms (PRQF#) Pull up through.k ohms (PRQ#) PO PO PO PO PO PO 0 PO PO PO PO ~ PO O Pull up through.k ohms (PRQH#) Pull down through 0K ohms (unused) Pull down through 0K ohms (unused) Pull Up to.vsy through.k ohms (SO_PM) Not mplemented Not mplemented SM_LRT (multifuntion pin) XTSM# with Pull up 0K ohms to _S Pull down through 0K ohms (unused) Not mplemented NT# (multifunction pin) PO PO * O O NT# (multifuntion pin) No onnected PO PO 0 O O No onnected No onnected PO PO PO PO PO PO PO PO PO ~ O O O /O /O /O /O /O O No onnected No onnected Pull Up to.v through.k ohms (OS protect) No onnected No onnected Not mplemented No onnected No onnected Not mplemented PO /O No onnected PO /O No onnected PO /O Primary T/00 detection (P_T) PO /O Secondary T/00 detection (S_T) PO /O No onnected PO /O No onnected PO /O No onnected PO /O No onnected PO 0 /O No onnected PO /O No onnected PO /O No onnected PO /O No onnected PO ~ /O Not mplemented * PO will toggle at Hz frequency. FWH PO Pin Type Function P 0 P P P P P onfig. V H NT Pin SL P Slot P Slot P Slot P LN NT# NT# NT# NT# NT# NT# NT# NT# NT# NT# NT# NT# NT# NTF# Pull down through.k ohms (unused) Pull down through.k ohms (unused) P customer defined P customer defined Pull down through.k ohms (unused) LOK PLK0 PLK PLK LN_PLK LK N PN OUT 0 (P/FS) (P) (P) (P) *H reserved P address line for the P-to-S ridge's SL input. MM onfig. V RSS LOK MM LK0/LK0# LK/LK# LK/LK# MM 0000 LK/LK# LK/LK# LK/LK# MS MRO-STR NT'L O.,LT. eneral SP 00 MS- ate: Monday, May, 00 Sheet of

5 P X_OPPR LOK NRTOR LOK *Trace < 0." Shut Source Termination Resistors Pull-own apacitors filtering from 0K~M * Put copper under lock en. connect to every pin * 0 mils Trace on Layer with copper around it put close to every power pin * Trace Width mils. * Same roup spacing mils * ifferent roup spacing 0mils * ifferentical mode spacing mils on itself P P F SKTO# F R0 R 0 R X_OPPR _00 _00 X_.u-00 K K R u-00 VV,,,, SMLK_SO,,,, SMT_SO Q 0 V U PU_V PU_ MRF_V 0 PU0 PU0# PU PU# PULK RN PULK# MRF_ V_V V_0 0 V_ V_ SL_ V_ V_/SL_# R FS FS/P0 FS P_V FS/P SL_ SL_#/P FS RN P_ P_V P_ PULK0 PULK0# PULK PULK# FS/P P P P P P P 0 PULK PULK# MHLK MHLK# MH_ H_ PLK SO_ PLK PLK0 PLK PLK FWH_PLK SO_PLK H_PLK _V FS0 R H_ 0.0u FS0/MHz FS R OT_LK H_ FS/_MHz OT_LK _ RF_V MUL0 R H_ MUL0/RF0 H_ 0.0u MUL R00 X_ UO_ MUL/RF UO_ RF_ X p OR_V X 0.0u X M-pf-HS- X p OR_ X SMLK_SO R _% ref =.m SMT_SO SLK RF ST 0 RST# PWR_N# R0 K V VTT_# PWR_N# R Y X_K RN R R R0 R Q._%._%._%._% PULK PULK# MHLK MHLK# MH_ H_ PLK SO_ PLK PLK0 PLK PLK FWH_PLK SO_PLK H_PLK PULK PULK# MHLK MHLK# Trace less 0.".ohm for 0ohm M/ impedance LOK STRPPN RSSTORS FS0 V OT_LK SL_ FS FS FS SL_ MUL0 MUL FS FS FS FS FS0 FS (MHz) 0 SMLK_SO SMT_SO R R R R R0 R R._%._%._%._% 0K R.K R.K RN R 0K 0K 0K K R.K R.K V V R00 K V 00 MHz MHz SL0 MUL0=0 MUL= PULK PULK# MHLK MHLK# PLK H_ MH_ PLK PLK0 PLK PLK FWH_PLK SO_PLK H_PLK H_ SO_ H_ OT_LK p 0p 0p 0 N0 p N p N p p p p 0p 0p oh=*ref Voh=0.V used only for M issue Trace less 0." PRMRY LOK YJ0-- H_RST# H_RST# R P P[0..] P P P P[..] P P P 0 P0 P P P P P P P0 P P_RQ P_OW# P_OR# P_ORY P_K# 0 RQ P_ P_T P_0 P_S# P_ P_S# P_L 0 R.K p R 0K R K T00 ONNTORS SONRY LOK * Trace Width : mils * Trace Spacing : mils * Length(longest)-Length(shortest)<0." * Trace Length less than " YJ0-W- S[0..] H_RST# R S S S S S[..] S S0 S 0 S S S S S S S S0 S S_RQ S_OW# S_OR# S_ORY S_K# 0 RQ S_ S_T S_0 S_S# S_ S_S# S_L 0 R.K p R0 0K R K MS MRO-STR NT'L O.,LT. lock en & T00 onnectors 00 MS- ate: Monday, May, 00 Sheet of

6 PU SNL LOK PU TL RFRN VOLT LOK H#[..] V[..0], H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# V V V V V0 P U Y W V U T W R V T U P U T R P P R T N N N M N M M L M L K L K K TLRF /*Vccp R._% HNV#[..0] FRR# STPLK# HNT# HSY# HRY# HTRY# HS# HLOK# HNR# HT# HTM# HPR# HFR# Trace 0 mils width 0 mils space, Max " PU_TMP TRMTRP# SKTO# PROHOT# NN# HSM# 0M# SLP#, SL0 PU_ PURST# H#[..0] HNV#0 HNV# HNV# HNV# HNT# TP_T TP_TO TP_TMS TP_TRST# TP_TK PROHOT# PU_ PURST# H# H# H# H#0 H# H# H# H# H# H# P V PM# PM# PM# PM# HRQ# HRQ# HRQ# HRQ# HRQ#0 HRS# HRS# HRS#0 HR#0 * Short trace with in "~" very pin put one 0pF cap near it. Trace Width mils, Space 0mils. Keep the voltage divider within." of the TRF pin. PU STRPPN RSSTORS LL OMPONNTS LOS TO PU TP_T TP_TRST# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 V Y W H H J F F F Y Y Y W Y W V 0# # # # RR# MRR# FRR# STPLK# NT# NT# RSP# SY# RY# TRY# S# LOK# NR# HT# HTM# PR# FR# T TO TMS TRST# TK THRM THRM THRMTRP# /SKTO# PROHOT# NN# SM# 0M# SLP# RSRV0 RSRV RSRV RSRV F RSRV F RSRV RSRV SL0 SL PWROO RST# # # # 0# # # # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # R# _SNS _SNS TP_LK TP_LK0 V# V# V# V# V0# F0 F Y H J J K J TSTH R TSTH Y R0 TSTH0 W R TSTH U R TSTH TSTH 0 TSTH TSTH TSTH 0 TSTH TSTH R TSTH TSTH0 F F F F V H P L L K K J R L W P J F W R K LNT/NM LNT0/NTR R R TLRF._%._% P P PM# PM# PM# PM# PROHOT# PU_ HR#0 PURST# HNT# TP_TO TP_TMS TP_TK 0p R R R R R R 0 R u-00 R 00_% P P P # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# # # # # # # # # # 0# TLRF TLRF TLRF TLRF0 PM# PM# PM# PM# PM# PM0# RQ# RQ# RQ# RQ# RQ0# LK# LK0# RS# RS# RS0# P# P0# R0# OMP OMP0 P# P# P# P0# ST# ST0# STP# STP# STP# STP0# STN# STN# STN# STN0#._%._%._%._% K PULK# PULK HR#0 HST# HST#0 HSTP# HSTP# HSTP# HSTP#0 HSTN# HSTN# HSTN# HSTN#0 NM NTR HRQ#[0..] HRS#[..0] R X_ R0 00 R 0 R R 0 R 0 R V U V U U U T T T T R R P R N N M N M P N M H K J L M H L F F F H J H SOKT MS MRO-STR NT'L O.,LT. mp- NTL PU SOKT Part 00 MS- ate: Monday, May, 00 Sheet of

7 PL PS WTHN PU VTY PU VOLT LOK PU OUPLN PTORS MS Place these caps on south side of processor Trace Width mils, Space 0mils. Keep the uf cap within 0." of the PU pin. Place pcs 0 size cap north side of processor Within PU avity Solder Side MS- 00 mp- NTL PU Part MRO-STR NT'L O.,LT. Monday, May, 00 ate: Sheet of P P P P P P P 0u-0 0u-0 0u-0 0u-0 0 u-0 0u-0 u-0 0 u-0 0u-0 U SOKT F F F F F F F F F F F F F F F F F0 F F F F F0 F F F F F0 F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N R R R R P P P P N N V V U U U U T T T T Y Y Y Y W W W W V V F -OPLL -V -VPR u-0 0 u-0 L.uH/00M L.uH/00M 0u-00 0u-00 0u-00 0u-00 0u-00 0u-00 0u-00 0u-00 0u-00 0u-00 u-00 0u-00 0u-00 u u-00 u-00 0u-00 0u-0 0u u-00 0u-00 0u-0 _V

8 MH RFRN LOK Place 0.0uF ap. as lose as possible to MH< 0." MS * Length must be matched within /-0."of the Strobe Signals Trace 0 mils & mils space < 0." Trace width mils & 0mils space Trace 0 mils & mils space < 0.", Trace width mils & 0mils space Place ap. as lose as possible to MH Keep the voltage divider within " of the MH pin. Place <0." =0m =m =00m =0m MS- 00 rookdale- MH- (HOST & H & V) MRO-STR NT'L O.,LT. Monday, May, 00 ate: Sheet of H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# HU_MRF H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H# H# H#0 HNV#0 HNV# HNV# HNV# HRS#0 HRS# HRS# HRQ#0 HRQ# HRQ# HRQ# HRQ# HL HL HL HL HL0 HL HSWN H_SWN HL0 HL HL HL HL _FS _FS Q_SM _SM _SM _PLL Q_SM HU_MRF HVRF _PLL HSWN HVRF H_SWN _P _P P _P _P MM_STR _P MM_STR _P P _P P P L 0.uH_00 R._% R._% R._% R0 _% L uh-00 L 0.uH-00 0 R. % R _% R 0 % u-0.u u R0 0 % 0.0u u p 0.0u L 0uH_00 R0 0K R 00_% R 00_% R 00_% T0 00u_V R0 0u R0 0K POWR Other U rookdale_mh K L L P R R W W0 U W F0 H0 J F H J H J H K J L M J L U K0 J L U M U M J J L P U H J K L M0 H J K L H J K L U J L U M J K U H K P0 J L P L R T0 T U J Y Y W Y Y Y W H J T T U U U U H J F0 H0 F W W V U U V M0 T0 Y0 H H0 H H F V P K K _P _P _P _P _P _P _P _P _P _P _P _P _P _H _H _H _H SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM SM VTT_P VTT_P VTT_P VTT_P VTT_P _PO _PLL _FS _SM _SM Q_SM Q_SM Q_SM SM PSSL RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV N N N N N N N N N N N N VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS _P HOST HU LNK V U rookdale_mh W 0 V Y Y Y F F F H T T M U U N F0 T0 R R N R L L P J K K M0 M L K H J F F H F H 0 0 H N 0 L J F Y0 H V0 J K0 J U V W W N H0 H 0 P0 V F F H F P M T R U P Y T M K K K0 K H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# S# NR# PR# RQ0# SY# FR# H_ST0# H_ST# PURST# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H_STN0# H_STN# H_STN# H_STN# H_STP0# H_STP# H_STP# H_STP# H0 H H H H H H_RF HL_ROMP HY_SWN HX_SWN HTRY# RSTN# HLKP HLKN LKN RY# HRQ0# HRQ# HRQ# HRQ# HRQ# NV_0# NV_# NV_# NV_# H_VRF0 H_VRF H_VRF H_VRF H_VRF HY_ROMP HX_ROMP H H H H H0 H_STS H_STF LU LU# RN RN# R R# _T _LK HSYN VSYN RFLK RFST HT# HTM# HLOK# RS0# RS# RS# H_SWN PWROK VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS VTTFS R H#[..] H#[..0] HR#0 HNR# HPR# PURST# PRST# MH_ HT# HTM# HNV#[..0] MHLK MHLK# HSTN#0 HST#0 HST# HSTP#0 HSTN# HSTP# HSTN# HSTP# HSTN# HSTP# HTRY# HFR# HSY# HRY# HRS#[..0] HRQ#[..0] HS# HLOK# HL[..0] HL_ST HL_ST# RT_ RT_# RT_ RT_# RT_R RT_R# V_VSYN V_HSYN V VL HL[0..] SL0 PWR_ OT_LK

9 Trace lengh must as short as possible for SRVN Trace width mil with mil space for SM_VRF. [..0] _#[..0] R_VRF R MQ0 N MQ P MQ T MQ P MQ N MQ P MQ R MQ T MQ T MQ R MQ0 T MQ R0 MQ T MQ P MQ T MQ P MQ P0 MQ T MQ T MQ T MQ0 T0 MQ R MQ R MQ P MQ T MQ P MQ T MQ T MQ R MQ T MQ0 P MQ R0 MQ R MQ P MQ P MQ T MQ T MQ T MQ T MQ R MQ0 P MQ T MQ R0 MQ P0 MQ T MQ R MQ T0 MQ T MQ R MQ T MQ0 R MQ P MQ P MQ T MQ P MQ T MQ N MQ M MQ K MQ J MQ0 P MQ M MQ K MQ K _Soder K L M 0 V V W W U U U V T T 0 T R R R T P P K K J 0 M L L H K J J J H 0 K _#0 R _# N _# M _# H U SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SRVN_OUT# SRVN_N# SM_VRF _ /0# _/# _/# _/# H0 H H H H H SM SM SM SM SM SM R P _P _P _P _P _P _P _P _P K0 K K K P0 V0 0 0 MM_STR L RM0 SM0 N RM SM P RM SM K0 RM SM L RM SM L RM SM P RM SM P RM SM N RM SM K RM SM K RM0 SM0 L RM SM N RM SM P SM N SM N SM K SM R MSQS0 SQS0 T MSQS SQS T MSQS SQS T MSQS SQS R MSQS SQS T MSQS SQS T MSQS SQS L MSQS SQS P MSM0 SM0 R MSM SM P MSM SM R MSM SM T MSM SM P MSM SM R MSM SM L MSM SM P MSK0 SK0 N MSK SK K MSK SK L MSK SK L SS0# P SS# K0 SS# N SS# L SML_K0 K SMLK_0# N SMLK_ P SMLK_# M SMLK_ L SMLK_# P SMLK_ N SMLK_# P SMLK_ N SMLK_# P SMLK_ N SMLK_# N S_0 P S_ K SRS# N SS# P SW# F0 SMX SMX_ROMP0 J SMY SMY_ROMP M _FRM# N _RY# N _TRY# N _VSL# P _STOP# P _PR _RQ# _NT# S0 S0 S S S S S S S S S S F S S F S S F S_ST S_ST# ST0 ST0 ST ST ST ST V _ST0 U _ST0# M _ST L _ST# H PP# RF# WF# W P_VRF L R 0._% P_ROMP rookdale_mh Place < 0." RM[..0],, RM RM, RM, RM, MSK[..0],, MSS0# MSS#, MSS#, MSS#, LK0 LK0# LK LK# LK LK# LK Trace width mil LK# with 0 mil space. LK LK# Place F <" to MH LK LK# MM_STR MSS0 MSS MRS#, MS#, R R0 MW#, FRM# R R RY# TRY# VSL# STOP# PR RQ# NT# S[..0] S_ST S_ST# ST[..0] _ST0 _ST#0 _ST _ST# PP# RF# WF# PRF _P, RM[..0] R SRL RSSTORS RM RN 0 MQ RM MQ RM MQ RM0 MQ0 RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM0 MQ0 RM MQ RM MQ RM RN0 0 MQ RM MQ RM MQ RM0 MQ0 RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM MQ RM0 MQ0 RM MQ RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM MQ RM MQ RM0 MQ0 RM RN0 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM MQ RM MQ RM MQ RM RN 0 MQ RM0 MQ0 RM MQ RM MQ RM RN 0 MQ RM MQ RM MQ RM0 MQ0 RM RN 0 MQ RM MQ RM MQ RM MQ MSM0 R0 0 SM0 MSM R0 0 SM MSM R 0 SM MSM R 0 SM MSM R 0 SM MSM R 0 SM MSM R 0 SM MSM R 0 SM MSQS0 R0 0 SQS0 MSQS R 0 SQS MSQS R 0 SQS MSQS R 0 SQS MSQS R 0 SQS MSQS R 0 SQS MSQS R 0 SQS MSQS R 0 SQS SM0 SM SM SM SM SM SM SM SQS[..0], MS MRO-STR NT'L O.,LT. rookdale- MH- (R & P) 00 MS- Monday, May, 00 ate: Sheet of

10 MH OUPLN PTOR U V Y L R U F H K M P T V Y F H M N R R M J N R F H M T Y F M U0 V0 Y0 0 M0 J W J L N R U F V Y J R F H U J V H0 M N R U Y J R R M0 R U F J L N U R W J R F0 T J L N R U W M M N R U L N R U W F M J N U J H T J U J N R R U J J R F K M J J R F L R U F M J N U N R R U N rookdale_mh _P Pin Pin Pin J Pin N Pin U Place decoupling cap close to MH P nterface < 0." _P Place decoupling cap close to MH ore Logic nterface < 0." _P 0.0u 0 T 000u 0.0u Place ulk cap for ore Logic, P & Hub Link nterface MM_STR T 00u T 000u T 00u T 000u Place ulk cap between MH & MM slot _P Place decoupling cap close to MH Hub-Link nterface< 0." P Place decoupling cap close to MH PU nterface < 0mil in the Vtt corridor P X_ X_ X_ 0u-0 Pin Pin 0u-0 Place decoupling cap close to MH nterface< 0." MM_STR _P 0 0.0u Pin L Pin U Pin U Pin U Pin U Pin U Pin U Pin U Pin Pin Place decoupling cap close to MH Memory nterface < 0.", with mil trach width MS MRO-STR NT'L O.,LT. roodale MH() 00 MS- ate: Monday, May, 00 Sheet 0 of

11 H P / HU LNK / PU / LN / NTRRUPT SNLS SM# R 00p HSM# H STRPPN RSSTORS _P _S _S _OUT R K [..0] _#[..0] VSL# FRM# RY# TRY# STOP# PR PLOK# SRR# PRR#, PM# H_PLK PRST# LN_RST# HRSMRST# _S _N _OUT _SHLK _#0 _# _# _# PRQ# R R 0 R _OUT H J H K J H J K L L H L F F N N N M P P R P J K M N M F L F F M K L W P U Y /0# /# /# /# VSL# FRM# RY# TRY# STOP# PR PLOK# SRR# PRR# PM# K0 K K K P0 T U V PO0/RQ# PO/NT# PLK PRST# LN_RST# _S _N _OUT _SHLK H H J J K M0 P P U V0 V V 0 F R T U SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ F0 F F F F K V V V SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ SUS_ 0 0 U 0M# PUSLP# FRR# NN# NT# NTR NM SM# STPLK# RN# 0T N THRMTRP# U W V V W V U Y U W0 L H0 L0 H M H M H P H R H T0 H R0 H P H L H N H0 K H P H_ST N0 HL_ST# R HLOMP R H_SWN M HRF PRQ# PRQ# PRQ# PRQ# RQ RQ PLK P0 P SRRQ RQ0# RQ# RQ# RQ# RQ# PO/RQ#/RQ# NT0# NT# NT# NT# NT# PO/NT#/NT# LN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX J H K0 J NT-0 SM# K_RST# 0T# TRMTRP# HL0 HL HL HL HL HL HL HL HL HL HL0 R R0._% H_SWN HU_RF PLK P_0 P_ SRRQ PRQ#0 PRQ# PRQ# PRQ# PRQ# PRQ# PNT#0 PNT# PNT# PNT# PNT# FRR# R 0 This resistor less than 0." from H use mils trace HL_ST HL_ST# _P NT#, NT#, NT# NT# RQ RQ SRRQ PRQ#0 PRQ# PRQ# PRQ# PRQ# PNT#0 PNT# PNT# PNT# PNT# 0M# SLP# FRR# NN# FNT# HNT# NTR NM STPLK# K_RST# 0T# TRMTRP# HL[0..0] LN_LK LN_SYN, LN_RX0 LN_RX LN_RX LN_TX0, LN_TX, LN_TX, Reserved pull-down resistor for H reserved function straps. H PULL-UP/OWN RSSTORS FRR# R TRMTRP# R SRRQ R.K K_RST# 0T# R R.K.K PRQ# R.K PRQ# R.K P_0 P_ PLK H RFRN VOLT H_SWN HU_RF 0.0u 0.0u R R 0K 0K 0 X_ X P Place ap. as lose as possible to H < 0." Trace width use mils and 0mils space P R _% R 00_% R 00_% H OUPLN PTORS Place one close to H <00 mil Pin 0 Pin Pin H 0 0 Pin T Pin 0 0 Pin 0 0 Pin K Pin _P FOR ore Logic Pin Pin _P 0 0.0u FOR PLL Pin T Pin N _P X_ FOR Hub nterface Pin Pin _S 00 0 MS MRO-STR NT'L O.,LT. H P & H & LN 00 MS- ate: Monday, May, 00 Sheet of

12 THRM#, SLP_S# SLP_S# PWR_ PU_ VRM_ PWRTN# RN# HRSMRST# SUSLK _N# SMLRT#,, SMT SMLK H_ H_ H RST#, _SYN _LK, _SOUT _SN0 _SN, _SN SPKR FWH_WP# LN_SL, L0/FWH0, L/FWH,, L/FWH L/FWH, LFRM#/FWH LRQ# Place < 0." 0 O# 0 USP0 USP0- USP USP- USP USP- USP USP- USP USP- USP USP- SMS Place ap close to Pin Note: R may be change. % for 0 version H OUPLN PTOR _S O# X_ Pin Pin THRM# PWR_ RN# NTRUR# RTRST# VS _SOUT XTSM# P FWH_WP# PO LN_SL 0 Pin R HRSMRST# SYS_RST# Y TLOW# _N# R SMLRT# W W Y RTX RTX V0 T J F H V W T Y0 J W W T R T U T U U R. % K V Y THRM# Y SLP_S# SLP_S# SLP_S# Y PWROK V PUPWR VRMPWR Y PWRTN# R# RSMRST# SUSSTT# SUSLK SYS_RST# TLOW#/TP0 P Pin 0 _S p _S P RT_ VRF _P _P _S V VRF VRF PUSY#/PO PO/SMLRT# SMLNK0 SMLNK NTRUR# RTRST# VS SMT SMLK RTX RTX N LK LK LK _RST# _SYN _TLK _SOUT _SN0 _SN _SN SPKR PO PO _STT#/PO PUPRF#/PO SSMUXSL/PO PO PO L0/FWH0 L/FWH L/FWH L/FWH LFRM#/FWH LRQ0# LRQ# 0 0 USP0 USP0- USP USP- USP USP- USP USP- USP USP- USP USP- USRS USRS# O0# O# O# O# O# O# VRF_SUS PLL RT Place one close to H <00 mil VRF 0 Pin L M P T _H _H _H _H F F LN_/SUS_ LN_/SUS_ F LN_/SUS_ LN_/SUS_ F H J K K K K K L0 L L L L L M M M P U VPU_O VPU_O0 VPU_O Y Y W W W V V V U0 T T T R R M M0 M N0 N N N N N N N N P P P0 P P R U PS# SS# PS# SS# P0 P P S0 S S PRQ SRQ PK# SK# POR# SOR# POW# SOW# PORY SORY PO/PRQ# PO/PRQF# PO/PRQ# PO/PRQH# PO PO STP_P#/PO SLP_S#/PO STP_PU#/PO0 LKRUN#/PO PO R V Y W W V NT-0 Y W 0 0 Y Y W P0 P0 P P Y0 P P 0 P P P P P P Y P P P P P P Y P P P0 P0 W P P 0 P P W0 P P W P P Y P P W S0 S0 S S W S S S S W S S S S W S S S S Y S S S S S0 S0 Y S S S S Y S S S S Y S S PO PO PO PO PO PO PO PO PO0 PO PO PO J0 F0 0 F H0 F H H F P SO_PM# PO PO P_S# S_S# P_S# S_S# P_0 P_ P_ S_0 S_ S_ P_RQ S_RQ P_K# S_K# P_OR# S_OR# P_OW# S_OW# P_ORY S_ORY P[0..] S[0..] NT# NTF# NT# NTH# SO_PM# VT NTRUR# P_ORY S_ORY THRM# FWH_WP# P _S _N# PWR_ HRSMRST# R P R0 K R K R PROHOT LOK R R K T *Put a Plane under X'TL *Please put this block close H H STRPPN RSSTORS _SOUT HH FS Safe mode LOW FS uto mode * R.K R.K THRM# MS SPKR HH LOW RT LOK JT lear MOS - Normal - lear MOS * No Reboot mode Reboot mode * H PULL-UP/OWN RSSTORS 0K R.K R0.K R R R0 PROHOT# N 0K K X_K 0K T-S-SOT X_.K Q p VT R M R X_.M _SOUT SPKR RT_ RT_ R 0K p R0 R SMT SMLK TLOW# SO_PM# SMLRT# RN# LN_SL R.K XTSM# P PO PO PO FP_RST# p R 0M R RTRST# R0.K R.K SYSTM RST MRO-STR NT'L O.,LT. H S/RT/'/PO/LP/US/ 00 MS- VS RTX RTX _S R _S.K SYS_RST# ate: Monday, May, 00 Sheet of X 0M JT YJ0 K-.pf-S-0- -0PPM X_.K X_K R.K R.K R.K R.K R R R R0 R R 0 0K 0K 0K 0K 0K p

13 LP SUPR /O WHF THRML RSSTOR LOK _S PRST# SO_PLK SRRQ LRQ#, LFRM#/FWH,, L/FWH L0/FWH0, L/FWH, L/FWH V[0..] PU_TRL PU_FN SYS_TRL SYS_FN PWR_FN PU_TMP THRM# SO_PM#,,,,,,,, SMT_SO SMLK_SO PWRTN# PWRTN PS_ON# SLP_S# SO_ VT P V V V V V0 JYS_X JYS_X JYS_P0 JYS_P JYS_X0 JYS_X JYS_P JYS_P M_OUT M_N TMP_VRF PU_TMP SYS_TMP -VN -VN VN VTN_ P HSSS U LRST# LLK SRRQ LRQ# LFRM# L0 L L L PX/P/P PY/P PS/P/P0 PS/P PX/P/P PY/P/P PS/P/P PS/P MSO/RQN0 MS/P0 VRF VTN VTN VTN -VN -VN VN.VN VOR VOR V V V V V0 FNPWM FNO FNPWM FNO FNO 0 OVT# P SOPN# PM# WTO/P S/P SL/P PSOUT# PSN 0 SUSL/P PL/P PWRTL#/P SUSN/P0 LKN VS VT RVN0 RVN NX# MO# S# S# MO# R# STP# 0 WRT# W# TRK0# WP# RT# H# SKH# P0 P P P P P P P SLT P USY K# SLN# NT# RR# F# ST# 0 RRX/P RRX/P RTX/P SUSLKN # 0 SR# SN RTS# SOUT TS# TR# R# # SR# SN RTS# SOUT TS# TR# R# KRST KT KLK MST MSLK KLOK# RSMRST#/P PWROK/P 0 0 R RN RN RN RN RRX RTX LP_0 LP_ LP_ LP_ LP_ LP_ LP_ LP_ RRX RTX SUSLK # SR# SN RTS# SOUT TS# TR# R# # SR# SN RTS# SOUT TS# TR# R# 0T# K_RST# KT KLK MST MSLK RVN0 RVN NX# MOT_# RV_# RV_# MOT_# R# STP# WT_T# WT_N# TRK0# F_WP# RT# H# SKH# LP_[0..] LP_SLT LP_P LP_USY LP_K# LP_SLN# LP_NT# LP_RR# LP_F# LP_ST# V -V -V VTN_ TMP_VRF R0 0KST SYS_TMP RT R-T-00 NOT: LOT LOS STTUS PNL R KST R KST R 0KST hasiss ntrusion Header JS x VT P 0P R M F0 R 0KST HSSS X_OPPR S/00 R KST VN -VN -VN R KST TMP_VRF P R TMP_VRF ntel Front R Header RTX SPKR LOK R 0K R.K 0KST Q N0S PU_TMP R ONX LRM RRX WHF V_ JYS_P0 JYS_X0 JYS_X JYS_P V_ R.K R.K R K R K P M_OUT M_N 0 UO YNF P M/M ONNTOR R0.K R.K R.K R.K 00P JYS_P JYS_X M_OUT JYS_X JYS_P M_N 00P JYS_X0 JYS_X JYS_X JYS_X JYS_P JYS_P0 JYS_P JYS_P JYS_X0 JYS_X JYS_X JYS_X JYS_P JYS_P0 JYS_P JYS_P RN PR-.K N P-0P N P-0P RN PR-M LP /O OUPLN PTORS 0 0 MS SUPR /O STRPPN RSSTOR SOUT SOUT RTS# TR# R.K R.K R L: isable K L: MHZ L: F= L: PNP efault LP O & M PORT MS- SOUT SOUT X_.K RTS# H: nable K H: MHZ H: F= H: PNP no efault MRO-STR NT'L O.,LT. 00 ate: Monday, May, 00 Sheet of

14 SYSTM MMORY SLV RSS = R MM SOKT Place 0p ap. near the MM SLV RSS = 0000 R MM SOKT Place 0p ap. near the MM Keep the voltage divider within " of MM. Trace width mil with mil space. MS Place high freq bypass cap between the MMS. MS- 00 R MM& MRO-STR NT'L O.,LT. Monday, May, 00 ate: Sheet of SMT_SO MW# MS# MRS# SMLK_SO MSS0 MSS LK# LK LK LK LK# LK# MSK MSK RM RM RM0 RM0 RM RM RM RM RM SQS SQS SQS SQS SQS SQS SQS0 SQS RM RM0 RM RM RM RM RM RM RM RM RM RM RM RM RM RM RM0 RM RM RM0 RM RM RM RM RM RM RM RM RM RM RM RM RM RM RM0 RM RM RM RM RM RM RM RM0 RM RM RM RM0 RM RM RM RM RM RM RM RM RM RM RM RM0 RM RM RM RM RM MRS# MSK RM RM MSK0 LK# SQS RM0 RM RM RM RM RM RM RM0 SQS RM RM RM RM0 RM RM RM RM RM RM RM RM RM0 MW# RM RM SMLK_SO RM RM RM RM RM LK# SQS0 RM RM RM RM LK0 RM RM RM RM RM RM RM0 RM LK RM SQS RM RM RM0 RM RM MS# SQS RM RM RM LK RM RM0 SMT_SO RM RM SQS SQS RM RM RM RM RM RM RM0 RM RM RM RM RM RM LK0# MSS MSS0 SQS RM RM RM RM RM RM0 RM RM RM SM SM SM SM SM0 SM SM SM SM SM0 SM SM SM SM SM SM RM RM RM RM R_VRF MM_STR MM_STR MM_STR R_VRF MM_STR 0 0P 0P N-00 R Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q S0# S# S# S# QS0 QS QS QS QS QS QS QS QS FTN 0 SL S S0 S S 0 0_P 0 K0(U) K0#(U) K(K0) K#(K0#) K(U) K#(U) N N(RST#) K0 K S# RS# M0 M M M M M M M M WP(N) W# VRF N N N V0 V V V V V V V V VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ V VSP N-00 R Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q S0# S# S# S# QS0 QS QS QS QS QS QS QS QS FTN 0 SL S S0 S S 0 0_P 0 K0(U) K0#(U) K(K0) K#(K0#) K(U) K#(U) N N(RST#) K0 K S# RS# M0 M M M M M M M M WP(N) W# VRF N N N V0 V V V V V V V V VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ V VSP R 0 % R0 0 % SQS[..0], RM[..0], MSS0, MSS, LK LK0 LK0# LK LK# LK# MSK, MSK0, MS#, MRS#, LK# LK# LK LK# LK LK MSK, MSK, MSS0#, MSS#, MSS#, MSS#, MW#, RM[..0], SM0 SM SM SM SM SM SM SM RM, RM, RM, RM, SMLK_SO,,,, SMT_SO,,,,

15 R ecouping aps, SM, SM, SQS, SQS, RM, RM, RM MSS0, RM, RM, RM, RM, RM, MSK[0..] MSS, RM0, RM0, RM, RM, RM, RM, MSS#, MSS#, MSS0#, MSS#, RM, RM, RM, RM,,, R TRMNTORS MS# MW# MRS# SM SM SQS SQS RM RM RM MSS0 RM RM RM RM RM MSK0 MSK MSK MSK MSS RM0 RM0 RM RM RM RM MSS# MSS# MSS0# MSS# RM RM RM RM MS# MW# MRS# R R R R R R R R R R0 R R R RN RN RN RN0 RN0 R R R0 VTT_R, RM, RM, RM, RM0, RM, RM, SQS0, SM0, RM, RM, RM, RM, RM, RM0, RM, RM, SM, SQS, RM, RM, RM, RM, RM, RM0, RM, RM, SM, SQS, RM, RM, RM, SQS, RM, RM, RM, RM, RM, RM0, RM, RM, RM, RM, RM, RM, RM, RM, SM, RM, RM, RM0, RM, RM, RM, RM, RM, RM, RM, RM, RM, RM, RM0, RM, RM0, RM, RM, SQS, SM, SQS, SM, RM, RM, RM, RM, RM, RM RM RM RM RM0 RM RM SQS0 SM0 RM RM RM RM RM RM0 RM RM SM SQS RM RM RM RM RM RM0 RM RM SM SQS RM RM RM SQS RM RM RM RM RM RM0 RM RM RM RM RM RM RM RM SM RM RM RM0 RM RM RM RM RM RM RM RM RM RM RM0 RM RM0 RM RM SQS SM SQS SM RM RM RM RM RM RM RN RN RN RN0 RN RN RN R R R RN RN RN RN RN RN RN RN RN RN RN VTT_R VTT_R Total 0 signal, need pcs decoupling. Place for VTT_R island VTT_R 0 X_ X_ X_ X_ X_ Place at the end of the VTT_R island T 000u VTT_R X_ X_ X_ X_ X_ X_ X_ X_ VTT_R 0u-00 0u-00 0u-00 VTT_R ottom Vtt enter Vtt Top Vtt X_ X_ X_ X_ 0 X_ VTT_R 0 X_ X_ 0 X_ X_ X_ 0 0 X_ MS MRO-STR NT'L O.,LT. R Terminator Resistor 00 MS- ate: Monday, May, 00 Sheet of

16 P SNL RFRN RUT S_ST _ST RY# VSL# PRR# SRR# _ST0 PRF P.V X/X SLOT(P VR:.0 OMPLY) _S _P = 0mils trace / mils space P NT# NT# S_ST# _ST# _P FRM# TRY# STOP# PR _ST#0 PRST# V 00p -OVRNT V V -TYPT V RSRV US US- NT# NT# NT# -NT -NT PRST# NT# PLK RQ# NT# PRST# RQ# NT# ST0 ST ST RF# PP# RF# PP# WF# WF# S0 S S S_ST S S _ST _# RY# VSL# _# 0 _ST0 PRF X_ LK -RQ.V ST0 ST -RF RSRV S0.V S S_ST S S RSV/KY /KY UXV/KY.V/KY.V _ST VQ /- VQ -RY UXV/KY /KY RSV/KY.V/KY -VSL VQ -PRR -SRR /- VQ 0 VQ _ST0 VQ VRF_ P--N_.V -RST -NT.V ST RSRV -PP -WF S.V S -S_ST S S RSV/KY /KY RSV/KY.V/KY 0.V -_ST /- VQ 0 VQ -FRM RSV/KY /KY RSV/KY.V/KY -TRY -STOP -PM 0 PR VQ /-0 VQ -_ST0 0 VQ 0 VRF_ S S_ST# S S 0 _ST# _# 0 FRM# TRY# STOP# PM#, PR _#0 _ST#0 0 PRR# SRR# _ST0 _ST S_ST _ST# _ST#0 S_ST# LSS 00MLS STU TR LNTH FOR /X LSS 00ML FOR X MUST FOLLOW N. Place these resistors between P slot & MH _P T 000u R.K R.K R0 R R R R R0 _P X_.K X_.K X_.K X_.K X_.K X_.K _P PRF: 0u PRF NR P SLOT P TRMNTON RSSTORS _P PR STOP# TRY# VSL# FRM# RY# RQ# NT# ST0 ST ST PP# RF# WF# P SLOT OUPLN PTORS V R K_% R K_% 0.0u _S 0.0u R R0 X_.K X_.K RN X_.K RN 0 0 PR-.K 0.0u _P _P 0 0.0u MS MRO-STR NT'L O.,LT. P SLOT 00 MS- ate: Monday, May, 00 Sheet of

17 Video onnector _P _P _P RT_R L0 0ohm/00MHz.P R._% R _%.p.p RT_.P R._% R _%.p V V V RT_R RT_R# RT_ L 0ohm/00MHz RT_#.p RT_ RT_ L 0ohm/00MHz RT_# Place clamping component & Level shift circuit near to connector VL V U VO VO VP VO X_N00S VO VN VO VO V_HSYN V_VSYN P X_OPPR V_ FS YFUS.S-P F S/00 X_ JV.P R._% R _% 0.p.p V_VSYN V_HSYN V_VSYN V_HSYN R R VL V_VSYN V_HSYN V 0 N 00p V--L--S V V R.K Q N00 T R.K R V V_VSYN R X_K U0 V X_NWZ0_S0- V_VSYN VL VL R.K Q N00 R.K R VL V_HSYN R U0 X_K V X_NWZ0_S0- V_HSYN MS MRO-STR NT'L O.,LT. V onnector 00 MS- ate: Monday, May, 00 Sheet of

18 P SLOT (P VR:. OMPLY) P SLOT (P VR:. OMPLY) SL = P SLOT (P VR:. OMPLY) SL = MSTR = PRQ MSTR = PRQ P SLOT OUPLN PTORS P PULL-UP / OWN RSSTORS NT# MSTR = PRQ0 NT# SL = NT# MS MS- 00 P SLOT && MRO-STR NT'L O.,LT. Monday, May, 00 ate: Sheet of NT# PRQ#0 NT# NT# NT# PRQ# _# _# RY# VSL# PLOK# PRR# SRR# _# 0 NT# _#0 0 PM# 0 NT# PRST# 0 STOP# PR TRY# FRM# NT# NT# PRQ# _#0 0 PM# 0 PRST# 0 STOP# PR TRY# FRM# NT# NT# NT# NT# _# _# RY# VSL# PLOK# PRR# SRR# _# 0 VSL# TRY# RY# FRM# SRR# PRR# PLOK# PRQ#0 NT# NT# NT# NT# PRQ# PRQ# NT# NTF# NT# NTH# SMLK SMT SMLK SMT STOP# NT# PRQ# PRQ# PRQ# _S _S -V V -V V _S -V V V _S -V P P-0-WH-SN TRST# V TMS T V NT# NT# V RSRV V(/O) RSRV RSRV RST# V(/O) NT# RSRV 0.V SL. 0.V FRM# TRY# STOP#.V SON SO# PR.V /#0.V 0 V(/O) RQ# V V -V TK TO V V NT# NT# PRSNT# RSRV PRSNT# RSRV LK RQ# V(/O).V /#.V /# RY#.V VSL# LOK# PRR#.V SRR#.V /# 0.V V(/O) K# V V RN0.K RN.K 00p 00 00p 0 00p 0 00p RN.K RN.K P P-0-WH-SN TRST# V TMS T V NT# NT# V RSRV V(/O) RSRV RSRV RST# V(/O) NT# RSRV 0.V SL. 0.V FRM# TRY# STOP#.V SON SO# PR.V /#0.V 0 V(/O) RQ# V V -V TK TO V V NT# NT# PRSNT# RSRV PRSNT# RSRV LK RQ# V(/O).V /#.V /# RY#.V VSL# LOK# PRR#.V SRR#.V /# 0.V V(/O) K# V V P P-0-WH-SN TRST# V TMS T V NT# NT# V RSRV V(/O) RSRV RSRV RST# V(/O) NT# RSRV 0.V SL. 0.V FRM# TRY# STOP#.V SON SO# PR.V /#0.V 0 V(/O) RQ# V V -V TK TO V V NT# NT# PRSNT# RSRV PRSNT# RSRV LK RQ# V(/O).V /#.V /# RY#.V VSL# LOK# PRR#.V SRR#.V /# 0.V V(/O) K# V V RN.K 0 R M_00 R M_0 R M_0 R 0 R M_0 R0.K R 00 R 00 R 00 _# _# RY# VSL# PRR# PLOK# SRR# _# 0 PLK PNT# 0 0 _#0 PR FRM# 0 PRST# PNT#0 STOP# PNT# PM#, PRQ#0 PRQ# NTF# NT# NT# NTH# NT# NT# NT# NT# PLK0 PLK SMLK, SMT, PLK PRQ# PNT# PRQ# TRY# PRQ#

19 Firware Hub (FWH) P Mounting Holes S_T P_T J onfig. - Normal * - onfiguration Mode PRST#, L0/FWH0, L/FWH, L/FWH F_P F_P FWH_WP# U VPP RST# FP FP FP FP0 WP# LK FP 0 (VL) 0 TL# NT# FWH RFU 0 RFU 0 FWH0 RFU FWH RFU FWH RFU FWH PL-SMT F_P FWH_PLK FWH_ NT# LFRM#/FWH, L/FWH, FWH RSSTORS F_P F_P F_P F_P F_P FWH_ R R X_K RN.K X_K S rill / 00 Pad S rill / 00 Pad S rill / 00 Pad S rill / 00 Pad S rill / 00 Pad S rill / 00 Pad OPN Recovery * efault P Fiducials FWH OUPLN PTORS FWH write protect FWH NT Signal Voltage Translation lock 0 OS_WP YJ0 FWH_WP# FWH_WP# P R 0K FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL Place ap. as lose to FWH< 0 mil OS_WP OS Update SHORT OPN Locked Unlocked * FNT# 0 Q R 0 NT# FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL FM X_FUL * LN Trace width : mils * ' Trace Spacing : 0 mils * Maxium trace length <." * qual to or up to 00 mils shorter than the LN_LK trace, _N, _SHLK LN_TX LN_RST LN_RX LN_RX0 SM_0,,,, SMLK_SO _N# _N# R 0 _SYN SOUT _SYN R0 0 _SOUT_ NR_LK R 0 _LK_ NR NR NR RSR SM_ SM_ LN_TX LN_TX LN_TX0 LN_RST LN_LK LN_RX LN_RX LN_RX0 RSV RSV RSV RSV RSV PR_ RSV RSV RSV0 RSV 0 LN_TX LN_TX LN_TX0 LN_TX LN_TX0 0 LN_RSTSYN 0 LN_LK LN_LK LN_RX LN_RX LN_RX LN_RX0 RSV US _S RSV VUL US- US_O# V V -V _S -V.VUL.V V 0 0 _OUT _SHLK SM_0 SM_SL PRMRY_N# _SYN _ST_OUT _TLK _N _S SM_ SM_ SM_S _RST# RSV _ST_N _ST_N0 0 0 _RST# _SN SN SN0_ RN _OUT, _S, RN PR_ RN 0P SM_0 SMT_SO,,,, _RST# LN_TX, LN_TX, LN_TX0, LN_SYN, LN_LK LN_RX LN_RX LN_RX0 RN0.K _SN _SN _SN0 PR&RST Q0 N0S MS SMULTON TR J X_PN* R 0 Q N0S R _S.K Q N0S R MRO-STR NT'L O.,LT. FWH & NR 00 MS- _N# _S _RST# ate: Monday, May, 00 Sheet of R J X_PN* R K.K R 0K R 0K

20 FRONT PNL US ONNTOR FOR US PORT 0, POWR RUT FOR US PORT 0,,, F 0 L ohm_00 USP S USP- S- FS F 0 _STR S F0 0.-MNSMM0-S R T R S0-.K 0P 000u X_K USP0- S0 O# USP0 O# R.K NR US ONNTOR F 0 L ohm_00 NR US ONNTOR For S Protection ntel Front US Header MS Front US Header FRONT PNL US ONNTOR FOR US PORT, JUS S S L S- S0- JUS ohm_00 S S0 S S- S0- USP- S USSWP S0 S USP F 0 0 S- N-0-P0 USSWP 0 S F 0 S- USP- M_USX- USP S L JUS ohm_00 S S R S- S- USSWP S S M_0_00 O# 0 mils F 0 0 NR US O# R 0 N-0-P0 ONNTOR F 0 For S Protection _STR O# FS.-miniSM00-S POWR RUT FOR US PORT, R.K R.K NR US ONNTOR US 0P T 000u R X_K RR PNL US ONNTOR FOR US PORT, NR US ONNTO R For S Protection USP USP- USP USP- F F F F L ohm_00 L ohm_00 S- S S- S US LN_US UP OWN USLN * US Trace width : mils * US Trace Spacing : mils * ifferential US Signlas Trace, Spacing : mils * US Power Trace must be 0mils width P X_OPPR F 0_00 X_ MS MRO-STR NT'L O.,LT. US ONNTORS 00 MS- ate: Monday, May, 00 Sheet 0 of

21 _SOUT NR_LK _LK _SN _SYN PR&RST P 0 P P R 0 R R R 0 F MONO_PHON SPF R S/00 0 0P X_OPPR XTLN XTLOUT 0 0P X_.K V MONO_PHON UXL UXR LX X RX 0 V XTL_N XTL_OUT ST_OUT T_LK ST_N V SYN RST# P_P PHON N N TST TST UXL UXR R00 X_.K R 0 TST TST VOL VOR 0 OUTR TST OUTL L R 0 V MONO M M HPOUT_R HPOUT_L MONO_OUT LNL LNR LOUTR LOUTL N N VR VR L0 U 0 FLT FLT N VRF V VR 0 0P 0P/00 0P/00 HPOUT_R HPOUT_L 0 0P VR VRF_OUT LN_ROUT LN_LOUT T LS0U/V R 0K L0 O R 0K 0P R0 R L0 L0 ST L0 Line_OUT.Vrms.Vrms HP_OUT.Vrms.Vrms ST.0Vrms.0Vrms 0P K K 0 0P P 0P P 0P U 0 0P 0P 0 0P 0P 0 0P LN_N_R LN_N_L 0 P X_P UO YNF-00- UO O RYSTL RUT XTLOUT UO_ R M X 0 P.MHZ F 0/00 F 0/00 F 0/00 UO_ 0 P XTLN UO O RULTORS R00 VRF_OUT 0P/00 X_P R.K R K M_N VR R.K R.K M_N 0 0P UO YNF-00- RX X LX UO O / UX / MOM N HRS 0P/00 0P 0P/00 R0 K R K R K R L N _N YJ0- MONO_PHON MONO_OUT UXR UXL M_N R 0P 0P 0P R 0 0P M_0 MOM N UX N MM_N YJ0- UX_N YJ0-R SPF HRS SPF JSPF X_x-K V 0 0P R X_/0 P X_OPPR VR 0 0P MS U YLT0S-0. VN VOUT J SOT R 00RST R 00RST MRO-STR NT'L O.,LT. O 00 MS- 0U/V/S VR 0 0P ate: Monday, May, 00 Sheet of

22 SPKR OUT RUT SPKR OUT JK LN_ROUT R00 0 LOUTR LS0U/V- R0 R HPOUT_R SPKR_R SPKR_NXT_R SPKR_NXT_L UO 0 0 YNF-00- R HPOUT_L 0P 0P LN_LOUT R00 0 LOUTL LS0U/V- R SPKR_L FOR ntel NTRNL HR VR M_N VR R0.K M_N R.K R 0 M SPKR_R SPKR_L JUO 0 ONX 0P SPKR_NXT_R SPKR_NXT_L SPKR_L SPKR_R M 0P 0P P SPKR_R SPKR_L R R SPKR_NXT_R SPKR_NXT_L MS MRO-STR NT'L O.,LT. UO MPLFR 00 MS- ate: Monday, May, 00 Sheet of

23 TR# RTS# SOUT RX R TS SR U 0 RN RN RN RN RN N N N - V ROUT ROUT ROUT ROUT ROUT OUT OUT OUT 0 V- N-S-LL -V -V V 0 SRL PORT V -V TR RTS TX 0 N-S-LL 0 # SN R# TS# SR# V RX R TR RTS TS TX SR RX TX TR V 0 F P 0 LPT X_ N 0p N 0p SR RTS TS R LPT--K- _00 X_OPPR TR# RTS# SOUT RX R TS SR U 0 RN RN RN RN RN N N N - V ROUT ROUT ROUT ROUT ROUT OUT OUT OUT 0 V- V -V SRL PORT TR RTS TX # SN R# TS# SR# TX RTS R TR R RX SR TX TS RTS OM HR OM x-:-wh N 0p N 0p RX TR SR TS X_ PRLLL PORT US PS KYOR & MOUS ONNTOR LP_ LP_ LP_ LP_0 LP_[0..] LP_SLT LP_P LP_USY LP_K# LP_SLN# LP_NT# LP_RR# LP_F# LP_ST# LP_ LP_ LP_ LP_0 LP_ LP_ LP_ LP_ LP_SLT LP_P LP_USY LP_K# LP_SLN# LP_NT# LP_RR# LP_F# NS RN.K RN.K RN.K RN.K LP_ST# R0.K LP_0 LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_K# LP_USY LP_P LP_SLT LP_F# LP_RR# LP_NT# LP_SLN# LP_ST# p N 0p N 0p N 0p N 0p LP_ST# LP_0 LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_K# LP_USY LP_P LP_SLT 0 P 0 LPT LP_F# LP_RR# LP_NT# LP_SLN# LPT--K- F _00 F0 X_OPPR K_ MST MSLK KT KLK P 0_00 X_OPPR RN.K R X_K L 00 MS_T L 00 MS_K L 00 K_T L 00 K_K N 0p KMS 0 MNNx--ML US p 0 K_ K_ FLOPPY ONNTOR F P X_OPPR x-:-k RVN0 RVN NX# MOT_# RV_# RV_# MOT_# R# STP# WT_T# WT_N# TRK0# F_WP# RT# H# SKH# R R JMM X_YJ0 X_N X_N _S R0 P R K K R0 K R K RN# Q X_N0S Q X_N0S c=00m Vebo=V Vceo=0V RN# MS MRO-STR NT'L O.,LT. /O ONNTORS 00 MS- ate: Monday, May, 00 Sheet of L _00

24 PU_TRL SYS_TRL R R0 S S R R X_.K X_K Q0 X_N00S R X_.K R X_K Q X_N00S V Q X_S0S V T0 u Q X_S0S T u R.K R 0_0 R.K R0 0_0 N N FN SFN R R 0K 0K R.K PUFN x-wh-sn R.K SYS_FN x-wh-sn PU_FN PU FN SYS_FN SYSTM FN VRF_.V STNY POWR TRNSLTOR VRF_ (0mils trace / 0 mils space) VS - U YLMS-SO 0.0u _S S Q N00S R 0_% R 00_% 00 00p 0 _S 0.u-00 V V 0 R X_.K R0 K X_N R X_.K PWR_FN PX & MH.V POWR TRNSLTOR VS T u SMus solation V PWR_FN X_x-WH-SN SMLK POWR FN SMLK, VRF_ 0p - U YLMS-SO R R K % K % Q P0L-TO.V T 000u PWR_OK R 0K R 0K R.K R S Q N00S SMLK_SO SMT R000 SMLK_SO,,,, SMT, Q N0 0K S Q N00S SMT_SO R00 SMT_SO,,,, MS MRO-STR NT'L O.,LT. FN 00 MS- ate: Monday, May, 00 Sheet of

25 _S _S SL0 H L VUS MOSFT MOSFT **SO# pin function(hi level = V) same as VUS(Hi level = V) VUS US MOSFT Power S0 S _S Main Standby _STR Main Standby MM_STR Main Standby SLP_S# SLP_S#, PWR_ PWR_OK FP_RST# SLP_S# SLP_S# S Standby 0V 0V R R0 0 R 0 R K R.K R 0K _S R.K _S R 0K Q N0S X_ PS_ON# 00P _S S Q NS _STR T 000U/.V V UL Power **NPUT N MUST H LVL WHN US OUTPUT N FOR PO FUNTON R 0 R VTT Power.V/. Near 0 Q P0L-TO PWR_OK PWR_L SUS_L PRST#,,, PRST# PRST# H_RST#,,,,,,,, SMT_SO SMLK_SO R0 R 0 _S R X_.K R 0K R X_.K 0 0 PRST#/PO H_RST#/PO SLOT_RST#/PO V_RST#/PO _T _LK T_RV T_SN T_SNK 0 SL PL PL0 PWR_OK FP_RST#/PO PWR_OK/PO XTR_PW/PO HP_PW/PO PU_PW/PO RSM_RST#/PO SLP_S# SLP_S# SO#/PO/SL0 VRMRV VRMSN VRMRV SS VRM_._N VRM_._RV VS VROO.V_SN.V_RV V_US VS_RV V_RV TYPT# VP_SN VP_RV.VRF VS R X_K U 0 RSMRST# VRF_ 0P u-00 SMS P VRF_ Low RS ON MOSFT NS Q PN0L-S-TO VS u/00 T 000U/.V P _P.V Q P0L-TO VTT_R SL H TR-STT L 000U/.V VRM.VUL.VS.VSTR Q P0L-TO VRM_..V.V.V FOR VS OR VSTR STTN Y SL P FOR VUL STTN Y SL _S 000U/.V _S T 000u 000U/.V S _S 0P Wide Trace Q0 NS 0P 0 0.u XR Q PN0L-S-TO ** STTN VSTR THN VRM_. OM TO. VRF 0 W0 THS PN S OPN RN OUTPUT T 000U/.V _S 0P P MM_STR S Q P0L-TO _S V Q N00 0u-00 R.V Power.V/.. HR PUMP VOLT OUTPUT _V / V_OO Place MOSFT near PU.V/0. _V V_.0V.V MS 0 N00-S-SM- MM_STR MRO-STR NT'L O.,LT. P ONTROLLR 00 MS- ate: Monday, May, 00 Sheet of

26 R.K R V pf HOK.uH- pf T0 00u-V T 00u-V T 00u-V T 00u-V.u-0.u-0 u-00 V_ VRM_ PWM OO N R R.K V[..0] N0S R VR 0KST QK 0K X_p VR R0 X_K V V V V V0 R 0 0 0p R R 0K % 00p R KST KST R0 X_.K U0 V V V V V0 R POO FS/S OMP PWM SN PWM SN 0 F VSN NTS-HP0-SO R R.K %.K % R 0 V u-00 R0 0 u-00 V U PWM HP0 R 0 U P U_ 0 OOT u-00 PHS P PWM HP0 U_ OOT PHS L_ L_ 0p 0p R._00 R0 0_00 R._00 R0 u-00 0_00 F0L-S-TO S S S S Q0 PN0L Q F0L-S-TO Q PN0L Q HOK 0.u-0% HOK 0.u-0% T 00UF/.V-R T 00UF/.V-R T 00UF/.V-R T 00u T 00u T 00UF/.V-R T 00UF/.V-R T 00u P T0 00UF/.V-R T 00UF/.V-R 0 0p R0 R0 0 P R 0 HP0 -- VRM.0/. V V V V V0 V(V) OFF V V V V V0 V(V) NOT: NS ON PU SOKT. 0.0u V PULL-UP RSSTORS TXV POWR ONNTOR V 00p V p 0.0u 0 X_.u-0 JPW V V x X_.u-0 R 0-0 RLZ.V _V V0 V V V V R RN K K _V MS MRO-STR NT'L O.,LT. VRM.0 00 MS- ate: Monday, May, 00 Sheet of

27 TX ONNTOR _S RULTORS OUTPUT OUPLN PTORS _S _S _S 0 _S, pf -V R.K PS_ON# 0p pf -V.V.V -V.V PSON V V -V POK V VS 0 V V POWR pf 0 pf R K 0p 0 pf 0 X_u-00 pf 0 PWR_OK _S V MM_STR _STR u-00 _S 0 R 00K R K _S R K R % 0P _S R 0K Q N0S R K Q N0S S R K Q0 YFT-S0S R Q N0S R _S K RSMRST# HRSMRST#, 0 MS/ntel Front Panel R0 0 JFP, FP_RST# H _L FP_RST# H H- PL SL RST- PWSW RST PWSW- N PWR_L SUS_L PWRSW JFP JFP SUS_L PWR_L SUS_L PWR_L SPKR SL PL UZ UZ- SPK SPK SPK R0 P_0 JFP P_L S_L NS NS P _L POWR UTTON _S _S R K SPKR R.K PWRTN PWRTN SPKR LRM R.K R 0 R0 0 Q N0S SPK N 0P SPK UZZR SPKR PWRSW R 0P Q N0S R K X_u-00 MS MRO-STR NT'L O.,LT. Front Panel & TX onnector & FN 00 MS- ate: Monday, May, 00 Sheet of

28 LN SL _S Place Termination R as close to M as possible _R Near U ( ntel ) L_p L_p X L_M-pf-HS- LN_LK LN_RST LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX SOL 0 P 0 P X X LN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX SOL_TK SOL_T SOL_TX TSTN T T T T R R U TP TN RP RN LL# TL# SPL# RS0 RS00 TOUT V0 0 R0 L_00 % R L_ % LL LL _TL _TL SPL SPL R L_RST L_RST R TX TX- RXN RXN- TX TX- RXN RXN- Trace : mil Space : mil Space :0mil Trace : mil Space : mil LN_RST# LN_SL R L_0K R 0 R L_0K _S R L_00 Q L_N0S SOL R L_K P P R R R L_0 R0 L_00 0 L_NTL-T LN OPTON RSSTORS LN_RST LN_TX0 LN_TX LN_TX RN LN_SYN, LN_TX0, LN_TX, LN_TX, L_PR_ L_0P L_0P L_0P L_0P _S L_P/00 L_P/00 _R L_0P 0 L_0P F L_F0_00 L_P/00 _S L_0P LN_RX0 LN_RX LN_RX LN_LK RN L_PR_ LN_RX0, LN_RX, LN_RX, LN_LK, LL SPL 0 L_0P L_0P LN PROM L_0P RN RN- U T MT T TX T- TX- R RX R- RX- R RX L_TS X_ XR 0 TX TX- RX RX- _TL _S RN L_PR- R R L_0 TX TX- RXN RXN- L_0 LL RX- RX TX- TX SPL L_0P 0 0 LN_US MR MR- USLN N N RN N N RP TN TP Near H _S _SHLK _OUT _N U S SK O N N L_TL-x-0.us-SO _S Remark: M with :M-N00- T with :M-O00- * P X_OPPR F K_ S/00 MRO-STR NT'L O.,LT. LN NTL M/T 00 MS- Monday, May, 00 ate: Sheet of

29 P U_X FLSHM T_X TTRY U_ Q0- JT(-) YJUMPR-M JUO(-) YJUMPR-M JFP(-) YJUMPR-M JT lear MOS - - Normal* lear MOS P0-00-K0 hipset Heatsink MOS_Heatsink U-00 FN Header JUO(-0) OS_WP() YJUMPR-M X_YJUMPR-M U_ Q- OS_WP OS Update JLN LN SLT U-0 FN Header SHORT Locked - NL OPN Unlocked * - SL PU Retention MOS_Heatsink P_ P-0-WH-SN LN_US_ US X - pin UX_N_ YJ0-Y 0 OM OM--N JLN(-) X_YJUMPR-M Option :M Option :M P_ P-0-L-SN LN_US_ US X RJ UX_N_ YJ0-R MS MRO-STR NT'L O.,LT. MNUL PRTS 00 MS- ate: Monday, May, 00 Sheet of