0.9V, 5nW, 9ppm/C Resistorless Sub- Bandgap Voltage Reference in 0.18um CMOS

Transcription

1 0.9V, 5nW, 9ppm/C Resistorless Sub- Bandgap Voltage Reference in 0.18um CMOS Oscar Mattia, Hamilton Klimach and Sergio Bampi Microelectronics Graduate Program Electrical Engineering Department & Informatics Institute Federal University of Rio Grande do Sul Porto Alegre, Brazil 1

2 Outline Introduction Circuit Description Design Methodology Simulation Results Conclusion Acknowledgements 2

3 3 Introduction Basic Principle of the Bandgap Reference, introduced by Widlar in 1971: CTAT voltage counterbalance PTAT voltage PTAT & CTAT: proportional and complementary to absolute temperature 3

4 Circuit Description 4

5 Circuit Description BJT Bias Sweep VG1; Mirror Id to the junction; Find the crossing point between VG1 and Ve. 5

6 Circuit Description BJT Bias DC Op. Point 6

7 Circuit Description BJT Bias V E = t 1 m 1 2n [1 + ln 2eKW 5L I SQ I SE V T0 n t ] ISQ MOS Specific Current < 0dB ISE Junction Reverse Saturation Current Stable VT0 Threshold Voltage n MOS subthreshold slope m BJT non-ideality factor W MOS width L MOS length φt Thermal Voltage 7

8 Circuit Description BJT Bias V E = t 1 m 1 2n [1 + ln 2eKW 5L I SQ I SE V T0 n t ] < 0dB Stable 8

9 Circuit Description Self-Cascode Both transistors are in weak inversion; MHIGH is in saturation; MLOW can be in saturation or in triode. V DS LOW = n t ln I LOWS HIGH I HIGH S LOW PTAT [2] E. Vittoz, J. Felrath, JSSC

10 Circuit Description Sub-BGR Bias Circuit 10

11 Circuit Description Sub-BGR 3 Self-Cascode Cells 11

12 Circuit Description Sub-BGR -1mV/ C +1mV/ C V REF = + = V E 2 + n t ln 60 S 3S 5 S 7 S 2 S 4 S 6 12

13 Design Methodology Junction voltage of 550 mv 3.5 na; At least C for ID of every MOSFET; Balance the SC PTAT cells contribution; Round numbers for current mirror and SC PTAT aspect ratio gains; Standard transistors with VB = 0. 13

14 Simulation Results - Layout Area = mm² in 0.18um XFAB 14

15 Simulation Results - Temperature TC = 8.79 ppm/ C for C 5 27 C, C 15

16 Simulation Results Power Supply LS = mv/v and 69pA/V For VDD = V 100 Hz = -48dB VDD = 0.9 V 16

17 Simulation Results Variability Average Process Variation VREF TC Local Random Variation σ/μ = 2% die-to-die σ/μ = 0.8% within-die Yield = 96% for TC < 50 ppm/c 17

18 Simulation Results Comparison Specification [4] [5] [8] [6] [7] [9] This Unit Technology μm Temperature Range C TC ppm/ C Power E nw All papers are experimental results, except for this work. The best case result was chosen for comparison in all works. [4] De Vita et. al. JSSC, 2007 [5] Ueno et. al. JSSC, 2009 [6] Magnelli et. al. JSSC, 2011 [7] Seok et. al. JSSC, 2012 [8] Ming et. al. TCAS II, 2010 [9] Osaki et. al. JSSC,

19 Simulation Results Comparison Specification [4] [5] [8] [6] [7] [9] This Unit Technology μm Power Supply 100Hz V db Area mm² All papers are experimental results, except for this work. The best case reference was chosen for comparison in all works. [4] De Vita et. al. JSSC, 2007 [5] Ueno et. al. JSSC, 2009 [6] Magnelli et. al. JSSC, 2011 [7] Seok et. al. JSSC, 2012 [8] Ming et. al. TCAS II, 2010 [9] Osaki et. al. JSSC,

20 Conclusion Presented a nano-watt sub-bandgap voltage ref; New BJT bias topology and self-cascode PTAT cells; Achieves 9 ppm/ C for the C temp. range; 5 27 C and 0.9 V; Very small area of mm². 20

21 Conclusion Average process variation is main cause for variability; 2% sigma/mean process variation for Vref; 96% yield for a TC < 50 ppm/ C; Re-designed with similar results on IBM 0.13um. Sent to fabrication on 18 February

22 Acknowledgments CI-BRASIL Program for licensing XFAB 0.18um PDK and financial support; MOSIS Educational Program for licensing IBM 0.13um PDK and fabrication; 22