IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS 1

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1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS 1 BiCMOS-Based Compensation: Toward Fully Curvature-Corrected Bandgap Reference Circuits Yi Huang, Student Member, IEEE, Li Zhu, Student Member, IEEE, Fanpeng Kong, Chun Cheung, and Laleh Najafizadeh, Member, IEEE Abstract We present a novel BiCMOS-based temperature compensation technique aiming at complete correction of the curvature in the temperature response of bandgap references. The source of the appearance of this curvature is because the well-known nonlinear term T ln(t) in the base emitter voltage (V BE ) is not completely canceled across all temperature points. Here, we show that the gate-source voltage (V GS ) of a subthreshold-operating MOSFET, biased with a proportional to absolute temperature current, also exhibits the T ln(t ) nonlinear temperature dependence. We leverage the existence of T ln(t ) in the temperature response of V GS to directly cancel the nonlinear term T ln(t) in V BE. A theoretical analysis of the proposed compensation approach is presented. As a proof of concept, a current-mode voltage reference circuit, utilizing the proposed approach, is designed in IBM s 8HP Silicon Germanium (SiGe) BiCMOS technology. Thermal characteristics of the compensation components are examined through extensive simulations and are also experimentally evaluated, for the first time. Measurement results of the reference circuit show that the circuit outperforms the temperature performance of the state-ofthe-art SiGe reference circuits. Possible origins of observed temperature dependences and mitigation techniques are discussed. The proposed compensation approach can be realized in any BiCMOS/CMOS technology for implementing either currentmode or voltage-mode high precision reference circuits. Index Terms Silicon-germanium (SiGe), heterojunction bipolar transistors (HBTs), BiCMOS, bandgap voltage reference (BGR), curvature compensation, subthreshold, temperature coefficient (TC). I. INTRODUCTION PRECISE voltage reference circuits are essential building blocks in virtually all electronic circuits including data converters, voltage regulators and memories. A key requirement of a voltage reference circuit is to generate a voltage that is independent of temperature variations. Thermal independence is particularly important in applications where Manuscript received June 14, 2017; revised July 28, 2017; accepted August 1, This work was supported in part by the National Science Foundation under Award This paper was recommended by Associate Editor N. Krishnapura. (Corresponding author: Laleh Najafizadeh.) Y. Huang is with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ USA, and also with Intersil Corporation, Bridgewater, NJ USA ( yhuang85@rutgers.edu). L. Zhu and L. Najafizadeh are with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ USA ( laleh.najafizadeh@rutgers.edu). F. Kong was with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ USA. He is now with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA. C. Cheung is with Intersil Corporation, Bridgewater, NJ USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSI maintaining a high level of accuracy is required across wide temperature ranges [1] [8]. The most commonly used topology for the implementation of reference circuits is the bandgap reference (BGR) [9], [10]. A BGR is ideally designed to generate an output voltage that is referred to the bandgap energy of the background semiconductor material (which is strongly temperature independent). In Silicon (Si)-based technologies, the base-emitter voltage (V BE ) is related to the bandgap energy, and so it has been utilized to develop BGR circuits. However, in addition to being related to the bandgap energy, V BE is also a strong function of the temperature, depending linearly ( T ) and nonlinearly ( T ln(t )) on the temperature. Therefore, a major challenge in BGR design has been to find innovative ways to cancel the temperature dependent parameters in V BE. In a conventional BGR circuit, a proportional to absolute temperature (PTAT) component is generated to cancel the temperature dependency of V BE only to the first order. However, due to the existence of the high-order temperature effects, these circuits offer medium performance and are not adequate for high performance applications. To improve the temperature stability of BGR circuits, a variety of high-order temperature compensation solutions have been proposed (as will be discussed in Section II) to cancel higher order temperature effects of V BE related to T ln(t ) [11] [34]. Majority of these solutions cancel few higher order terms, leaving out some levels of temperature dependency in the output voltage. In this paper, a novel BiCMOS-based compensation technique is introduced which aims to directly cancel the nonlinear term T ln(t ) in the V BE, thereby, offering the possibility of achieving fully temperature-independent BGR circuits. The initial concept of the compensation approach was presented in [35]. Here, we provide extensive theoretical analysis along with simulation and measurements for the thermal characteristics of the compensation components. As a proof of concept, a current-mode BGR circuit is designed and implemented in the 8HP Silicon-Germanium (SiGe) BiCMOS technology. The SiGe technology is emerging to be the technology of choice for the development of high-speed data converters [36], RF communication circuits [37], [38], and extreme environment electronics [3], where precision reference circuits are required. While the circuit is implemented in SiGe technology, the proposed compensation approach can be realized in any BiCMOS/CMOS technology, and as such, we also provide discussions on how the proposed approach performs in Si vs SiGe technologies IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS The rest of this paper is organized as follows. In Section II, the design of BGR circuits with emphasis on temperature compensation, and prior techniques in addressing their temperature dependency, are briefly reviewed. In Section III, the proposed BiCMOS-based compensation solution is introduced after reviewing the operation of MOSFETs in the subthreshold region. The design of a current-mode BGR circuit incorporating the proposed compensation technique, is discussed in Section IV, where design equations for achieving a fully temperature-independent reference are derived. Measurement and simulation results of the compensation components and the reference circuit are presented in Section V. Discussions about the proposed compensation solution are provided in Section VI, and the paper is concluded in Section VII. II. BANDGAP REFERENCE DESIGN-REVIEW In the realization of a bandgap reference, at least one design component related to the bandgap energy must be available [10], [39]. In Si-based technologies, the relation to the bandgap energy is established through the base-emitter junction. Ignoring the small temperature variations in the bandgap voltage itself, the thermal dependency of the base-emitter voltage of the Si-based bipolar junction transistor (V BE,BJT ) can be expressed as [10], [40] V BE,BJT (T ) = V G0,Si [V G0,Si V BE0 ] T T 0 kt q (η θ)ln ( T T 0 ), (1) where V G0,Si is the extrapolated bandgap voltage of Si at 0 Kelvin, T is the absolute temperature in Kelvin, T 0 is the reference temperature, V BE0 is the base-emitter voltage at the reference temperature T 0, k is the Boltzmann constant, q is the electron charge, η is a process-dependent positive constant, and θ represents the order of the temperature dependency of the collector current I C, with which the transistor is biased: I C (T ) = I C0 ( T T 0 ) θ. (2) In (2), I C0 is the collector current at the reference temperature T 0. Note that when the collector current follows a PTAT behavior, θ = 1. Re-ordering the terms in (1), results in [ ] k V BE,BJT (T ) = V G0,Si (η θ) [T ln(t )] q }{{} nonlinear [ VG0,Si V BE0 k ] T 0 q ln(t 0) (η θ) T. (3) }{{} linear Equation (3) highlights the two temperature dependent terms in V BE,BJT (T ): the linear term (T ), and the nonlinear term (T ln(t )). In the design of BGR circuits, temperature dependent compensation components are generated and added properly to V BE,BJT in an attempt to cancel the temperature dependent terms in (3). The cancelation of the linear term is performed through the addition of the PTAT voltage/current, leading to what is known as the traditional first-order temperature compensated BGR circuits. For high precision reference circuits, the nonlinear term in (3) also needs to be canceled. This cancelation, however, due to the nature of the nonlinear term T ln(t ), has been challenging to achieve. A popular approach has been to perform the Taylor series on the expression of V BE,BJT (T ), and to design proper compensation circuits to cancel the few major high-order terms. Several solutions, including quadratic temperature compensation, second-order curvature compensation using resistor ratio, and piecewiselinear curvature correction, have been proposed for canceling the nonlinear term in (3) to some degree (e.g. up to 2 nd order) [11] [34]. In all these work, since the T ln(t ) is not completely canceled, there always exist some levels of temperature dependency in the output voltage. The recent work in [33] has proposed a solution to generate a current proportional to the nonlinear voltage kt q ln T T 0, in an attempt to compensate the high order terms. However, the technique used to generate the nonlinear current requires the existence of the temperature-independent current (θ = 0). This requirement introduces error in the cancelation process, as in practice θ = 0. As it will be shown in the next section, in the proposed compensation technique, the generation of the nonlinear term used for compensation is achieved through biasing the transistor with a PTAT current, which already exists in the circuit for the cancelation of the linear term in (3). III. BiCMOS-BASED COMPENSATION: PROPOSED TECHNIQUE FOR THE COMPENSATION OF THE NONLINEAR TERM Here, we first theoretically and then through simulations, show that the gate-source voltage (V GS (T )) of a subthresholdoperating MOSFET biased with a PTAT current, exhibits similar nonlinear T ln(t ) behavior that was observed in V BE (T ) in (3). Subthreshold-operating MOSFETs have recently gained an increasing attention for the realization of low power BGR circuits [43] [48]. In the subthreshold region (where V GS is set to be less than the transistor s threshold voltage (V TH ), the drain current (I D ) is expressed as [35], [44] I D (T ) = I S (T ) exp( V GS(T ) V TH (T ) )[1 exp( V DS )], nv T V T (4) where V DS is the drain-source voltage and I S (T ) is expressed as I S (T ) = W L μ(t )(n 1)C oxv 2 T. (5) In (5), μ(t ) is the carrier mobility, C ox is the gate-oxide capacitance, V T is the thermal voltage (V T = kt q ), n is the subthreshold slope factor (a process dependent constant around 1.5 [49]), and W and L correspond to the transistor s channel s width and length, respectively.

3 HUANG et al.: BiCMOS-BASED COMPENSATION: TOWARD FULLY CURVATURE-CORRECTED BGR CIRCUITS 3 Under the operating condition of V DS > 3V T (which is generally the case), (4) is simplified to I D (T ) = I S (T ) exp ( V GS(T ) V TH (T ) nv T ). (6) From (6), V GS (T ) can be derived as V GS (T ) = V TH (T ) + nv T ln( I D(T ) ). (7) I S (T ) Replacing (5) in (7), V GS (T ) can be re-written as V GS (T ) = V TH (T ) + nv T ln(i D (T )) nv T [ln( W ] L μ(t )(n 1)C ox) + 2ln(V T ). (8) In (8) the main temperature-dependent parameters are the threshold voltage (V TH (T )), the thermal voltage (V T ), the mobility (μ(t )), and the drain current (I D (T )) if the transistor is not biased with a temperature-independent current. The temperature dependency of the threshold voltage can be approximated as [50] [52] V TH (T ) = V TH0 α(t T 0 ), (9) where V TH0 is the threshold voltage at T 0,andα is a positive constant. The temperature dependency of the carrier mobility is estimated as [53] μ(t ) = μ 0 ( T T 0 ) m, (10) where μ 0 is the mobility at T 0 and m is a positive constant. Taking into account equations (9) and (10), and assuming that the transistor is biased with a PTAT current described as I D (T ) = I D0 ( T T 0 ), (11) where I D0 is the drain current at T 0, V GS (T ) in (8) is obtained as [ ] nk V GS (T ) =[V TH0 + αt 0 ]+ (m 1) [T ln(t )] q }{{} nonlinear [ ] 0 )] α + nk q [ln( k 2 W q 2 (n 1)C ox μ 0 T (m+1) LI } D0 {{} linear T. (12) Equation (12) indicates that V GS (T ) of a PTAT-biased subthreshold-operating MOSFET exhibits the nonlinear T ln(t ) behavior, similar to what is observed for V BE,BJT (T ) in (3). To further verify the existence of T ln(t ) dependency in V GS (T ) of a PTAT-biased subthreshold-operating MOSFET, we performed further analysis. Taking the derivative of (12) Fig. 1. a) Simulated V GS (T) and V TH (T) of a subthreshold-opearating MOSFET (M SubT hreshold ) as a function of temperature, with its circuit schematic, and b) V GS (T )/ (T ) fitted to the function ln(t ). with respect to T we find V GS (T ) (T ) [ ] nk = (m 1) ln(t ) q }{{} coefficient b + nk [ q (m 1) α+ nk q [ln( k 2 ] W q 2 (n 1)C ox μ 0 T (m+1) 0 )]. LI }{{ D0 } constant a (13) The existence of T ln(t ) dependency in V GS (T ) described by (12) therefore, can be verified by showing that its derivative follows ln(t ) behavior. To evaluate this behavior, we performed simulations using the structure shown in Fig. 1-a. Transistor M SubThreshold is biased with a PTAT current (through the current mirror M Mirror1 -M Mirror2 ), and its gate terminal voltage is controlled by a self-biased transistor M Sat, operating in the saturation region. The voltage at the source terminal of M SubThreshold is adjusted to ensure that it is operating in the subthreshold region across the temperature range of interest. Fig. 1-a also shows simulation results for V GS (T ) of M SubThreshold as well as its V TH (T ) vs temperature, demonstrating that M SubThreshold operates in the subthreshold region across the targeted temperature range. V Fig. 1-b shows GS (T ) (T ) for transistor M SubThreshold. MATLAB was then used to evaluate the goodness of fit of the derivative of V GS (T ) to the function ln(t ). AR 2 value of is obtained (with a = and b = ), suggesting the existence of T ln(t ) in V GS (T ). The existence of secondary design component in V GS (T ) with similar nonlinear temperature dependent behavior as V BE,BJT (T ), provides the designers with the possibility for direct compensation of the nonlinear term in BGR circuits. Additionally, an advantage of this technique is that there is no requirement for the MOSFET to be biased with a temperatureindependent current, which is difficult to realize. IV. PROOF OF CONCEPT Motivated by the proposed BiCMOS-based compensation solution, a current-mode BGR circuit is designed in IBM s 8HP SiGe BiCMOS technology. Current-based references

4 4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS have been designed and developed in several Si technologies [19], [31] [33], [43], [45], [48], [54]. Compared to voltage-mode references, the current-mode architecture provides several advantages, including being able to operate with sub-1 V power supply, or offering reference values that are different than the bandgap voltage of the background semiconductor material. While we have used a current-mode topology to realize the proposed compensation technique, the proposed BiCMOS compensation solution can also be incorporated in voltage-mode BGRs. The circuit consists of four major blocks: the I PT AT current generator, the I VBE current generator, the I VGS current generator, and the V REF generator. Details for each block are described here. Fig. 2. Schematic of the PTAT current generator circuit. A. The I PT AT Current Generator The schematic of the PTAT current generator with its startup circuit (consisting of transistors M S1 -M S4 ) is shown in Fig. 2. The core of the PTAT current generator (right side of Fig. 2) consists of transistors M 1 -M 6 and the resistor R 1. The operational amplifier (op-amp) uses vertical PNP BJTs as input transistors and follows the folded-cascode architecture [33], and is designed to offer large DC gain (see Fig. 3). Current mirrors M 1 -M 2 and M 5 M 6 have identical aspect ratios, and the opamp guarantees equal voltages at nodes A and B [55], ensuring equal currents in two branches (I 1 = I 2 ). Transistors M 3 and M 4 have different aspect ratios and are biased to operate in the subthreshold region [56] [58]. Following (12), it can be seen that the voltage difference between the V GS of these two transistors ( V GS ) generates a PTAT voltage that falls across the resistor R 1, generating current I PT AT (= I 1 = I 2 ), expressed as I PT AT (T ) = V GS4(T ) V GS3 (T ) = V GS(T ) R 1 (W/L) 4 ] R 1 = n ln[ (W/L) 3 nk ln[ V T = R 1 (W/L) 3 (W/L) 4 ] qr 1 T. (14) Since V TH is temperature dependent, careful design considerations were made in choosing the aspect ratios of transistors M 3 and M 4, to ensure they remain operating in the subthreshold region over the target temperature range. Note that while the PTAT current could also have been generated via the V BE difference of two HBTs instead of Fig. 3. Schematic of the operational amplifier used in PTAT current generator. the V GS difference of two sub-threshold operating MOSFETs (M 3 and M 4 ), by using the structure shown in Fig. 2, we were able to save on the number of transistors used in the circuit. This is because the V GS of transistor M 4 will be used later to generate I VGS (as will be discussed in Section IV-C). B. The I VBE Current Generator The I VBE current is generated based on the base-emitter voltage of SiGe HBTs. The energy band diagram of a gradedbased SiGe HBT is displayed in Fig. 4 and is compared to that in BJT [59]. In the case of SiGe, the introduction of compositionally graded Ge in the base (as shown by the dash lines), results in a finite band offset at the emitter-base junction ( E g,ge0 ) and a larger band offset at the collector-base junction ( E g,ge_wb ), compared to the V BE,HBT = V G0,SiGe V G0,SiGe V BE0 T kt [ ( ) ( )] T IC (T ) l ln ln T 0 q T 0 I [ ( )] [ C0 ( )] kt q ln T0 E g,ge(grade) kt 1 T E g,ge(grade)0 q ln exp( Eg,Ge(grade)0 /kt 0 ) 1 exp( E g,ge(grade) /kt [ ] [ k kt V BE,HBT (T ) = V G0,SiGe (l 2) [T ln(t )] + q q ln ( 1 exp( E g,ge(grade) /kt) ) ] }{{}}{{} nonlinear 1 nonlinear 2 [ VG0,SiGe V BE0 k ( )] T 0 q ln T0 (l 2) E g,ge(grade) (1 exp( E g,ge(grade)0 /kt 0 )) T E g,ge(grade)0 }{{} linear (15) (16)

5 HUANG et al.: BiCMOS-BASED COMPENSATION: TOWARD FULLY CURVATURE-CORRECTED BGR CIRCUITS 5 Fig. 4. Energy band diagram for the Si BJT and the SiGe HBT (after [59]). Si counterpart. The Ge-induced bandgap offset is expressed as E g,ge(grade) = E g,ge0 E g,ge_wb [59]. The base-emitter voltage of the SiGe HBTs can be expressed as (15), as shown at the bottom of the previous page, where V G0,SiGe is the extrapolated bandgap voltage of SiGe at 0 K, E g,ge(grade)0 is the Ge grading-induced bandgap offset at T 0, and l denotes the saturation current temperature exponent [59]. Assuming the collector current of the HBT is a PTAT current (i.e. θ = 1 in (2)), and E g,ge(grade) does not change with temperature [59] and rearranging the terms in (15), equation (16), as shown at the bottom of the previous page, is obtained where the linear and nonlinear T dependent terms are identified [60]. E g,ge(grade) is typically around 100 mev, therefore, over the temperature range of [0 150] C, the nonlinear 2 term in (16) can be neglected, kt i.e. q ln(1 exp( E g,ge(grade) /kt)) 0. Neglecting the second nonlinear term in (16), and comparing (3) and (16), one can see that, similar to the BJT, in the case of the HBT, the base-emitter voltage exhibits both linear ( T ) and nonlinear ( T ln(t )) temperature dependencies. The schematic for the I VBE current generator circuit is shown in Fig. 5-a [39]. A PTAT current is used to drive the HBT Q 1. Cascode current mirror pairs M 10a -M 11a, M 10b - M 11b and transistor M 12 form a negative feedback loop [39], and capacitor C 2 is added to stabilize the loop. The baseemitter voltage of Q 1 falls across resistor R 3, generating the I VBE current that is proportional to V BE,HBT (T ), expressed as I VBE = V BE,HBT(T ). (17) R 3 Note that HBTs carry very large current gain [59] (for this technology the nominal current gain for the NPN HBT is 460), and hence, the error introduced by the base current can be neglected. C. The I VGS Current Generator To directly cancel the nonlinear T ln(t ) term in I VBE, a circuit (see Fig. 5-b) for generating a current proportional to V GS (T ) of a subthreshold-operating MOSFET is designed. As mentioned in Section IV-A, transistor M 4 operates in the subthreshold region. A feedback transistor, M 9, is included in the circuit [39], and the capacitor C 3 is added to stabilize the negative feedback loop. The V GS of transistor M 9 equals V DS of transistor M 4. The current V GS (T ), proportional to the gate-source voltage of M 4 (which includes both linear and Fig. 5. Schematic of a) I VBE current generator circuit, and b) I VGS current generator circuit. Fig. 6. Schematic of the V REF generator circuit. nonlinear T ln(t ) terms), is generated through resistor R 2 as I VGS (T ) = V GS4(T ). (18) R 2 D. The V REF Generator The three currents I PT AT, I VBE and I VGS generated by the structures described above, will be mirrored, scaled properly and added. Fig. 6 shows the schematic of the V REF generator circuit. V REF is expressed as V REF = R 4 [K 1 I VBE (T ) + K 2 I VGS (T ) + K 3 I PT AT (T )] = K 1 R 4 R 3 V BE,Q1 (T ) + K 2 R 4 R 2 V GS4 (T ) + K 3 R 4 R 1 CV T, (19) where C = n ln[ (W/L) 3 (W/L) 4 ], and parameters K 1, K 2 and K 3 are current scaling factors (determined by the aspect ratios in current mirrors) for I VBE, I VGS and I PT AT currents, respectively. These factors need to be properly determined such that the temperature dependency of the total current flowing through resistor R 4 (and thereby, the generated voltage V REF ), is minimized. Since the output voltage is dependent on the resistor ratio, if both resistors are made of the same material, the dependency of the output voltage to variations in resistors will be minimized. We now find the design equations required for determining the current scaling factors K 1, K 2 and K 3. Referring to (12) and (16) for V GS4 (T ) and V BE,Q1 (T ), to minimize the temperature dependency of V REF, the following two conditions need to be met: cancelation of the temperature dependent linear term as seen in (20), as shown at the bottom of the next page.

6 6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS cancelation of the temperature dependent nonlinear term as [ ] [ ] R 4 k R 4 nk K 1 (l 2) = K 2 (m 1). (21) R 3 q R 2 q Re-ordering terms in (21) results in the following design equation for the cancelation of the nonlinear term K 1 = R [ ] 3 n(m 1). (22) K 2 R 2 (l 2) The design equation (22) relies on the technology-dependent parameters (m, n and l). The estimated value for the carrier mobility temperature exponent m is typically 1.5 [44], [50], and the value for the saturation current temperature exponent l has been approximated to be between 3 to 4 [39], [59] [63], ensuring that a positive number is obtained for the ratio of scaling factors K 1 and K 2. Replacing (22) in (20) and re-ordering terms, the design equation for canceling the linear term ( T ) is obtained as K 3 = R [ ] 1 A K 2 R 2 nk q ln[ (W/L), (23) 3 (W/L) 4 ] where A is described in (24), as shown at the bottom of this page. When design conditions (22) and (23) are met, a temperature-independent V REF is obtained as V REF = R 4 R 3 K 1 V G0,SiGe + R 4 R 2 K 2 [V TH0 + αt 0 ]. (25) V. VERIFICATION The proposed reference circuit was designed in IBM s 8HP SiGe BiCMOS technology. p + polysilicon resistors, which have a very small temperature coefficient, were used to implement all the resistors. Common-centroid layout technique was employed for the realization of the current mirrors to minimize the effects of mismatch. The micrograph of the circuit is shown in Fig. 7. The circuit occupies an active area of μm 2 excluding bondpads. A resistive network was also included to allow trimming of the post-fabricated circuit and to compensate for the effects of process variations, inaccuracies in simulation models, and package stress that may occur after fabrication. Additional pads (not shown in Fig. 7) were included to monitor the voltage values of Fig. 7. Die microphotograph and layout of the voltage reference circuit employing the proposed compensation technique. internal nodes, to study the temperature dependency of the I PT AT and the I VGS currents (see Fig. 8). Since thermal characteristics of SiGe HBTs have been previously extensively investigated [1], [8], [59], [64] [66], the I VBE current is not characterized here. For measurements, three circuits from three different wafers were characterized. Each circuit was mounted in a 28-pin ceramic DIP package and wirebonded. A thermal conductive lid was used to shield the bonded die from the impact of airflow during thermal measurement. The package was placed into a zero-insertion-force (ZIF) socket soldered on a PCB. Thermal characterization was done using ThermoJet ES precision temperature cycling system from SP Scientific [67]. A thermal cap, covering the PCB, isolated the board from the exposure to the external environment. Voltage measurements were done using Keithley 2000 units. To minimize the loading effect of measurement equipment, buffers were placed between the PCB and the Keithley units [68] (see Fig. 9). In addition to experimental evaluation, to further investigate the effects of mismatch and process variations, extensive Monte Carlo and corner simulations were run, with all passive devices (resistors and capacitors) and active devices (MOSFETs, SiGe HBTs and Si Vertical PNP devices) included. Simulation and experimental results for the compensation components as well the V REF, are presented and discussed in this section. A. The I PT AT Current The PTAT current in this circuit was generated through the difference of the gate-source voltages ( V GS ) of two subthreshold-operating transistors (M 3 and M 4 ). To evaluate the effects of mismatch and process variation on V GS, Monte Carlo simulations (1000 runs including process variations and [ R 4 VG0,SiGe V BE0 K 1 k ( (l 2) R 3 T 0 q ln T0 E g,ge(grade) )] (1 exp( E g,ge(grade)0 /kt 0 )) E g,ge(grade)0 [ α + nk q [ln( k 2 ] W q 2 (n 1)C ox μ 0 T (m+1) 0 )] LI D0 + K 2 R 4 R 2 [ ] R 4 nk = K 3 R 1 q ln[(w/l) 3 ] (W/L) 4 (20) A = n(m 1) (l 2) [ VG0,SiGe V BE0 k ( )] (l 2) T 0 q ln T0 E g,ge(grade) (1 exp( E g,ge(grade)0 /kt 0 )) E g,ge(grade)0 [ + α + nk q [ln( k 2 ] W q 2 (n 1)C ox μ 0 T (m+1) 0 )] LI D0 (24)

7 HUANG et al.: BiCMOS-BASED COMPENSATION: TOWARD FULLY CURVATURE-CORRECTED BGR CIRCUITS 7 Fig. 8. Schematic of the reference circuit, resistive network (circuit 1) and the test structure for the experimental characterization of the PTAT current (circuit 2). Fig. 10. Measured I PT AT and its percentage deviation from linearity as a function of temperature. Fig. 9. Illustration of the experimental setup for thermal characterization of the circuits. TABLE I SUMMARY OF MONTE CARLO SIMULATION RESULTS FOR V GS AND V GS4 AT FOUR TEMPOERATURE POINTS mismatch for all passive and active components) were run at four temperature points. Results are summarized in Table I. In this Table, μ and σ denote mean and standard deviation, respectively. It can be seen that the worst-case coefficient of variation (σ/μ) is 2.33% (obtained at T = 0 C), indicating that mismatch and process variations have negligible effects on V GS. The I PT AT current, generated by the V GS of two subthreshold-operating MOSFETs, was also experimentally evaluated using a test structure that was included with the circuit (see Fig. 8-Circuit 2). In this structure, the PTAT current from the BGR circuit is mirrored and flown through an external resistor R TEST. The generated PTAT voltage across this resistor was measured over [0 150] C, via the V PT AT bondpad. Voltage measurements were then converted into current. Measurement results are shown in Fig. 10, clearly demonstrating a PTAT behavior. To further analyze the linearity of the measured I PT AT, its percentage deviation from a linear line (I PT ATIDEAL (T )) Fig. 11. Simulated and measured V GSSAMPLED and simulated V TH as a function of temperature. described as I PT ATIDEAL (T ) = I PT AT (0 C) + I PT AT (150 C) I PT AT (0 C) T, (26) was calculated, following %I PT ATERROR (T ) = I PT AT IDEAL (T ) I PT AT (T ) 100. (27) I PT ATIDEAL (T ) Results are plotted in Fig. 10. The percentage deviation from linearity for the measured I PT AT stays below 0.12% over the temperature range of interest. This result along with Monte Carlo simulations validate the feasibility of using subthreshold-operating MOSFETs to generate the PTAT components for the cancelation of the linear term, and are also of interest to subthreshold-based circuit designers. B. The I VGS Current As it was shown in Section III (both theoretically and through simulations), the V GS of a subthreshold-operating MOSFET biased with a PTAT current, includes a term with T ln(t ) behavior. This voltage was then used to generate the current I VGS, to cancel the T ln T in I VBE. To examine the effect of mismatch and process variation on V GS, Monte Carlo simulations were run for V GS4 at four temperature points. Results are summarized in Table I.

8 8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS TABLE II SUMMARY OF MONTE CARLO SIMULATION RESULTS FOR V REF AT FOUR TEMPERATURE POINTS TABLE III TC AT TRANSISTOR CORNERS Fig. 12. Normalized deviation from linearity for simulated and measured V GSSAMPLED,aswellasfor1/10 analytical estimation of V GS. It can be seen that the coefficient of variation (σ/μ) is higher than what was observed for V GS and it increases with temperature. To compensate for this variation, a trimming network is necessary to be included. We further experimentally examined the temperature response of V GS4. Resistor R 2 in Fig. 5 was implemented by two series-connected resistors (R 2_1 and R 2_2 ), with 1:9 ratio. Through the V GSSAMPLED bondpad (see Fig. 8), the voltage across resistor R 2_1 was measured over the target temperature range. This voltage represents 1/10 of the actual V GS value of transistor M 4. Simulation and measurement results for V GSSAMPLED are shown in Fig. 11, which clearly demonstrate the negative temperature dependency of the V GS. While there are expected differences between the measurement and simulation results (due to process variations, and errors during measurement caused by package stress and loading effects), the outcomes are fairly close. To ensure that transistor M 4 has maintained operating in the subthreshold region across the intended temperature range, in the same figure, we also have included simulated values for the threshold voltage (V THSIMULATED )at different temperature points. It can be seen that the difference between V THSIMULATED and V GS4 (= 10 V GSSAMPLED ) remains larger than 100 mv across the temperature, showing that the transistor indeed maintained its subthreshold-operating status across the temperature range of [0-150] C. Note that due to a limited number of measurement points, a similar approach discussed in Section III (i.e. taking the derivative of V GS numerically with respect to temperature), can not be taken to evaluate its nonlinearity. Normalized deviation from linearity for simulation and measured results are shown in Fig. 12. Here we are also showing normalized deviation from linearity obtained from the analytical model for V GS obtained from (12). The parameters in (12) were estimated from the literature. Because of different scaling levels across three curves, curves were normalized to their minimum value, for the purpose of visualization. Results confirm the presence of nonlinear terms in all three cases. Fig. 13. Simulation results for V REF of a) the reference circuit employing the proposed compensation approach, with and without I VGS, and b) an optimallydesigned first-order BGR, and the reference circuit employing the proposed compensation approach. C. The Output Voltage V REF Fig. 13-a shows simulation results for V REF as a function of temperature. To show the effectiveness of the proposed curvature compensation technique, simulation results for V REF for the case when I VGS is excluded are also shown. It can be seen that the inclusion of the I VGS significantly impacts the TC performance. Fig. 13-b compares the performance of the compensated circuit with that of an optimally designed firstorder circuit (where the coefficients of I PT AT and I VBE are tuned to obtain an optimum first-order BGR with the nominal voltage equal to that of the designed compensate BGR). It can be seen that by the inclusion of the I VGS, the curvature compensated circuit achieves a much improved TC (more than 5 times better). To investigate the effects of mismatch and process variation on V REF Monte Carlo simulations (1000 runs) were run with all components (SiGe HBTs, MOSFETs, Si Vertical PNPs, resistors and capacitors) included, and results at four temperature points are summarized in Table II. The worstcase coefficient of variation (σ/μ) is 2.21% obtained at T = 150 C. Despite variations that were observed in V GS4, the circuit demonstrates a reasonably robust performance against mismatch and process variations. Table III summarizes the simulation results for MOS transistors corners. The circuit achieves temperature coefficient (TC) of less than 11.8 ppm/ C in the worst-case, indicating that the circuit is reasonably robust against corner variations. To evaluate the effects of mismatch and process variations on TC of the first order BGR and the proposed curvature compensated BGR, we performed Monte Carlo

9 HUANG et al.: BiCMOS-BASED COMPENSATION: TOWARD FULLY CURVATURE-CORRECTED BGR CIRCUITS 9 Fig. 14. a) Monte Carlo simulation results (1000 runs, with SiGe HBTs, MOSFETs, Si Vertical PNPs, resistors and capacitors included) for first order BGR between 0 C to 150 C at untrimmed condition, and b) the histogram of the calculated TC from (a). c) Monte Carlo simulation results (1000 runs, with SiGe HBTs, MOSFETs, Si Vertical PNPs, resistors and capacitors included) for V REF of the proposed curvature compensated BGR between 0 C to 150 C at untrimmed condition, and d) the histogram of the calculated TC from (c). e) Monte Carlo simulation results (1000 runs, with SiGe HBTs excluded) for V REF of the proposed curvature compensated BGR between 0 C to 150 C at untrimmed condition, and f) the histogram of the calculated TC from (e). simulation of 1000 runs considering both mismatch and process variations (with SiGe HBTs, MOSFETs, Si Vertical PNPs, resistors and capacitors included) at 0 C, 30 C, 60 C, 90 C, 120 C, and 150 C. Figs. 14-a and 14-c illustrate V REF as a function of temperature for the first order and the curvature compensated BGR circuits, respectively. Figs. 14-b and 14-d show the histogram of the calculated TC over 1000 simulation runs, for the first order and the curvature compensated BGR circuits, respectively. The TC was calculated for T 0 = 30 C, and over [0 150] C. Across 1000 runs, an average TC of 54.0 ppm/ C is achieved for the first order BGR, while this number is significantly reduced to 23.8 ppm/ C for the proposed curvature compensated BGR. The calculation of the coefficient of variation is not applicable here as sigma is not meaningful in non-gaussian distributions [43]. Variations are always expected in Monte Carlo simulations [43], [69], but comparing Figs. 14-b and 14-d, the number of samples showing large TC are significantly lower for the proposed curvature compensated BGR, as compared to the first order BGR. For example, 44.9% of samples show TC> 50 ppm/ C in the first order BGR, while only 6.4% of samples show TC> 50 ppm/ C for the proposed compensated BGR. Note that these Monte Carlo simulation results are obtained in the most general case where mismatch and process variations for all components (SiGe HBTs, MOSFETs, Si Vertical PNPs, resistors and capacitors) are included. These results, along with the nominal simulation results shown in Fig. 13-b provide convincing evidence that the proposed curvature compensation approach outperforms the first-order BGR in terms of temperature stability and precision. The curvature compensated BGR circuit includes subthreshold-operating MOS transistors, MOSFETs operating in the saturation region, Si Vertical BJTs and a SiGe HBT transistor. Therefore, a fair comparison with existing CMOS references cannot be made. Monte Carlo simulation results for the TC were also not available for other SiGe reference papers. To be able to do a relatively fair comparison with the state of the art CMOS reference circuits, we excluded the SiGe HBTs in Monte Carlo simulations and ran simulations of 1000 runs with mismatch and process variation, and included MOSFETs, Si Vertical PNPs, resistors and capacitors. Simulation results and the corresponding histogram for TC are shown in Figs. 14-e and 14-f, respectively. It can be seen that an average TC of 17.8 ppm/ C is achieved across [0 150] C, which is much smaller than what was observed in Fig. 14-d. Looking at equations (19), (20), (24) and (25), the dependence on Ge doping profile and Ge-induced bandgap offset can be seen. Therefore, removing SiGe HBTs from Monte Carlo simulation runs is expected to enhance the stability. In addition, only 1.9% of samples show TC> 50 ppm/ C in this case. To investigate how trimming would improve the performance of the circuit, we further considered a subset of trimming options provided by the resistive network shown in Fig. 8, and performed Monte Carlo simulations. Considering the top three connections and the option of shorting resistor R 2_1, 1000 Monte Carlo simulations, including mismatch and process variation for all components, were run. The histogram of obtained TCs is shown in Fig. 15. As expected, compared to the untrimmed scenario, the TC in terms of the average and the range of variations, has been improved after trimming. The average TC across 1000 simulation runs after trimming is now 9.7 ppm/ C with 91.3% of samples showing TC< 20 ppm/ C. The trimming performance of course, can be further improved by considering more trimming options in the resistive network, and also by incorporating trimming networks for resistors R 1 and R 3. Table IV summarizes the results presented in Figs. 14 and 15. Table V compares the performance of Monte Carlo simulation results of the untrimmed proposed reference circuit, with the state of the art CMOS reference circuits that had reported their Monte Carlo simulation results for the untrimmed condition. In the table, we have included CMOS-based bandgap circuits, those that exploit zero temperature coefficient (ZTC) point, and those that have subthreshold

10 10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS TABLE IV COMPARISON OF UNTRIMMED AND TRIMMED MONTE CARLO SIMULATION RESULTS TABLE V PERFORMANCE COMPARISON WITH UNTRIMMED CMOS REFERENCES (MONTE CARLO SIMULATIONS) Fig. 15. Histogram of TCs for 1000 runs obtained with considering the top three connections in the resistive network shown in Fig. 8. Mismatch and process variation (for all components) were included. devices. Note that there exist several CMOS reference circuits with improved TC (usually obtained after trimming), but their untrimmed Monte Carlo simulation results were not available to be included in this table. From this table, it can be seen that, in terms of TC, the untrimmed proposed compensation technique outperforms these circuits at untrimmed condition ( twice reduction in TC compared to the best case, even when SiGe HBTs are included). This is achieved considering that for our case, the number of simulation runs is the largest, and the temperature range is wider (150 C) compared to most cases in the table. The measured trimmed output voltage of the reference circuit employing the proposed compensation technique, and operating with 1.6 V power supply for three units coming from three wafers, as a function of temperature, is shown in Fig. 16. All measured units showed high stability with respect to temperature variation with unit 1 exhibiting the best temperature coefficient (TC) (9.9 ppm/ C across [0 150] C). The average TC across three units is 13.1 ppm/ C over [0 150] C. The observed difference in the nominal output voltage values across three units is most likely due to the Fig. 16. Experimental results for the trimmed output voltage of the voltage reference employing the proposed compensation solution for three units from three different wafers as a function of temperature. variation in Ge doping level (and impacting V G0,SiGe )and other process variations (e.g. V TH0 or α) across wafers, as each unit is coming from a different wafer. A simple trimming procedure was followed. First V REF was observed across temperature with no resistor in the trimming network selected. Second, V REF was observed across temperature with the bondpad V GSSAMPLED in Fig. 8 shorted to the ground. Based on the results of these two cases, proper resistance in the trimming network was estimated to minimize the deviation across temperature. With this choice, V REF was then measured across temperature. Other more effective trimming approaches such as those proposed in [33] and [69] can be incorporated to obtain an even better TC. Furthermore, note that here we only had the resistive network for the tuning of the I VGS. Additional trimming networks can be added for resistors R 1 and R 3 to adjust the I PT AT and I VBE currents as well, to achieve an even more highly stable output voltage. Fig. 17 shows the measured output voltage for unit 2 as a function of temperature, for the supply voltage ranging from 1.6 V to 1.8 V. The unit was first trimmed at 1.6 V supply voltage, and then measured at 1.7 V and 1.8 V supply voltages

11 HUANG et al.: BiCMOS-BASED COMPENSATION: TOWARD FULLY CURVATURE-CORRECTED BGR CIRCUITS 11 TABLE VI PERFORMANCE COMPARISON WITH PRIOR SiGe-BASED BGRs (MEASUREMENTS) Fig. 17. Measured output voltage (trimmed at 1.6 V ) as a function of temperature for different supply voltages. Fig. 18. Measured power supply rejection ratio (PSRR) at room temperature, with a 1.6 V supply, and without a filtering capacitor. over the entire temperature range by preserving the same trimming option that was identified at 1.6 V. The proposed BGR circuit continues to exhibit high temperature stability when operating at different power supply voltage values. At room temperature, the reference circuit exhibits a line regulation of 0.24 %/V for supply voltage ranging from 1.6 V to 1.8 V.The power supply rejection ratio (PSRR) of this BGR, measured at room temperature by Model 200 Frequency Analyzer from AP Instrument, is shown in Fig. 18. The circuit shows 40 db PSRR at 10 Hz, and less than 36 db at 100 Hz, which is comparable to what is reported in [29] and better than what is reported in [72] for a SiGe reference. The PSRR can be further improved by employing PSRR enhancement techniques such as the one proposed in [69] and [73]. Fig. 19-a shows deviation in the output voltage of unit 2 from its mean, measured over 30 minutes, at room Fig. 19. a) Measured output voltage over time at room temperature, and b) simulated output noise spectral density of the output without any buffer or filtering capacitor. temperature, without using any output filtering capacitors. It can be seen that changes in the V REF over time remains to be less than 0.028%. Fig. 19-b shows simulation results for the noise without any filtering capacitor. The simulated output noise spectral density is 1.97 μv/ Hz at 100 Hz. The noise spectral density can be further reduced by introducing a filtering capacitor [43]. Table VI compares the performance of the proposed circuit with some of previously designed SiGe-based BGR circuits. The proposed reference circuit offers superior performance in terms of temperature stability and power consumption. Since the circuit was implemented in the SiGe technology platform, performance comparison with existing references implemented in Si technology platforms (CMOS, BJT) was not made here, due to differences in the technology. It is expected to see even a much better performance if the proposed compensation technique is realized in Si-based technology (compare (3) and (16)). This SiGe circuit in fact offers comparable performance (in terms of temperature stability) to Si-based circuits [28], [31], [32], [74], [75], despite technology differences (Si vs SiGe). VI. DISCUSSION In this paper, we presented the theoretical basis along with simulation and experimental results for a new BiCMOSbased curvature compensation technique to achieve fully temperature-independent reference circuits. The introduction of a secondary design component with T ln(t ) temperature dependency provides BGR designers with an option to achieve complete cancelation of the nonlinear term in V BE (T ) and obtain a highly temperature-stable reference circuit.

12 12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS The contributions of this paper are as follows: 1) we demonstrated for the first time, theoretically and through simulations, that T ln(t ) temperature dependency exists in V GS (T ) of subthreshold-operating MOSFET that is biased with a PTAT I D (T ) current. We also presented measurement results for V GS (T ) of a subthreshold-operating MOSFET and showed that the measured results closely follow theoretical derivations; 2) we presented a new BiCMOS compensation solution to directly cancel the T ln(t ) dependency in V BE (T ) using the T ln(t ) dependency identified in V GS (T ) of a subthresholdoperating MOSFET biased with a PTAT I D (T ); 3) we, theoretically and experimentally, verified that a PTAT current can be generated through V GS (T ) of two subthresholdoperating MOSFETs. Monte Carlo simulation results across various temperature points showed that mismatch and process variations have a negligible impact on V GS (T ), and hence, the generated PTAT current; 4) as a proof of concept of the proposed compensation solution, a current-mode BGR was designed in SiGe BiCMOS technology. Design equations were derived, and simulation and measured results for the reference circuit were extensively presented, demonstrating that the circuit outperforms existing SiGe reference circuits in terms of TC, and 5) we identified differences in nonlinearities observed in V BE (T ) of a Si BJT and V BE (T ) ofasigehbt,andtheir impact on the proposed compensation solution. The benefits of the proposed compensation solution can be summarized as follows: 1) it aims to directly cancel the nonlinearities in V BE (T ); 2) it does not require temperatureindependent currents for biasing the transistors (as was required in [33]), and it achieves compensation through biasing transistors with PTAT currents, which are already available in the circuit; 3) it can also be easily incorporated with existing first-order current-mode BGR circuits to further improve their thermal stability; 4) it is not limited to current-mode BGRs and can be utilized in voltage-mode BGR circuits as well; and 5) while we presented the results for a circuit implemented in a SiGe technology, it can be implemented in any BiCMOS/CMOS technology. The measured results of the SiGe voltage reference presented here, while still demonstrating a highly temperature stable output and superior performance to existing SiGe circuits, revealed deviation from being fully temperature-independent. One reason for the observed deviation is that the I VBE current was generated from the base-emitter voltage of the SiGe HBT, as expressed in (16). Several terms exist there that depend on the Ge doping profile and Ge-induced bandgap offset. We neglected the temperature dependencies of these parameters. In addition, we neglected the temperature variation in (16) introduced by the nonlinear 2 component. The temperature dependencies of these parameters have likely played roles in causing deviation from achieving complete thermal stability. In fact, comparing the expressions of V BE,BJT (T ) and V BE,HBT (T ) ((3) and (16)), we believe that if the proposed approach is implemented in Si technology (either BiCMOS or in CMOS by utilizing lateral or vertical BJTs) the Si-based reference circuit will achieve a much better performance in terms of temperature stability. Lack of accurate models for technology parameters in the simulator when designing the circuit, could also be the reason for the observed deviation in post-fabricated measurements. In addition, in deriving the theoretical basis for the compensation approach, we assumed V TH (T ) is a linear function of temperature [43], [50]. Depending on the technology, the high-order temperature dependency of V TH (T ) could contribute to the deviation in V REF from being fully temperature independent. To address these issue, as well as the issue of sensitivity of subthreshold-operating transistors to process variations, trimming networks should be incorporated. In our design, we included a simple trimming network for adjusting the I VGS current only. Additional trimming networks can be added for resistors R 1 and R 3 to adjust the I PT AT and I VBE currents as well, and more effective trimming procedures [33], [69] can be employed, to achieve a highly stable output voltage. VII. CONCLUSION In this paper, a novel BiCMOS-based compensation approach for achieving fully curvature-corrected BGR circuits was presented. The proposed compensation approach via utilizing subthreshold-operating MOSFETs, introduces an innovative and elegant solution to directly cancel the nonlinear T ln(t ) term in the I VBE component, thereby, offering the possibility of achieving fully temperature-independent BGR circuits. Theoretical basis of the proposed compensation approach was extensively described and design equations were derived. Based on the proposed BiCMOS-based compensation approach, a low temperature coefficient current-mode BGR circuit was designed and fabricated in IBM s 8HP SiGe technology. The compensation components (the PTAT and the I VGS components) were experimentally characterized for the first time, and results validated the theoretical analysis. Measurement results for the reference circuit showed the circuit offers highly temperature stable output across [0 150] C. The presented BiCMOS-based compensation technique can be realized in any CMOS/BiCMOS technology to obtain highly precise reference circuits required for high performance voltage regulators and high resolution ADCs. ACKNOWLEDGMENT The authors are grateful to Professor John Cressler at the Georgia Institute of Technology for his support for the fabrication of the chips. They would like to thank the anonymous reviewers for their valuable suggestions and comments. REFERENCES [1] L. Najafizadeh et al., SiGe BiCMOS precision voltage references for extreme temperature range electronics, in Proc. IEEE BCTM, Oct. 2006, pp [2] B. G. Rax, C. I. Lee, and A. H. Johnston, Degradation of precision reference devices in space environments, IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp , Dec [3] R. M. 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Zhang, A high-precision compensated CMOS bandgap voltage reference without resistors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 10, pp , Oct [76] A. S. Cardoso et al., Single-event transient and total dose response of precision voltage reference circuits designed in a 90-nm SiGe BiCMOS technology, IEEE Trans. Nucl. Sci., vol. 61, no. 6, pp , Dec Yi Huang (S 14) received the B.S. degree from the Beijing University of Aeronautics and Astronautics, China, in 2007, and the M.S. degree from Stony Brook University State University of New York, Stony Brook, NY, in He is currently pursuing the Ph.D. degree in electrical engineering with Rutgers University, Piscataway, NJ. He is also a Senior Applications Engineer with the Intersil Corporation New Jersey Development Center. His research interests include analog/mixed-signal circuit design, and control and modeling of power electronics converters. He was a recipient of the 2016 IEEE Circuits and Systems Society Student Travel Award and the Best Student Paper Award (Runner Up) from the 2014 IEEE International Symposium on Circuits and Systems. Li Zhu (S 13) received the B.S. degree from the Wuhan University of Technology, China, in 2004, and the M.Sc. degree in electronics and communication engineering from the Huazhong University of Science and Technology, China, in He is currently pursuing the Ph.D. degree in electrical and computer engineering with Rutgers University. Fanpeng Kong received the B.S. degree from the University of Electronic Science and Technology of China, Chengdu, China, and the M.S. degree from Rutgers University, Piscataway, NJ, in 2014 and 2015, respectively. He is currently pursuing the Ph.D. degree with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA. Chun Cheung received the B.S. and M.S. degrees from Binghamton University State University of New York, Binghamton, NY, in 1998 and 2000, respectively. He was a member of the First and Third Place Innovation Awards Recipient Team, Intersil Corporation, in He is currently the Applications Engineering Manager with the Intersil New Jersey Development Center, responsible for the production definition and validation on PWM controllers, drivers, and smart power stage. He is the inventor of five U.S. patents, and the author of over ten technical papers. His experiences include isolated ac/dc, isolated dc/dc, and nonisolated dc/dc converter designs, and high density, high efficiency, and free/integrated compensation dc/dc converters for industrial and infrastructure applications. Laleh Najafizadeh (S 02 M 10) received the B.Sc. degree from the Isfahan University of Technology, Isfahan, Iran, the M.Sc. degree from the University of Alberta, Edmonton, AB, Canada, and the Ph.D. degree from the Georgia Institute of Technology, Atlanta, GA, USA. From 2010 to 2012, she was a Post-Doctoral Fellow with the National Institutes of Health, MD, USA. She is currently an Assistant Professor with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ. Her research interests broadly lie in the areas of microelectronics and signal processing. She has co-authored two book chapters and more than 80 peer-reviewed papers in premier journals and conference proceedings. She is a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems Society, and a Technical Committee Member of the IEEE BCTM. She was a recipient of a Texas Instruments Leadership Fellowship, a Delta Kappa Gamma World Fellowship, and competitive scholarships from the Alberta Ingenuity Fund, and the Alberta Informatics Circle of Research Excellence. Together with her students she received the Best Student Paper Award (Runner-Up) from the 2014 IEEE ISCAS.