A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences

Transcription

1 392 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017 A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences Yi Huang, Student Member, IEEE, and Laleh Najafizadeh, Member, IEEE Abstract Silicon germanium (SiGe) BiCMOS technology platform provides designers with a unique opportunity to have access to both Si Si and SiGe Si p-n junctions. By taking advantage of the coexistence of these two p-n junctions, this paper presents a new temperature compensation technique for SiGe reference circuits. The source of the appearance of curvature in the thermal characteristics of reference circuits is due to the fact that the temperaturedependent nonlinearities in the base emitter junction are not completely canceled across the temperature range of interest. Here, it is shown that under specific biasing conditions, the two Si Si and SiGe Si p-n junction voltages exhibit similar nonlinear temperature dependences. As such, a two-step temperature compensation technique is proposed: first, via a weighted subtraction of two currents, one proportional to the base emitter junction of Si BJT and the other proportional to the base emitter junction of SiGe heterojunction bipolar transistor, major nonlinear temperature-dependent terms are canceled; second, via the addition of a proportional to the absolute temperature current, the remaining linear temperature-dependent term is canceled. As a result of this two-step temperature compensation technique, an output voltage proportional to the difference of the bandgap voltages of Si and SiGe can be obtained. The proposed compensation technique is utilized to implement a precision reference circuit in IBM s SiGe BiCMOS 8HP technology. Measurement results verify the stability of the circuit against temperature variations. As the generated output voltage of the circuit is proportional to the difference of Si and SiGe bandgap voltages, the proposed circuit can be utilized to experimentally evaluate the Geinduced bandgap offset in a given SiGe technology platform. Index Terms Bandgap engineering, bandgap, bandgap reference circuits (BGRs), curvature compensation, reference circuits, silicon (Si) bipolar junction transistor (BJT), Silicon germanium (SiGe) heterojunction bipolar transistor (HBT). I. INTRODUCTION SILICON GERMANIUM (SiGe) BiCMOS technology, by offering high-speed, low-noise bandgap-engineered heterojunction bipolar transistors (HBTs) while maintaining Manuscript received October 12, 2016; revised November 28, 2016; accepted December 16, Date of publication January 5, 2017; date of current version January 20, This work was supported in part by the National Science Foundation under Award This paper was presented in part at the IEEE ISCAS The review of this paper was arranged by Editor G. Niu. (Corresponding author: Laleh Najafizadeh.) Y. Huang is with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854, USA, and also with Intersil Corporation, Bridgewater, NJ USA. L. Najafizadeh is with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ USA ( laleh.najafizadeh@rutgers.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED integration capability with conventional silicon (Si) CMOS [1], [2], has emerged as a promising technology platform for the realization of a wide variety of analog, RF, and mixed-signal circuits [3] [6]. High precision reference circuits are needed in these and virtually all electronic systems. A key requirement of reference circuits is to generate a robust voltage that is invariant against temperature variations. Any variations in the reference voltage will directly affect the performance of the overall system (for example, the resolution of data converters). The most commonly used topology for the realization of reference circuits is the bandgap reference (BGR) [7]. A BGR is designed to generate an output voltage that is referred to the bandgap energy of the background semiconductor material. In Si-based BGR circuits, the relation to the bandgap energy can be established through the base emitter voltage (V BE ). However, V BE also depends linearly ( T ) and nonlinearly ( [T ln(t )]) to the temperature. Traditionally, a proportional to the absolute temperature (PTAT) component is created to cancel the linear-dependent term of V BE, known as the complementary to the absolute temperature (CTAT) term [7]. The major problem with this approach is that the output of BGRs will still be dependent on the temperature (due to the existence of [T ln(t )] terms), limiting their application for high-performance electronics. To date, a variety of high-order temperature compensation solutions have been proposed to cancel the nonlinear temperature effects. In Si-based technologies, the majority of the solutions are based on expressing V BE by its Taylor series, and canceling the temperature dependencies to few degrees via various design techniques [7]. For example, in [8], the temperature dependence is canceled up to the second order via creating PT AT 2 components. In other approaches, nonlinear temperature-dependent components are generated and used to improve the temperature stability of reference circuits [9] [11]. Recently, a curvature compensation technique exploiting the bandgap narrowing effect was also proposed [12] to actively adjust the temperature characteristics of the BJT used in the circuit. Compared with the Si-based technology, in SiGe BiCMOS technology, a relatively smaller amount of work exists for reference circuits. A first-order temperature compensated BGR circuit was realized in [13] to demonstrate the feasibility of this technology for implementing BGRs. The influence of Ge grading on the temperature characteristics of SiGe-based reference circuits was investigated in [14] and [15], demonstrating that Ge grading can impact the accuracy of references. Temperature characteristics of the current gain (β) ofsige IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 393 HBTs were also exploited in [3] and [16] for high-order temperature compensation. Recently, HBTs operating in their inverse-mode region were also utilized for realizing reference circuits [17]. While, these circuits have been shown to operate reliably at temperatures as low as 1 K [16], their accuracy has not yet reached the level of their Si-based BGR counterparts. In this paper, a new compensation technique for SiGe reference circuits is presented to improve their thermal stability. The proposed technique is motivated by two key observations: the existence of two p-n junctions in SiGe technology platforms-the Si Si p-n junction [through vertical p-n-p (VPNP) devices] and the SiGe Si p-n junction (through n-p-n HBTs), and the dependence of temperature-induced nonlinearities of V BE on the temperature order of the collector current. As the source of the curvature appearance in the thermal characteristics of reference circuits is due to the fact that the temperature-dependent nonlinearities in V BE are not completely canceled across the temperature range of interest, the proposed approach utilizes both Si Si and SiGe Si junctions, which exhibit similar temperature-dependent nonlinearities, under specific biasing conditions, to perform temperature compensation. The initial compensation concept was first presented in [18]. Here, the extensive theoretical discussions are presented, and the experimental results are provided. Furthermore, it is shown that the proposed reference circuit generates an output voltage that is related to the difference in the bandgap voltages of Si and SiGe. As such, it can also be utilized to experimentally estimate the Ge-induced bandgap offset in a given SiGe technology. The rest of this paper is organized as follows. In Section II, the proposed compensation technique is presented. The design of a current-mode reference circuit employing the proposed compensation technique is described in Section III. Experimental results are provided in Section IV, followed by discussions about the proposed technique in Section V. Finally, this paper is concluded in Section VI. II. PROPOSED COMPENSATION TECHNIQUE In a typical SiGe BiCMOS technology platform, the designer has access to SiGe n-p-n HBTs as well as substrateisolated Si VPNP transistors [19]. To describe the proposed compensation technique, we first review the temperature characteristics of the base emitter junction in Si BJTs and SiGe HBTs. If a Si BJT transistor is biased such that its collector current (I C,BJT ) follows: I C,BJT (T ) = I C0,BJT ( T ) θbjt (1) where T and are the absolute and reference temperatures in kelvin, respectively, I C0,BJT is the collector current at, and θ BJT represents the order of the temperature dependency of the collector current, its base emitter voltage (V BE,BJT ) can be described as [20] V BE,BJT (T ) = V G0,Si [V G0,Si V BE0BJT ] T kt ( ) T q (η θ BJT) ln (2) Fig. 1. Energy band diagram for the Si BJT and the SiGe HBT (after [2]). where V G0,Si is the extrapolated bandgap voltage of Si at 0 K (V G0,Si = (1/q)[E g0 E app gb ], with E g0 and E app gb being the bandgap energy of Si under low doping and in the presence of heavy doping, respectively, and q being the electron charge), V BE0BJT is the base emitter voltage at, k is the Boltzmann constant, and η is a positive constant [21]. Reordering the terms in (2), V BE,BJT (T ) can be rewritten as (3) as shown at the bottom of the next page, highlighting its two temperaturedependent terms: the linear term ( T ) and the nonlinear term ( [T ln(t )]). In the case of SiGe HBT, the energy band diagram of a graded-base SiGe HBT is shown in Fig. 1 and is compared with that of the BJT [2], [22]. The introduction of compositionally graded Ge in the base (shown by the dashed lines) results in a finite band offset at the emitter base junction ( E g,ge0 ) and a larger band offset at the collector base junction ( E g,ge_wb ), compared with its Si counterpart. The Ge grading ( E g,ge(grade) ) is expressed as E g,ge(grade) = E g,ge_0 E g,ge_wb. If the SiGe HBT is biased such that its collector current (I C,HBT ) follows: I C,HBT (T ) = I C0,HBT ( T ) θhbt (4) where I C0,HBT is the collector current at and θ HBT denotes the order of the temperature dependence of the collector current, and the temperature characteristics of its base emitter voltage (V BE,HBT ) is expressed as [2] V BE,HBT (T ) = V G0,SiGe [V G0,SiGe V BE0HBT ] T kt ( ) T q (l θ HBT) ln ( ) kt q ln 1 exp Eg,Ge(grade) 0 k ( ) Eg,Ge(grade) 1 exp kt { ( )} kt q ln T0 E g,ge(grade). (5) T E g,ge(grade)0 In (5), V G0,SiGe is the extrapolated bandgap voltage of SiGe at 0K, V BE0HBT and E g,ge(grade)0 are the base emitter voltage and the Ge grading-induced bandgap offset at, respectively, and l is a positive constant. Assuming the temperature dependence of Ge grading ( E g,ge(grade) ) is negligible [2], rearranging the terms in (5) results in (6), as shown at the bottom of the next page, where the linear and nonlinear

3 394 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017 Fig. 2. Simulated deviation from linearity in V BE,BJT and V BE,HBT for different biasing conditions. temperature-dependent terms have been highlighted. Since the Ge-induced bandgap offset is typically around 100 mev [1], the second nonlinear term in (6) can be neglected over conventional temperature ranges of interest (e.g., commercial, industrial, or military). Neglecting the second nonlinear term in (6), and comparing (3) and (6), one can see that both V BE,BJT and V BE,HBT exhibit similar temperature-dependent terms: T and [T ln(t )]. The presence of similar temperature-dependent nonlinear term in both V BE,BJT and V BE,HBT suggests that through proper biasing (θ BJT and θ HBT ) of the two transistors and appropriate weighted subtraction of the two junction voltages, the nonlinear term [T ln(t )] can be canceled. Fig. 2 shows the deviation from linearity for the base emitter voltage of a Si BJT and a SiGe HBT (with identical emitter areas) versus temperature for two different biasing conditions (collector current being temperature independent, and collector current being PTAT), obtained through simulations. The deviation from linearity was obtained by drawing a line between V BE s at the two temperature ends, and then subtracting this line from simulated data [14]. The figure indicates that the deviation from linearity in both transistors decreases as the order of the temperature dependence of the collector current increases. In addition, one can see that the deviation from linearity of the BJT is closest to that of HBT if the BJT is biased with temperature-independent collector current and the HBT is biased with a PTAT collector current. The expression for the weighted subtraction of the two voltages is described in (7) as shown at the bottom of this page, where A 1 and A 2 represent the coefficients of the linear term ( T ) in (3) and (6), respectively. Note that due to the inclusion of the graded Ge into the base of SiGe HBTs, V G0,SiGe is a smaller value than V G0,Si. We now summarize the proposed two-step compensation technique to minimize the temperature dependence of the SiGe reference circuit. Step 1: The temperature characteristics of the biasing currents (θ BJT and θ HBT ) and the weighted subtraction coefficients α 1 and α 2 are set, such that the coefficient of the nonlinear term [T ln(t )] is set to zero, that is α 1 = l θ HBT 1. (8) α 2 η θ BJT Equation (8) depends on parameters η and l, which are typically between 3 and 4 [14]. As a rough estimate, if we assume η = l, to keep the ratio in (8) a positive value, the order of the temperature dependence of the I C,HBT (i.e., θ HBT ) needs to be set to be smaller by one unit than that of I C,BJT (i.e., θ BJT ). For example, if the collector current of the Si BJT is designed to be PTAT (i.e., θ BJT = 1 in (1)), then I C,HBT needs to be temperature independent [i.e., θ HBT = 0in(4)]. A temperature-independent current, to the first order, can be generated through the summation of a PTAT current and a CTAT current. Alternatively, the BJT can be biased with a PTAT 2 current (i.e., θ BJT = 2), while the HBT is biased with a PTAT current (i.e., θ HBT = 1). [ VG0,Si V BE0BJT V BE,BJT (T ) = V G0,Si k ] q ln() (η θ BJT) linear coefficient (A 1 ) [ k T ] q (η θ BJT) [T ln(t )]. nonlinear [ VG0,SiGe V V BE,HBT (T ) = V G0,SiGe BE0HBT k ( (l θ q ln T0 HBT 1) [ ( )] E )] g,ge(grade) Eg,Ge(grade)0 1 exp T E g,ge(grade)0 k [ k ] q (l θ HBT 1) [T ln(t )] nonlinear 1 [ kt + linear coefficient (A 2 ) ( ( q ln 1 exp E ))] g,ge(grade) kt nonlinear 2 α 1 V BE,BJT (T ) α 2 V BE,HBT (T ) =[α 1 V G0,Si α 2 V G0,SiGe ] [α 1 A 1 α 2 A 2 ] T weighted difference weighted difference of bandgap voltages of linear terms k q [α 1(η θ BJT ) α 2 (l θ HBT 1)] [T ln(t )] (7) weighted difference of nonlinear terms (3) (6)

4 HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 395 Step 2: In the second step, the linear term in (7) will be canceled. This can be achieved through the addition of a PTAT component, such that the linear coefficient of the PTAT current (α 3 )issetso α 3 = α 1 A 1 α 2 A 2. (9) Once the temperature-dependent parameters in (7) are canceled, a temperature-independent output voltage related to the weighted subtraction of the two bandgap voltages of Si and SiGe is obtained. Note that, in this step, for the complete cancellation to be realizable through the addition of the PTAT component, one has to make sure that the coefficient [α 1 A 1 α 2 A 2 ] in (7) remains positive after the direct cancellation of the nonlinear terms. Using (8), and denoting C 1 = (V G0,Si V BE0BJT )/, C 2 = (V G0,SiGe V BE0HBT )/, and C 3 = ( E g,ge(grade) / E g,ge(grade)0 )[1 exp ( E g,ge(grade)0 /(k ) ) ] in (6), [α 1 A 1 α 2 A 2 ] can be expressed as [ [α 1 A 1 α 2 A 2 ]=α 1 C 1 η θ ] BJT l θ HBT 1 C 2 + k q α η θ BJT 1 l θ HBT 1 ln(c 3). (10) The choice of emitter area for Si BJT and SiGe HBT and their collector currents (defining V BE0BJT and V BE0HBT ) should then be made in a way that (10) remains a positive value. III. DESIGN EXAMPLE In this section, the design of a current-mode reference circuit utilizing the proposed temperature compensation technique is described. The circuit consists of four main circuit blocks: the Si-based current generator, the SiGe-based current generator, the PTAT current generator, and the V REF generator. Without loss of generality, for the realization of step 1 of the proposed solution, in this design, the BJT is biased with a PTAT current (i.e., θ BJT = 1) and the HBT is biased with a temperature-independent current (i.e., θ HBT 0). A. Si-Based Current Generator The schematic of the Si-based current generator is shown on the left side of Fig. 3. A VPNP transistor (Q 1 )isbiased by a PTAT current I PTAT1. The PTAT current generator circuit will be discussed in Section III-C. The base emitter voltage of Q 1 falls across resistor R 1, generating current I 1 related to V EB of Q 1 as I 1 (T ) = V EB,Q 1 (T ) = I VBE,BJT (T ) (10) R 1 where V EB,Q1 (T ) follows (3) with θ BJT = 1. Transistors M 1 and M 2 and M 3 and M 4 form a cascode current mirror, and M 5 is the feedback transistor [21]. Capacitor C 1 is added in the circuit to stabilize the loop. B. SiGe-Based Current Generator The schematic of the SiGe-based current generator circuit is shown on the right side of Fig. 3. The operation of this circuit is similar to that of the Si-based current generator discussed above, except that the HBT (Q 2 ) is now biased Fig. 3. Schematic of the Si-based and SiGe-based current generator circuits. Fig. 4. Schematic of the PTAT current generator circuits. with a current (I REF,1st_order ) that is temperature independent to the first order (i.e., θ HBT 0). This current is generated through the weighted addition of the PTAT current and the current generated through the Si-based current generator (I 1 ), which decreases as the temperature increases. Proper weights (K c and K p ) are realized through the aspect ratio of the transistors used in the current mirrors. A sink to source current converter, consisting of transistors M SS1 -M SS6,isusedforthe current conversion. The base emitter voltage of HBT Q 2 falls across resistor R 2, generating current I 2 as I 2 (T ) = V BE,Q 2 (T ) = I VBE,HBT (T ) (11) R 2 where V BE,Q2 (T ) follows (6) with θ HBT 0. C. PTAT Current Generator The schematic of the PTAT current generator with its startup circuit [23] (consisting of transistors M S1 M S4 )isshownin Fig. 4. The core of the PTAT current generator (right side of Fig. 4) consists of MOSFET transistors M 11 M 14,HBTs Q 3 and Q 4, and the resistor R 3. The PTAT current circuit can also be made using BJTs. We have used HBTs, since they offer significantly higher current gain compared with BJTs, to minimize the influence of base currents. In this circuit, a folded-cascode op-amp with large dc gain [11] is designed to enforce identical voltage levels at the inverting and noninverting input terminals (nodes A and B), ensuring that the currents I 3 and I 4 are identical. The emitter area of transistor Q 3 is designed to be eight times larger than that of Q 4. The difference between the base emitter voltages of the

5 396 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017 Fig. 5. Left: schematic of the V REF generator circuit. Right: die microphotograph of the circuit. Fig. 6. Simulation results for I VBE,BJT and I VBE,HBT (left), and I PTAT, and the weighted subtraction of I VBE,BJT and I VBE,HBT (right). two transistors falls across the resistor R 3, generating PTAT currents I 3 and I 4 following [15]: I 3 (T ) = V BE,Q4(T ) V BE,Q3 (T ) R 3 = k ln(n) T = I PTAT (T ) qr 3 (12) where n represents the emitter area ratio of transistors Q 3 and Q 4 (here n = 8). D. V REF Generator After the generation of the Si-based, the SiGe-based, and the PTAT currents, a circuit needs to be implemented to properly add the PTAT current to the weighted subtraction of the Si-based and SiGe-based currents, so a temperatureindependent output voltage is generated. As discussed, the nonlinear temperature-dependent components are canceled through the weighted subtraction of Si-based and SiGe-based currents, and the remaining linear temperature-dependent component is canceled through the addition of the PTAT current. Fig. 5 shows the simplified schematic of the V REF generator circuit. Mirrored versions of the Si-based current and the PTAT current will be added properly together at node V REF, while a portion related to the SiGe-based current will be taken away to implement the weighted subtraction step. As such, V REF (T ) is expressed as (13) as shown at the bottom of this page, where K 1, K 2,andK 3 are determined by the aspect ratio of the corresponding mirroring transistors. We now proceed with finding the required design equations, such that V REF becomes a temperature stable voltage. Following (8), to cancel the nonlinear temperature-dependent component, we will have: α 1 = K 1 R 2 = l θ HBT 1. (14) α 2 K 2 R 1 η θ BJT Since in this design, θ HBT 0andθ BJT = 1, and assuming l η, (14) simplifies to K 1 = R 1. (15) K 2 R 2 To cancel the linear temperature-dependent term, α 3 in (14) should be set, such that (9) is satisfied. Assuming θ BJT = 1, θ HBT 0, and l η, the equation for canceling the linear term is obtained as (16) as shown at the bottom of this page. Once conditions (15) and (16) are satisfied, the output voltage, related to the difference in the bandgap voltages of Si and SiGe junctions, is obtained as R 4 V REF = K 1 (V G0,Si V G0,SiGe ). (17) R 1 These theoretically driven equations can provide guidance and insight to designers on how to select circuit design parameters (resistor values, current mirror ratios, and emitter area ratios) to achieve an optimum temperature coefficient (TC). Fig. 6 shows the simulations results for I PTAT, I VBE,BJT and I VBE,HBT, and their weighted subtraction, in this design, respectively. IV. MEASUREMENT RESULTS The proposed reference circuit was fabricated in IBM s SiGe 8HP BiCMOS technology. P + polysilicon resistors were used for all resistors, since their TC is very small. Commoncentroid layout technique was employed for the realization of the current mirrors to minimize the effect of mismatch. The die microphotograph is shown in Fig. 5. The die was mounted in a 28 pin ceramic DIP package and wirebonded. The package was inserted into a zero-insertion-force socket soldered on a printed circuit board. Temperature characterization was performed using a ThermoJet ES precision temperature cycling system from SP Scientific [24]. To minimize the loading effects of the measurement equipment, unity gain buffers were also incorporated. V REF (T ) = R 4 [K 1 I VBE,BJT (T ) K 2 I VBE,HBT (T ) + K 3 I PTAT (T )] (13) [ ] [ ] [ ] R 4 R 4 R 4 k ln(n) = K 1 V EB,BJT (T ) K 2 V BE,HBT (T ) + K 3 T R 1 R 2 qr 3 α 1 α 2 α 3 K 3 = qr [ 3 VG0,Si V G0,SiGe V BE0BJT + V BE0HBT K 1 k ln(n)r 2 + k ( [ q ln Eg,Ge(grade) 1 exp E g,ge(grade)0 ( Eg,Ge(grade)0 k )])] (16)

6 HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 397 TABLE I PERFORMANCE COMPARISON OF THE PROPOSED REFERENCE CIRCUIT WITH PRIOR SiGe-BASED BGRs Fig. 7. Measured output voltage of the proposed reference circuit as a function of temperature. Fig. 7 shows the measured results for V REF of three samples from different wafers as a function of temperature. Operating with a power supply of 3 V, unit 1 provides the best overall thermal performance with a TC of 17.0 ppm/ C across ( 40 : 70) C. The averaged TC for all measured samples across ( 40 : 70) Cis24.9 ppm/ C. Incorporating trimming networks would further improve the TC. One important performance measure for BGR circuits is the power supply rejection ratio (PSRR), which is indicative of how well they can reject the power supply noise. PSRR of the proposed circuit was measured at 70 C, 30 C, 0 Cand 20 C. As shown in Fig. 8, at all temperature points, the circuit shows PSRR less than 40 db at 10 Hz and less than 30 db up to 100 khz. While this PSRR is comparable with that of voltage references in [13] and [25], it can be further improved by employing PSRR enhancement techniques such as the one proposed in [26]. Table I compares the performance of the proposed circuit with some of previously designed SiGe-based BGR circuits. While a direct comparison is not possible (due to differences in technology, design, and reported temperature ranges for TC), the proposed reference circuit offers the smallest TC for the best case and comparable TC for the average across three units, against temperature variations, verifying the effectiveness of the proposed compensation technique. V. DISCUSSION The proposed temperature compensation technique, by taking advantage of the availability of two types of p-n junctions, offers a new promising approach for designing highly stable reference circuits in SiGe BiCMOS technology platforms. To further evaluate the robustness of the circuit against process and mismatch variations, Monte Carlo Fig. 8. Measured PSRR of the proposed reference circuit at four different temperatures. Fig. 9. Distributions of V REF, from Monte Carlo simulation of 1000 runs, left figure for mismatch only, and right figure for mismatch and process variation. simulations of 1000 runs as well as corner simulations were performed. Fig. 9 shows the result of Monte Carlo simulations at 25 C. The coefficient of variation (σ/μ) [27] for V REF is obtained as 2.10% when mismatch is considered, and 2.83% when both mismatch and process variations are considered. Major sources of mismatch in reference circuits include mismatch in current mirrors, transistors, and resistors. Mismatch in transistors and resistors was minimized using layout techniques for transistors, and realizing resistors with p + polysilicon, which offers small temperature and voltage coefficients, respectively. The observed variations could be due to mismatch in current mirrors (which have also been identified as the dominant error in BGRs [28]). The coefficient of variation and the TC can be further improved by including trimming networks for R 1 -R 3, specifically for R 3, since the PTAT current plays a major role in generating I PTAT, I VBE,BJT, and I VBE,HBT. Table II summarizes the simulation results for MOS transistors corners. TC shows larger variations across process corners when T > 85 C is considered (e.g., military temperature range). This observation could be due to the fact

7 398 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017 TABLE II TC AT TRANSISTOR CORNERS that at high temperatures, the PTAT current dominates the overall behavior, due to changes in the op-amp loop gain and the offset voltage. While the measurement results exhibited small TC verifying the effectiveness of the proposed approach in realizing precise SiGe references, the output voltage still revealed some levels of temperature sensitivity. Possible reasons for the observed variations include the following. First, in the design example, it was considered that θ HBT 0 to the first order. In practice, an exact θ HBT = 0 is not achieved and some degree of temperature variability will exist. Deviation from θ HBT = 0 will introduce temperature sensitivity. Alternative solutions can be considered (e.g., θ HBT = 1and θ BJT = 2) to realize the proposed compensation approach. Second, post-fabrication variations, measurement setup (e.g., the mechanical stress of the ceramic DIP packages [29]), and current mirror mismatch (as discussed above), could also have introduced variations during the measurement. Resistive trimming networks can be employed to minimize such variations. An interesting aspect of the proposed compensation technique is that this circuit generates an output voltage that is related to the difference of the bandgap voltages of Si and SiGe. As such, it can be utilized to experimentally estimate the Ge-induced bandgap offset for different Ge grading profiles. In the circuit presented in this paper, the resistors R 1 and R 2 in Fig. 3 were set to 25.7 k, resistor R 4 in Fig. 5 was set to k, and the mirroring ratios K 1 and K 2 were both set to 1. Plugging these numbers and measured V REF into (17) results in the bandgap voltage difference of 87.2 mv. VI. CONCLUSION In this paper, a new temperature compensation technique based on the weighted difference of Si Si and SiGe Si p-n junction voltages for SiGe reference circuits was presented. Unlike regular BGR circuits, in which the generated output voltage is referred to the bandgap energy of the background semiconductor material, the circuit employing the proposed technique can generate an output that is related to the difference in the bandgap voltages of Si and SiGe. As such, it can be used to experimentally evaluate the Geinduced bandgap offset in a given SiGe technology. ACKNOWLEDGMENT The authors would like to thank Prof. J. Cressler and his group at the Georgia Institute of Technology for their support for the fabrication of the chips. REFERENCES [1] D. L. Harame et al., Si/SiGe epitaxial-base transistors. II. Process integration and analog applications, IEEE Trans. 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8 HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 399 [26] S. K. Hoon, J. Chen, and F. Maloberti, An improved bandgap reference with high power supply rejection, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2002, pp [27] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, 1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs, IEEE J. Solid-State Circuits, vol. 48, no. 6, pp , Jun [28] V. Gupta and A. Rincon-Mora, Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications, in Proc. IEEE Midwest Symp. Circuits Syst., Aug. 2002, pp [29] F. Fruett, G. C. M. Meijer, and A. Bakker, Minimization of the mechanical-stress-induced inaccuracy in bandgap voltage references, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp , Jul Laleh Najafizadeh (S 02 M 10) received the B.Sc. degree from the Isfahan University of Technology, Isfahan, Iran, the M.Sc. degree from the University of Alberta, Edmonton, AB, Canada, and the Ph.D. degree from the Georgia Institute of Technology, Atlanta, GA, USA, all in electrical engineering. She is currently an Assistant Professor with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ, USA. Yi Huang (S 14) received the B.Sc. degree in electronic information engineering from the Beijing University of Aeronautics and Astronautics, Beijing, China, and the M.Sc. degree in electrical engineering from Stony Brook University, Stony Brook, NY, USA. He is currently pursuing the Ph.D. degree with Rutgers University, Piscataway, NJ, USA. He has been with Intersil Corporation, Bridgewater, NJ, USA, since 2011.