PAPER A CMOS Temperature Sensor Circuit

Transcription

1 IEICE TRANS. ELECTRON., VOL.E90 C, NO.4 APRIL PAPER A CMOS Temperature Sensor Circuit Takashi OHZONE a), Member, Tatsuaki SADAMOTO, Student Member, Takayuki MORISHITA, Kiyotaka KOMOKU, Toshihiro MATSUDA, and Hideyuki IWATA, Members SUMMARY A supply voltage (V DD ) independent temperature sensor circuit, which can be realized by the optimum combination of three current modes of n-mosfets including the subthreshold current using the feedback scheme from the temperature dependent voltage (V TD ) output to the gates of three n-mosfets, was proposed and fabricated by a standard 1.2 µm n-well CMOS process. The circuit consists of only 17 MOS- FETs without high resistors resulting in a small die area of 0.18 mm 2.The temperature coefficient TC of the sensor circuit can be controlled by the channel length ratio L 4 /L 3 of two n-mosfets. The average temperature sensor voltage V TS and its typical TC are 1.77 V at V DD = 5.0V(20 C)and 5.1 mv/ C for V DD = 5.0 ± 1.0 V in the temperature range of C in case of L 4 /L 3 = 9, respectively. key words: CMOS, temperature sensor, temperature dependent voltage, subthreshold current 1. Introduction A supply-voltage independent on-chip analog-output temperature sensor is one of the key elemental subcircuits for analog CMOS integrated circuits as a temperature sensing unit in a thermally sensitive systems such as a microprocessor [1], a fan control unit, as well as cold-junction thermocouple compensation and medical equipment. Although a current-output temperature sensor with frequency-output [2] and a time-to-digital-converter-based temperature sensor [3] without the bandgap reference and/or the A/D converter have been recently proposed, the conventional CMOS smart temperature sensors contain the three basic parts; the temperature sensor, the voltage reference and the A/D converter [4]. Among the three basic circuits, the temperature sensor is the key circuit to realize high performance smart temperature sensors. The temperature sensors are conventionally designed using the difference between two base-emitter voltages of two identical transistors carrying different collector currents, which realize the proportional-to-absolute-temperature (PTAT) sensor [5] [8]. The PTAT sensor, in which the transistors can also be replaced by diodes [9], can generate a temperature dependent voltage V TD with a temperature coefficient TC. Manuscript received August 28, Manuscript revised December 13, The authors are with the Department of Communication Engineering, Okayama Prefectural University, Soja-shi, Japan. The authors are with the Department of Information Systems Engineering, Toyama Prefectural University, Imizu-shi, Japan. a) ohzone@c.oka-pu.ac.jp DOI: /ietele/e90 c However, high resistors have been conventionally used in the temperature sensor circuits to realize low power consumption [10], though the high resistors occupy large die area resulting in high chip cost. Consequently, it needs to develop a low current V TD generator without using high resistors to obtain a high-cost-performance temperature sensor. In this paper, a simple CMOS temperature sensor with analog output voltage was designed and fabricated for a low power temperature sensor. The temperature sensor was developed by adding one n-mosfet to the V TD generator based on the MOSFET threshold-voltage reference fabricated by a standard n-well CMOS process [11], [12], and composes only 17 MOSFETs including the startup circuit resulting in small die area and a good supply-voltage stability. 2. Temperature Sensor Circuit Figure 1 shows the proposed temperature sensor circuit designed by the optimum combination of three kinds of MOS- FET s current operation modes [i.e., the subthreshold currents (I S 1 and I S 2 flowing in N1 and N2 n-mosfets under V T > (V GS 1 and V GS 2 ), where V GS 1 and V GS 2 are the voltages between the gate and the source of N1 and N2, re- Fig. 1 A schematic of the proposed temperature sensor circuit. Copyright c 2007 The Institute of Electronics, Information and Communication Engineers

2 896 IEICE TRANS. ELECTRON., VOL.E90 C, NO.4 APRIL 2007 spectively), the linear current (I L3 flowing in N3 n-mosfet biased under V D3 V TD V T,whereV D3 is the drain voltage of N3), and the saturation current (I SAT4 flowing in N4 n-mosfet biased under V D4 > V TD V T,whereV D4 is the drain voltage of N4)], a feedback scheme from the V TD output to gates of N3 N5 n-mosfets, and the current mirror circuits composed of P1 P6 p-mosfets to satisfy I S 1 = I S 2 = I L3 = I SAT4 [11], [12]. N5 n-mosfet is inserted between P5 and N2 to keep each voltage between the drain and the source of N1 and N2 nearly equal to sufficiently satisfy I S 1 = I S 2. The gate-drain and the substrate-source connected (hereafter called the S=S type) n-mosfet M1 is inserted between the V TD node and the drain of N4 as shown by the rectangular dashed line in Fig. 1. The output voltage of the temperature sensor V TS is obtained at the source voltage of M1. N6 N9 and P7 MOSFETs shown in Fig. 1 make the start-up circuit, which controls the V TD generation circuit when V DD is supplied. Each source voltage of N8 and N9 is supplied to N1/N2 gates and V TD node to give the start-up voltage, respectively. After the V DD reaches the operational voltage, at which point the temperature sensor circuit can start to operate, N8 and N9 turn off. The relations of the currents and the node voltages are given independently from M1 n-mosfet as follows. I S 1 = I s1 exp[(v GS 1 V T )/nv t ] (1) I S 2 = I s2 exp[(v GS 2 V T )/nv t ] (2) I L3 = K W 3 (V TD V T )V D3 L 3 (3) I SAT4 = 1 2 K W 4 (V TD V T ) 2 L 4 (4) V GS 1 = V GS 2 + V D3 (5) Where I s : the temperature independent I S current, V T :the threshold-voltage, n: the fitting factor for the subthreshold swing, V t : the thermal voltage (= kt/q), and K: the transconductance parameter. W 3 (W 4 )andl 3 (L 4 )arethe channel width and length of N3 (N4) n-mosfet, respectively. From Eqs. (1), (2) and (5), the V D3 is given by V D3 = nv t ln I s2 (6) I s1 From Eqs. (3) and (4) under the condition of W 3 = W 4 and I L3 = I SAT4,theV D3 voltage is also given by V D3 = 1 L 3 (V TD V T ) (7) 2 L 4 Where the change of L 4 /L 3 ratio was selected to control the V D3 voltage following the experimental results obtained in Ref. [12]. As V D3 values given by Eqs. (6) and (7) are equal, V TD becomes as follows. L 4 V TD = V T + 2nV t ln I s2 (8) L 3 I s1 The output voltage of the temperature sensor V TS Fig. 2 The calculated relations between V TS and its TC versus (L 4 /L 3 ) ratio for the S=S type M1 n-mosfet. is approximately given as V TS = V TD V T = 2nV t (L 4 /L 3 )ln(i s2 /I s1 ), because V TS is lowered from the V TD value by about V T due to the S=S type M1, which is the same n-mosfet as N1 and thus operates at the slightly lower gate voltage than V T under the subthreshold region. Substituting k/q = (V/K) and n = 1.6 for the typical n-mosfets in case of I s2 /I s1 = 8 [throughout of this paper, the I s2 /I s1 value is designed as 8, which is determined by the W 2 /W 1 ratio, where W 1 and W 2 are the channel widths of N1 and N2 n-mosfets, respectively, in case of the same channel length for both N1 and N2], V TS and its temperature coefficient TC can be finally given as a parameter of L 4 /L 3 ratio as follows: V TS = 2nV t L 4 L 3 ln I s2 I s1 = L 4 (V) att = 293 K(20 C) (9) L 3 TC= V TS T =2n k L 4 ln I s2 =0.573 L 4 (mv/ C) (10) q L 3 I s1 L 3 In the temperature sensor circuit, both V TS and its TC are independent from the V T variation, and are only determinedbythenvalue and the MOSFETs dimensional ratios; (L 4 /L 3 )and(i s2 /I s1 ) = (W 2 /W 1 ). To obtain V TS = 1.5Vat T = 20 C, L 4 /L 3 should be 9 resulting in the V TS TC of 5.1 mv/ C. Consequently, V TS = 1.5 ± 0.4 V is obtained for the temperature range of 20 ± 80 C. The relations between V TS at 20 C and its TC versus L 4 /L 3 ratio calculated from Eqs. (9) and (10) are given in Fig. 2, where +V TS and V TS are the maximum and the minimum voltages at 100 C and 60 C, respectively. 3. Simulation Results Figure 3 shows an example of the simulated results for the supply voltage V DD dependence of V TD and V TS voltages at L 4 /L 3 = 9 at the temperature range of 60, 20 and 100 C using HSPICE program. The constant V TD and V TS outputs of about 2.6 and 1.8 V at 20 C, and the V TS TC of around 5.8 mv/ C are obtained for V DD 4.0V.TheL 4 /L 3 ratio dependences of V TD and V TS at V DD = 5.0V (20 C), and the

3 OHZONE et al.: A CMOS TEMPERATURE SENSOR CIRCUIT 897 (a) Fig. 3 V TD and V TS versus V DD characteristics at L 4 /L 3 = 9 simulated by HSPICE at 60, 20 and 100 C for the S=S type M1 n-mosfet. (b) Fig. 5 Photomicrographs of (a) the main temperature sensor circuit, and (b) the N4 n-mosfets array to control the L 4 /L 3 ratios. Fig. 4 The simulated V TD, V TS at V DD = 5.0 V (20 C) and V TS TC at V DD = 5.0 V versus L 4 /L 3 ratio characteristics in case of the S=S type M1 n-mosfet. V TS TC at V DD = 5.0VforL 4 /L 3 = 3 10 in the temperature range of 20 ± 80 C are given in Fig. 4. Though the simulated V TS and its TC versus L 4 /L 3 ratio characteristics show a little nonlinearity in comparison with the straight lines given by the simple theory as shown in Fig. 2, the overall characteristics are in good agreements with the simple theory. The nonlinearity may be affected by the short channel effects in N1, N2 and M1 which have the shortest channel length for the 1.2 µm n-well CMOS process. 4. Experimental Results and Discussion The proposed CMOS temperature sensor circuit was fabricated using the 1.2 µm n-well CMOS process. The (I s2 /I s1 ) ratio given in Eqs. (9) and (10) is set as 8 by designing W 2 /W 1 = 8. The channel length L 3 and the channel width of N3 n-mosfet are designed as 15 µm and 20 µm, respectively. Figure 5 shows photomicrographs of (a) the main temperature sensor circuit without an N4 n-mosfet, and (b) an array of 12 kinds of N4 n-mosfets for selecting the optimum L 4 /L 3 ratio to obtain a suitable TC value. The N4 channel lengths L 4 are varied from 30 to 180 µm by15µm step while the channel widths are fixed at 20 µm, which is the same channel width of N3. Consequently, L 4 /L 3 ratios can be varied from 2 to 12 by selecting each N4 drain terminal, while all of gates and sources are connected to the V TD node and GND, respectively. The die areas of the temperature sensor circuit and the N4 n-mosfets array are 0.18 and 0.19 mm 2, respectively. Typical V TD and V TS versus V DD characteristics at L 4 /L 3 = 9for 60, 20 and 100 C in case of the S=S type and the substrate-gnd connected (called the S=G type) M1 are shown in Fig. 6(a). The S=S type M1 fabricated on the same chip with the main temperature sensor circuit could not be used for our experiments, because the n-well CMOS process has the common p-type silicon substrate (which is conventionally connected to the common GND) for all n- MOSFETs resulting automatically in the S=G type M1 on the same chip. Consequently, the S=S type M1 n-mosfet fabricated on another chip is inserted between P6 and N4 of the main temperature sensor circuit in our experiments. Superior temperature dependent constant V TD and V TS characteristics are obtained for V DD 4.0 V as expected by the simulation results given in Fig. 3. Figure 6(a) also gives the experimental results using the S=G type M1 fabricated on the same chip with the main circuit. Though V TD (S=G) is nearly the same as V TD (S=S), V TS (S=G) becomes lower by V T (i.e., V TS (S=G) = V TS (S=S) V T similarly to Eq. (9), where V T is the V T increase due to the substrate bias effect of the S=G type M1). Furthermore, the V TS (S=G) difference between those at 60 and 100 C is lower than those of V TS (S=S), because the V TS (S=G) difference becomes lower

4 898 IEICE TRANS. ELECTRON., VOL.E90 C, NO.4 APRIL 2007 (a) (a) (b) Fig. 6 (a) A typical V DD dependence of V TD and V TS at L 4 /L 3 = 9forthe S=S orthes=g type M1 n-mosfet at 60, 20 and 100 C. (b) The L 4 /L 3 ratio dependent V TS versus V DD characteristics at 100 C for the S=S type M1. (b) Fig. 7 The temperature dependent (a) V TS at V DD = 5.0 V and (b) V TS difference V TS,where V T = V TS (T) V TS (20 C), for L 4 /L 3 ratios from 2 to 12. by V T / T, which has the positive value, resulting in the lower TC than that in the case of V TS (S=S). Consequently, it is concluded that the substrate of M1 n-mosfet should be connected to its source to realize both higher V TS and TC for the proposed temperature sensor circuit. Figure 6(b) gives the L 4 /L 3 ratio dependent V TS (S=S) versus V DD characteristics at 100 C to know the lowest allowable V DD for the stable operation against the V DD decrease, because the V TS voltage becomes its maximum at 100 C. For the stable operation down to V DD = 4.0V,L 4 /L 3 ratio should be lower than 9. Figures 7(a) and (b) show the temperature dependent V TS (S=S) at V DD = 5.0 V and the voltage difference V TS, where V TS = V TS (T) V TS (20 C), for various L 4 /L 3 ratios, respectively. Both V TS and V TS increase as the L 4 /L 3 ratio becomes larger as expected from the simple theory given by Eqs. (9) and (10), respectively. The relatively good linear characteristics for both V TS and V TS are obtained for all L 4 /L 3 ratios. Figure 8(a) gives V TD and V TS versus L 4 /L 3 ratio characteristics. The V TD (S=S or G) voltages for the S=Sandthe S=G type M1 are almost identical. However, V TS (S=G) is apparently lower than V TS (S=S) due to the substrate bias effect of V T in M1. The approximate fitting curves are given as V TD (S=S)= 0.004(L 4 /L 3 ) (L 4 /L 3 ) (V), V TS (S=S)= 0.004(L 4 /L 3 ) (L 4 /L 3 ) (V), and V TS (S=G)= 0.004(L 4 /L 3 ) (L 4 /L 3 ) (V). Although the small quadratic terms are included for all equations similar to the simulation results given in Fig. 4, the L 4 /L 3 dependent linear coefficients 0.17 and 0.16 for V TD (S=S) and V TS (S=S), respectively, are similar to the theoretically estimated value of from Eqs. (8) and (9). The linear coefficient of V TS (S=G) is about 0.05 smaller than that of V TS (S=S) due to the substrate effect of V T. The intercept of the V TD curve ( 0.70 V) corresponds to V T 0.75 V of the M1 n-mosfet as expected from Eq. (8). However, the slightly lower V TD, which is equal to the gate-source voltage of M1, in comparison with V T indicates that M1 operates in the subthreshold region at V lower gate voltage than V T. Figure 8(b) shows the L 4 /L 3 dependent TC for V TS (S=S), V TS (S=G) and V TD (S=S or G). The V TD TC values for the S=S and the S=G types are almost identical and those slopes are about 0.58(L 4 /L 3 )mv/ C. The TC of V TS (S=S) is given by 0.57(L 4 /L 3 )mv/ C, which is nearly equal to the theoretically estimated 0.573(L 4 /L 3 )mv/ C. The TC in case of V TS (S=G) is 0.44(L 4 /L 3 )mv/ C and 0.13 mv/ C lower than that of V TS (S=S), which is nearly equal to the V T temper-

5 OHZONE et al.: A CMOS TEMPERATURE SENSOR CIRCUIT 899 (a) Fig. 10 V TS versus temperature characteristics for L 4 /L 3 = 9andV DD = 4.0/4.5/5.0/5.5/6.0 V. (b) Fig. 8 (a) V TD and V TS versus L 4 /L 3 ratio characteristics at V DD = 5.0 V (20 C) for the S=S andthes=g type M1. (b) L 4 /L 3 dependent TC for V TS (S=S), V TS (S=G) and V TD (S=S org)forv DD = 5.0 V and C. Fig. 11 The fluctuations of V TS at V DD = 4.0/4.5/5.0/5.5/6.0 V (20 C), and TC in the temperature range from 20 to 100 C for five samples. Fig. 9 The temperature dependence of V TS in case of the S=S type M1 for V DD = 4.0/4.5/5.0/5.5/6.0 V and L 4 /L 3 = 8/9/10. ature coefficient V T / T = 0.15 mv/ C for the M1 n- MOSFET. All data given in Fig. 8 are well estimated from the estimations given by Eqs. (8) (10), which means that the basic operation mechanism of the temperature sensor circuit is quite simple and its characteristics can be easily designed by the simple theory. Figure 9 shows the temperature dependence of V TS for the S=S type M1 at V DD = 4.0/4.5/5.0/5.5/6.0V and L 4 /L 3 = 8/9/10. All V DD dependent V TS data for the same L 4 /L 3 ratio are aligned on each single line in the volt- age range of V except for the case of L 4 /L 3 = 10 at 4.0 V given by the dashed line, from which the maximum available L 4 /L 3 ratio to obtain the maximum TC for the temperature sensor circuit is 9, which is the same conclusion as estimated from Fig. 6(b). Figure 10 gives V TS versus temperature characteristics for L 4 /L 3 = 9andV DD = 4.0/4.5/5.0/5.5/6.0 V, while all curves are aligned on the single line. The approximate linear line from 20 to 100 C gives the TC = 5.1 mv/ C for the typical sample. As the linearity departs from the temperature below 20 C, it is difficult to sense the correct temperature less than 20 C in our circuit. Figure 11 shows the fluctuations of V TS at V DD = 4.0/4.5/5.0/5.5/6.0V(20 C),and its TC in the temperature range from 20 to 100 C for five samples. The average V TS at V DD = 5.0V(20 C)andTC are V and 5.07 mv/ C, respectively. Those V TS and TC values are a little different from 1.5 V and 5.1 mv/ C estimated from Eqs. (9) and (10), respectively. The smaller V TS may be caused the M1 n-mosfet, because its equivalent V T given in Eq. (8) is dependent on the drain current flowing in M1 (i.e., dependent on the channel length L and width W of M1). It was experimentally proved using another M1 with smaller W/L ratio that the equivalent V T becomes higher re-

6 900 IEICE TRANS. ELECTRON., VOL.E90 C, NO.4 APRIL 2007 sulting in lower V TS. Consequently, the W/L ratio of M1 n-mosfet should be carefully selected for the appropriate V T and its temperature dependence assumed as in the theory given in Eq. (8). The V TS deviation from the average V TS is less than ±20 mv, which corresponds to the temperature deviation smaller than ±4 C. In Fig. 11, V TS voltages at V DD = 4.0/4.5/5.0/5.5/6.0 V are also shown to give the V TS dependence on the V DD variation. The maximum changes of V TS from V DD = 5.0 V in case of V DD = 5.0 ± 0.5V and V DD = 5.0 ± 1.0Vare±4mVand±9mV, respectively, which mean the temperature deviations of less than ±1 and ±2 C, respectively. The fluctuations in TC and V TS may be caused from the variations of V T, n as well as MOSFET s size among the measured chips. Consequently, the absolute V TS voltage control as well as the V DD stability should be controlled to realize the high precision temperature sensor by using the circuit. The supply currents I DD versus V DD characteristics of the typical temperature sensor circuit at 60, 20 and 100 C are shown in Fig. 12. I DD is about 40µA atv DD = 5.0V almost independently from temperature. To lower the I DD, it is necessary to decrease the W/L ratios of p-mosfets in both of the current mirror and the start-up circuits. Summary of the measured data is given in Table 1. All of the measured data give the reasonable results as expected from the simple theory as well as the HSPICE simulation results. V TS and TC variations among many samples may be improved when the temperature sensor circuit was fabricated on the same chip using a triple well CMOS process, because the difference of M1 characteristics from the n-mosfets used in the main temperature circuit should become smaller than the two chip operation used in our experiments. However, it is experimentally demonstrated that the proposed CMOS temperature sensor circuit has a potentiality to give a good stabilized TC independently from the supply voltage variation. In the following, some challenges to be solved for improving the circuit performance are described. (1) One chip integration including M1 n-mosfet. It is difficult to integrate the source-substrate connected M1 with the main temperature sensor circuit on the same chip in the case of the 1.2 µm n-well CMOS process, in which all n- MOSFETs have the common substrate (=GND). To realize a one-chip temperature sensor, it needs to use a triple-well CMOS process in which any n-mosfet s source can be connected to the individual p-well isolated from the common GND, resulting in the source-substrate connected M1 on the same chip. (2) Lower V DD operation. It was shown by the simulation that the minimum V DD (V DDmin ) of the MOSFET threshold-voltage reference circuit, which is the basic circuit of the temperature sensor, could be decreased to 1.2 V when V T was lowered to 0.2 V [12]. Furthermore, V DDmin can also be decreased when L 4 /L 3 ratio is lowered though resulting in lower TC as given in Fig. 6(b). Consequently, V DDmin of the temperature sensor circuit can be decreased by lowering V T as well as compromising TC and L 4 /L 3 ratio. (3) Lower power consumption. It can be easily realized to extremely lower the W/L ratios of all load p-mosfets. (4) Control of absolute V TS voltage as well as TC value independently from the process variations. It may need the switching method to select the optimum N4 n-mosfet for obtaining the suitable L 4 /L 3 ratio to satisfy the above problems. However, the fixed L 4 /L 3 ratio can be adopted in case of the lower specifications for the absolute V TS and TC. 5. Conclusion Fig C. Typical V DD dependent supply currents I DD at 60, 20 and Table 1 Summary of the temperature sensor circuit. Supply voltage V DD 5.0±1.0 V Supply current I DD 40 µaat5.0v Output voltage (V TS )at20 C 1.77 V at L 4 /L 3 = 9 Temperature coefficient (TC) 5.1 mv/ C at L 4 /L 3 = 9 Technology 1.2 µm n-wellcmos Active area without N4 n-mosfets array 0.18 mm 2 A temperature sensor circuit is proposed and fabricated by a standard 1.2 µm n-well CMOS process. The optimum combination of three current modes (i.e., the subthreshold current, the linear current and the saturation current) of n- MOSFETs, the feedback scheme from the V TD output to the gates of three n-mosfets, as well as the addition of the source-substrate connected M1 n-mosfet made it possible to generate the temperature sensor voltage V TS from the source node of the M1. The TC of the V TS is almost independent from the V DD variation can be easily controlled by the channel-length ratio (L 4 /L 3 ) of N4 and N3 n-mosfets. The temperature sensor circuit consists of only 17 MOS- FETs including the start-up circuit, and has no high resistors resulting in a small die area of 0.18 mm 2 without the N4 n-mosfets array. The temperature sensor circuit gives the average TC of about 5.1 mv/ C for V DD = 5.0 ± 1.0 V and the temperature range from 20 to 100 C at L 4 /L 3 = 9. The typical output voltage V TS at V DD = 5.0V (20 C) at L 4 /L 3 = 9is

7 OHZONE et al.: A CMOS TEMPERATURE SENSOR CIRCUIT 901 about 1.77 V. All experimental data are in good agreements with the simple theories as well as HSPICE simulations, and proved that the temperature sensor was operated following the simple theory. However, it needs further studies to discuss the deviations and the fluctuations of V TS and TC between the different wafers, lots as well as the scaled down CMOS processes. Acknowledgments This work is supported by the VLSI Design and Education Center (VDEC), The University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. The VLSI chips in this study have been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with On-Semiconductor, Nippon Motorola LTD., HOYA Corporation, and KYOCERA Corporation. We acknowledge T. Hikasa for designing the temperature sensor circuit. References [1] H. Sanchez, R. Philip, J. Alvarez, and G. Gerosa, A CMOS temperature sensor for PowerPC TM RISC microprocessors, 1997 Symp. on VLSI Circuits Dig. Tech. Papers, pp [2] V. Szekely, C. Marta, Z. Kohari, and M. Rencz, CMOS sensors for on-line thermal monitoring of VLSI circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.5, no.3, pp , Sept [3] P. Chen, C.-C. Chen, C.-C. Tsai, and W.-F. Lu, A time-to-digitalconverter-based CMOS smart temperature sensor, IEEE J. Solid- State Circuits, vol.40, no.8, pp , Aug [4] A. Bakker, CMOS smart temperature sensors An overview, Proc. IEEE Sensors, vol.2, pp , June [5] M. Ismail and T. Fiez, Analog VLSI, Signal and Information Processing, pp , McGraw-Hill, New York, [6] M. Tuthill, A switched-current, switched-capacitor temperature sensor in 0.6-µm CMOS, IEEE J. Solid-State Circuits, vol.33, no.7, pp , July [7] G.C.M. Meijer, G. Wang, and F. Fruett, Temperature sensors and voltage references implemented in CMOS technology, IEEE Sensors J., vol.1, no.3, pp , Oct [8] M. Pertijs, A. Niederkorn, X. Ma, B. McKillop, A. Bakker, and J. Huijsing, A CMOS temperature sensor with a 3σ inaccuracy of ±0.5 C from 50 C to 120 C, IEEE ISSCC Dig. Tech. Papers, pp , Feb [9] K.S. Szajda, C.G. Sodini, and H.F. Bowman, A low noise, high resolution silicon temperature sensor, IEEE J. Solid-State Circuits, vol.31, no.9, pp , Sept [10] A. Bakker and J.H. Huijsing, Micropower CMOS temperature sensor with digital output, IEEE J. Solid-State Circuits, vol.31, no.7, pp , July [11] T. Matsuda, R. Minami, A. Kanamori, H. Iwata, T. Ohzone, S. Yamamoto, T. Ihara, and S. Nakajima, A V DD and temperature independent CMOS voltage reference circuit, Proc. Asia and South Pacific Automation Conf (ASP-DAC 2004), pp , Jan [12] T. Matsuda, R. Minami, A. Kanamori, H. Iwata, T. Ohzone, S. Yamamoto, T. Ihara, and S. Nakajima, A temperature and supply voltage independent CMOS voltage reference circuit, IEICE Trans. Electron., vol.e88-c, no.5, pp , May Takashi Ohzone was born in Nagoya, Japan, on March 24, He received the B.S. and M.S. degrees in electrical engineering from Nagoya University, Japan, in 1966 and 1968, respectively, and Ph.D. degree in engineering science from Osaka University, Japan, in In 1968, he joined the Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Osaka, Japan, where he had been working on the research and development of MOS integrated circuits, charge-coupled devices, static RAMs and dynamic RAMs. In April 1990, he joined the Department of Electronics and Informatics at Toyama Prefectural University, as a professor. He moved to the Department of Communication Engineering at Okayama Prefectural University in October His current research interests are CMOS devices/circuits, light emitting effects from Si devices, and reconfigurable microprocessors. Tatsuaki Sadamoto received the B.E. degree in communication engineering from Okayama Prefectural University, Okayama, Japan, in 2006, where he is currently pursuing the M.S. degree in communication engineering. Takayuki Morishita received the B.S., M.S. and Ph.D. degrees in electronics from Okayama University in 1979, 1981 and 1988, respectively. Since 1993, he has been an associate professor of the Department of Communication Engineering of Okayama Prefectural University. Kiyotaka Komoku received the B.S. and M.S. degrees in physics from Okayama University, Japan, in 1991 and 1994, respectively. Since 1994, he has been a research associate of the Department of Communication Engineering of Okayama Prefectural University. His research interests are media processing using reconfigurable device and VLSI design.

8 902 IEICE TRANS. ELECTRON., VOL.E90 C, NO.4 APRIL 2007 Toshihiro Matsuda received the B.E. degree from Kyoto University in 1978, the M.S. degree in electrical engineering from the University of Michigan in 1985, and Ph.D. degree in engineering from Toyama Prefectural University in 1999, respectively. From 1978 to 1990, he was involved in CMOS and Bi-CMOS LSI design at Hitachi Ltd. He is currently a professor at Toyama Prefectural University. His research interests are CMOS device technology, light emitting effects from semiconductor devices, and VLSI design. Hideyuki Iwata received the B.S. and M.S. degrees in mathematics from Keio University, Japan, and the Dr. Eng. degree in electronic engineering from Nagoya University, Japan. He joined the Semiconductor Research Center, Matsushita Electric Co Ltd., Osaka, where he was engaged in the development of DRAMs and the numerical modeling and simulation of MOS devices. He later joined Toyama Prefectural University, Toyama, Japan, and is presently an associate professor. His current research interests include physics, modeling and simulation of advanced MOSFETs and quantum effect devices.