MOS PTAT Floating reference voltage circuit for PTAT current generation using subthreshold MOS characteristics

Transcription

1 MOS PTAT Floating reference voltage circuit for PTAT current generation using subthreshold MOS characteristics Ken Ueno Tetsuya Hirose Tetsuya Asai Yoshihito Amemiya Department of Electrical Engineering, Hokkaido University 1,, MOSFET PTAT,,,,, LSI,, 2 PTAT, MOSFET,, µw LSI PTAT(Proportional To Absolute Temperature), MOSFET PTAT MOSFET,, na,, MOS PTAT LSI [1] LSI [1] MOSFET V GS, MOSFET V T H I D, PTAT (Proportional, 01 V To Absolute Temperature),, I D [2], VGS V T H I D = I 0 exp (1) PTAT,,, I 0, PTAT V T (= k B T/e), k B, T

2 V, e, η DD, 2 I D1, /I D1, I D1 /, I 0, V T H V out2, V GS1 M1 M2 V GS2 M3 M4 V out1 I D1 = I D1 I ( D2 VGS2 V GS1 exp ) ( exp V GS2 V GS1 ) (2) M D1 I 1 I 2 I 1 I 2 M D2 V GS2 V GS1, 1: I D1 I D1 = 2 V GS2 V GS1 (3) Buck CMOS [4] (3),, 1 I D1 I = D1 2(V I GS2 V GS1 ) D2 31 ηk B = 2e(V GS2 V GS1 ) T (4) 1,, 2 I D1, MOSFET(M D1, M D2 ) V GS1, V GS2 V GS2 V GS1 2 (M1-M2, M3-M4) mv, MOSFET (K = W/L) PTAT, K D1 > K D2, K 1 < K 2, K 3 > K 4 (5) [1], V GS2 V GS1 MOSFET R,, MOSFET [5, 6], 2 V out1,, V out2 V GS2 V GS1 2 MOSFET (M D1, M D2 ) 3 V GS,Di, Ibias V GS,Di = V T H,Di + ln (i = 1, 2) (6) K Di I 0 [3] na MOS, V GS,D (= V GS,D2 V GS,D1 ), MΩ,, KD1 V GS,D = V T H,D21 + ln (7) K D2

3 , V T H,D21 (= V T H,D2 V T H,D1 ), V GS,D, M1-M2, M1, M2 I 1, I 2, Vs V GS,Di V T Hi 04 I i = K i I 0 exp (i = 1, 2) (8) 036 Temperature, V s, M1-M2 M2 I 2 2: (V out1, V out2 ) M4, M3, M4 V GS,3, V GS,4 105 Ii V GS,i+2 = V T H,i+2 + ln (i = 1, 2) K i+2 I 0 (9), V out1, V out2 V REF (=V out2 V out1 ), V REF = V GS,4 V GS,3 (10) 3: V REF (=V out2 V out1 ) (7), (8), (9), (10) V out1, V out2 (V) V REF (mv) V out2 V out1 V REF = V out2 - V out1 95 Temperature V REF = V T H,43 + V T H,12 V T H,D21 K3 K 2 K D2 + ln (11) K 4 K 1 K D1, V T H,43 (= V T H,4 V T H,3 ), V T H,12 (= 32, 035 µm-cmos SPICE, 15 V V T H,1 V T H,2 ), 2 V out1 V out2, (5) 20 C 100 C MOSFET, K 3 K 2 K D2 = K 4 K 1 K D1 (12) 3 V REF (=V out2 V out1 ) 10 mv, (11) ( 4, ), ±27 %, MOSFET(M D1, M D2 ) V REF = V T H,43 + V T H,12 V T H,D21 (13),, MOSFET, [5], 2 V out1, V out2 V REF, PTAT, PTAT,

4 4 MOSFET I PTAT, I REF1, (a) (b) [7]-[10], Rincon-Mora Allen 4: (, ) [10] PTAT CTAT V DD, I PTAT I REF1 I PTAT M I REF2 curv1 M curv2,, I I I PTAT CTAT curv1 I REF1 REF2 curv2 I R1 PTAT, generator Operating at low temp Operating at high temp 5: 41, I curv, I curv MOSFET(M D2 ), I curv,, V GS,D = V T H,D21 KD1 ( + I curv ) + ln (15) K D2 4(a), I REF 1 < V REF (=V out2 V out1 ) I REF 2, PTAT T 1, T 2 V REF = V T H,43 + V T H,12 V T H,D21 ( ) + ln (16) + I curv Currents PTAT current I REF2 Curvature-correcting currents (= I REF1 -I PTAT ) (= I PTAT -I REF2 ) T 1 T 2 T 1 T 2 Temperature Temperature 42 I curv, I M D2 V GS,D2 curv,,, Ibias + I curv I curv V GS,D2 = V T H,D2 + ln (14) K D2 I 0, I curv, 2 MOSFET(M D1, M D2 ) I curv1 (at low temp) V GS,D, I curv = 0 (at middle temp) (17) (at high temp) 0 I curv, PTAT I P T AT 2 I REF 1, I REF 2, T 1, PTAT I REF 1,, T 2, PTAT I REF 2 4(b),

5 V DD M curv1 M curv2 I curv I REF1 I REF2 V GS1 V out2 M1 M2 V GS2 M3 M4 V out1 I PTAT I PTAT M D1 I 1 I 2 I 1 I 2 M D2 I REF1 R1 I PTAT Current source Floating voltage reference PTAT current generator Operating at low temp Operating at high temp Curvature-correcting current generator 6: T 1, = I REF 1 I P T AT I P T AT I REF 2, M curv1, T 2 = I P T AT I REF 2 I curv, (17) I curv, I curv I curv, I REF 1 I P T AT (at low temp) 43 I curv = 0 (at middle temp) I P T AT I REF 2 (at high temp) 6, (18) SPICE 100 na, I REF 1 I REF 2 5 PTAT 2, 160 na, 190 na PTAT I P T AT, I REF 1 ( [11] ) I REF 2 7 I curv, PTAT I REF 1, I P T AT <I REF 1, PTAT M curv1, = I REF 2, I REF 1 I P T AT, M curv2 I curv MOSFET(M D2 ), I REF 1 < I P T AT < I REF 2, M curv1, M curv2 8 I curv V REF (=V out2 V out1 ), ±27 %, I REF 2 < I P T AT,,, M curv2, = ±03 %

6 , (na) Temperature [1] K Ueno, T Hirose, T Asai, Y Amemiya, Ultralow-power smart temperature sensor with subthreshold CMOS circuits, Proc ISPACS, pp , Dec 2006 [2] Y Taur, TH Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2002 [3] PE Allen, DR Holberg, CMOS analog circuit design second edition New York Oxford University Press, 2002 [4] AE Buck, CL McDonald, SH Lewis, TR 7:, Viswanathan, A CMOS bandgap reference without resistors IEEE J Solid-State Circuits, vol37, no1, pp81-83, Jan 2002 V REF (mv) w/o curvature correction curvature correction 95 Temperature [5] MC Hsu, BJ Sheu, Inverse-geometry dependence of MOS transistor electrical parameters, IEEE Trans Computer-Aided Design, vol CAD- 6, pp , July 1987 [6] YC Cheng, M-C Jeng, ZLiu, JH Huang, M Chen, K Chen, PK Ko, C Hu, A physical and scalable IV model in BSIM3v3 for analog/digitalcircuit simulation, IEEE Trans Electron DeVices, vol 44, No 2, pp , Feb 1997 [7] B-S Song, PR Gray, A precision curvaturecompensated CMOS bandgap reference, IEEE J 8: Solid-State Circuits, vol SC-18, pp , Dec V REF (=V out2 V out1 ) 1983 [8] GCM Meijer, PC Schmale, KV Zalinge, A new curvature-corrected bandgap reference, IEEE J Solid-State Circuits, vol SC-17, pp , Dec 1982 [9] M Pertijs, K Makinwa, J H Huijsing, A CMOS 46 µw smart temperature sensor with a 3σ inaccuracy of (T =100 C) ±01 C from 55 C to 125 C, IEEE J Solid-State Circuits, vol 40, no 12, pp , Dec [10] GA Rincon-Mora, PE Allen, A 11-V currentmode and piecewise-linear curvature-corrected, PTAT 035 µm-cmos bandgap reference, IEEE J Solid-State Circuits, vol 33, pp , Oct 1998 SPICE 20 C 100 C [11] T Hirose, T Matsuoka, K Taniguchi, T Asai, Y Amemiya, Ultralow-power current reference circuit with low temperature dependence, IEICE, ±27 %, Trans Electron, VolE88-C, no6, pp , ±03 % Nov 2004, PTAT,, 46 µw