A Low Power Bandgap Voltage Reference with Nonlinear Voltage Curvature Compensation

Size: px
Start display at page:

Download "A Low Power Bandgap Voltage Reference with Nonlinear Voltage Curvature Compensation"

Transcription

1 rd International Conference on Engineering echnology and Application (ICEA 2016) ISBN: A Low Power Bandgap Voltage Reference with Nonlinear Voltage Curvature Compensation Shuowei Jin*, Zhenni Li, Jingjiao Li & Aixia Wang College of Information Science and Engineering, Northeastern University, Shenyang, Liaoning, China ABSRAC: he reference voltage source is the main part both in the analog and mixed-signal integrated circuits. A good reference voltage source can provide a stable voltage for the circuit, so that the system can work stable accurately. his paper describes a low power bandgap voltage reference with second order compensated, which utilizes a Kujik bandgap reference as the first order curvature correction and adding second order non-linear voltage compensation. he presented circuit is implemented in a 0.18μm CMOS technology, and the voltage supply (VDD) is 1.8V. Piecewise curvature compensation is employed to reduce the temperature coefficient of the bandgap reference from 465ppm/ C to 5.5ppm/ C, with a temperature range 45~85 C. he circuit works under the condition of 27 C, the output of the reference voltage is V. he total current consumption of the whole bandgap is 11.69μA, the total area of the layout is mm 2 and the power supply rejection ratio is -63dB. Keywords: low power; bandgap voltage reference; second order compensated 1 INRODUCION During the last years, the research of mobile device has been widely used, and the growing demand for low power is pushed by the fact that the majority of recently proposed systems are battery-operated [1]. Bandgap reference voltage circuit is necessary for high precision processing systems, such as voltage regulators, analog to digital converters, digital to analog converters [2]. Aggressive technology scaling coupled with scaled power supply units is reduced area on the expense of lower dynamic range. Hence, to achieve a high dynamic range with the reduced supply voltage, the reference voltage needs to be very accurate [3,4]. Since 1971 when Widlar proposed the bandgap voltage reference [5], the references went through much of research and many new methods are proposed in the literature [6]. A first order bandgap voltage reference circuit is inadequate to provide high accuracy voltage, thus several high order curvature compensation techniques have been proposed [7]-[9]. A high order nonlinear compensation reference is achieved by using different-type resistors, with the cost of process dependency in [7]. In [8], a CA *Corresponding author: jinshuowei@ise.neu.edu.cn current is generated to compensate bandgap voltage for accuracy. While in [9] the high order nonlinear reference is canceled utilizing MOS transistor operating in weak inversion region. his paper presents a second order curvature correction voltage reference, which uses a Kujik bandgap voltage reference source circuit as the first order, by adding second-order curvature compensation circuit, in order to implement a bandgap reference voltage source with very low temperature coefficient. his article is based on CMOS tsmc0.18 standard process, starts with a short introduction about the Kujik voltage reference in Section 2, and briefly describes the temperature dependence of the base in Section 3. Second-order curvature compensation bandgap voltage reference source circuit is approached in Section 4, and shows the experimental results and performance comparison with other bandgap voltage references. Finally, Section 5 draws the conclusion. 2 KUJIK BANDGAP VOLAGE REFERENCE Kujik bandgap voltage reference sources can be applied to standard CMOS process, with low power 477

2 consumption, low temperature coefficient. Figure 1 presents the bandgap voltage reference implementation. 3.1 Nonlinear second order piecewise compensation circuit he traditional bandgap voltage reference compensates a first order temperature coefficient in the whole temperature range, and it utilizes the sum of VBE which has a negative temperature coefficient and VBE which has a Positive temperature coefficient. VBE is not a linear function of temperature, so the bandgap voltage can obtain accurate compensation only near the reference temperature 0, and the greater the error will be caused by the greater the temperature range. If the whole temperature range is divided into several segments and compensated respectively, the temperature coefficient will be reduced effectively. In this paper, the whole temperature range is divided into two parts, and the core compensation schematic is shown in Figure 2. Figure 1. Kujik bandgap reference source. he circuit can be implements in a standard 0.18μm CMOS technology. wo PMOS transistors have the same width to length ratio, and the emitter area of Q2 is 8 times of the emitter area of Q1, noted by n=8. hen we have the following equations: VA VBEQ0 VB VBEQ2 R0IQ2 (1) hen we have R0IQ2 VBEQ0 VBEQ2 VBE V lnn (2) Figure 2. he core compensation schematic. So, the reference voltage is VB, and given by V R I V V V B 0 Q2 BEQ2 BE BEQ2 V ln nv BEQ2 (3) where V=k/q is positive temperature coefficient, k is Boltzmann s constant, is the absolute temperature in Kelvin, q is the electronic charge. VB is the first order bandgap reference voltage Vref. 3 LOW POWER HIGH PRECISION BANDGAP VOLAGE REFERENCE A first order bandgap voltage reference only has a first order linear compensation, and its temperature coefficient is still not small enough. In order to obtain more stable output bandgap voltage reference, this paper presents a nonlinear second order correction technique by using resistances. Figure 3. he schematic of piecewise compensation. VBE is the piecewise function of temperature, can be written as VBE =VBE (R3+R4)+INLR4, the temperature coefficient of R3 and R4 is ignored here. he compensating current is made up of two parts, one is 478

3 the positive temperature coefficient current IPA, and the other is piecewise compensation current INL. INL is the piecewise function of temperature, it is 0 when the temperature is low and it is IPA-ICA when the temperature is high, where ICA is negative temperature coefficient current. INL can be made by the schematic shown in Figure 3. he current of MP0 is ICA, when the temperature is low we can have ICA>IPA. If MP1 is in the saturation region, then we can have IMp1=ICA and IMp1>IPA. But according to the kirchhoff s current law, the current of MP1 is lower than IPA, MP1 must be in linear region, the VDS of MP1 is small, MP2 and MP3 will cut off. When the temperature is high we can have ICA<IPA, MP1 is in the saturation region, and the current of MP1 is ICA. he VDS of MP1 is big, MP2 and MP3 turn on, and the current is the difference of ICA and IPA, the current of MP3 is INL. In conclusion, the current of MP3 is 0 when the temperature is low and is the difference of ICA and IPA when the temperature is high. 3.2 Nonlinear second order bandgap voltage reference he presented bandgap voltage reference is shown in Figure 4. he emitter area of Q1 is 8 times of the emitter area of Q0 and Q2, the voltage of A and B is the same, and the reference voltage can be changed by adjusting the value of the resistors. base-emitter voltage when the temperature is 0, η is a temperature constant depending on the technology, α is the order of the temperature dependence of the collector current. If α=0, the BJ current is independent of temperature. If α=1, the BJ current is proportional to absolute temperature. From (4), ln is a high order nonlinear term, the first order bandgap voltage reference compensates for term, while the second order implies the additional cancellation of the nonlinear term. In Figure 2, M14, R2, R4 and Q2 make up the second order compensation circuit. he current of Q2 has been compensated by the first order, so it is temperature independence, α=0, the base-emitter voltage is given by VBE2VG VG VBE0 V ln (5) 0 0 he current of Q0 is proportional to absolute temperature, α=1, the base-emitter voltage is VBE0 1 VG VG VBE0 1V ln 0 0 (6) From Figure 2, the voltage of R2 and R4 is the difference between the base-emitter voltage of Q0 and Q2 VNL VBE2VBE0 V ln (7) 0 he current of M12, M13 is given as VG VG VBE0 I IVBE INL IPA R1 R1 0 1 V V V ln ln lnn R1 0 R2 0 R3 (8) Figure 4. Nonlinear second order correction bandgap voltage reference he goal of the first order bandgap voltage reference is to cancel the temperature dependence of a base-emitter voltage (VBE) by summing with a PA voltage. But the relationship between VBE and temperature is not fully liner, we have the following expression: k VBE VBG VBG VBE0 ln (4) 0 q 0 Where VBG is the bandgap voltage, VBE0 is the From (8), the current is temperature-independent, and the summation of the terms which contain is 0. We can have V V V ln R G BE0 n (9) 3 R V V ln ln (10) R R Combining equations (9) and (10) leads to the following R R V V qr K ln 0 n G BE0 0 2 (11) 1 R2 1 From (11) and (12), the value of R1 and R2 can be set by a proper value of R0. (12) 479

4 Figure 5. he whole circuit of the bandgap voltage reference. Figure 6. Layout of the presented reference. 3.3 he whole circuit of the bandgap voltage reference he whole circuit of the bandgap voltage reference is shown in Figure 5, which is made up of: bias circuit, OA, bandgap circuit and start-up circuit. he OA is shown in the middle of Figure 5. It is a folded cascode amplifier, for it has high voltage gain and good power supply ripple rejection. Using common source common grid, which has excellent shielding characteristics, can avoid the change of the output node to influence the input MOS. Meanwhile it has a high output impedance, and reduces the impact on current by the output voltage. Due to the 1 / f noise is inversely proportional to the area of the MOS pipe, the input PMOS is large, and it can reduce the power supply ripple rejection. he bias circuit is shown in the left of Figure 5. Appropriate bias voltage and current is provided by the left four MOS, and the bias voltage and current is low pertinence to the power supply. For determining the current, R0 in the source of M0 is set. Meanwhile the source and the substrate of the MOS is connected to eliminate the effect of the body. o prevent the bandgap reference from working on the zero working point, a start-up circuit formed by M1, M2, and M3 is necessary, which is shown in the right of Figure 6. If the bandgap reference works on the zero working point, the current is 0 of the whole circuit, Vref is 0, M3 cuts off. he gate voltage of M2 is Vdd+Vthp, which drives M2 on, the output of OA is then pulled down, the current of the bandgap reference no longer is 0, the circuit works up to the normal working point. Choosing proper size of M1 and M3, the gate voltage of M2 is lower than Vthn, then M2 cuts off, meanwhile the current of M3 is infinitesimally small. he start-up circuit does not affect the bandgap reference on normal working point. he layout of the presented reference is shown in Figure 6, and the total area is mm 2. 4 SIMULAION RESULS his second order nonlinear compensated bandgap voltage reference will be fabricated in 0.18μm CMOS technology and the simulation tool that we used is Cadence. he supply voltage is 1.8V. he total current consumption of the whole bandgap is 11.69μA. he simulation result for the first order reference output voltage versus temperature is shown in Figure 7. he maximum output voltage is V, the minimum voltage is V and the output voltage is V when the temperature is 27 C. he temperature coefficient is only 465ppm/ C. he simulation result for the second order nonlinear compensated reference output voltage versus temper- 480

5 ature is shown in Figure 8. he maximum output voltage is V, the minimum voltage is V and the temperature coefficient is only 5.5ppm/ C. current consumption and PSRR is good, the temperature coefficient is normal, and the active area is a little big. Figure 7. Simulation results for the first order reference output voltage versus temperature. Figure 9. Simulation result for PSRR. Figure 8. Simulation results for the second order nonlinear compensated reference output voltage versus temperature. he simulation result for PSRR (Power Supply Rejection Ratio) is shown in Figure 9. he PSRR is still -63dB at 1MHz. he simulation results for process corners are shown in Figure 10, and the process corner is the best. able 1 shows the comparison with other results. From the table, the reference voltage is highest, the Figure 10. Simulation results for process corners. 5 CONCLUSION A second order nonlinear compensated bandgap voltage reference is presented. he presented reference achieved a temperature coefficient of 5.5ppm/ C from -45 C to 85 C, and PSRR -63dB at 1MHz. he output value is from V to V. he total current consumption of the whole bandgap is 11.69μA. he total area of the layout is mm 2. able 1. Comparison with other published results. Parameter Ref.[10] Ref.[11] Ref.[12] Presented reference Year reported Supply voltage(v) Current consumption(µa) Reference voltage(mv) PSRR emperature coefficient(ppm/ C) Active area(mm 2 ) NA echnology (µm CMOS)

6 REFERENCES [1] Ann-Johan, Annema Low-power bandgap references featuring DMOS s, IEEE Journal of Solid-State Circuits, 34(4): [2] Eric Bohannon, Clyde Washburn, P.R. Mukund An ultra-thin oxide sub-1 V CMOS bandgap voltage reference. Int. J. Circ. heor. Appl., 42(8): [3] Siew Kuok Hoon, Jun Chen, Maloberti. F An improved bandgap reference with high power supply rejection, Circuits and Systems, ISCAS IEEE International Symposium on, 1(5): [4] Y Jiang, E.K.E Lee Design of low-voltage bandgap reference using transimpedance amplifier. IEEE ransactions on Circuits and Systems, 47(5): [5] R. Widlar, New developments in IC voltage regulators, IEEE Int. Solid-State Circuits Conf. Dig. ech. Pap., 6(1): 2-7. [6] Dalton Martini Colombo, Gilson Wirth, Sergio Bampi Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13 µm CMOS. Analog Integrated Circuits and Signal Processing, 82(1): [7] Ka Nang Leung, Mok, P.K.., Chi Yat Leung A 2V 23μA 5.3ppm/ C curvature-compensated CMOS bandgap voltage reference Circuits, IEEE Journal of Solid-State, 38(3): [8] Andreou, C.M., Koudounas, S., Georgiou, J A novel wide-temperature-range, 3.9ppm/ C CMOS bandgap reference circuit, IEEE Journal of Solid-State Circuits, 47(2): [9] Bill Ma, Fengqi Yu A Novel 1.2 V 4.5-ppm/ C curvature-compensated cmos bandgap reference, IEEE ransactions on Circuits and Systems I: Regular Papers, 61(4): [10] Basyurt, P.B., Aksin, D.Y Design of a curvature-corrected bandgap reference with 7.5ppm/ C temperature coefficient in 0.35μm CMOS process, Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, pp: [11] Duan Q., Roh J A 1.2-V 4.2-ppm/ C high-order curvature-compensated CMOS bandgap reference, IEEE ransactions on Circuits and Systems I, 62(3): [12] Necula I. C., Cosmin Radu Popa Voltage reference with second order curvature correction. Semiconductor Conference (CAS), pp:

4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP)

4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP) emp. Indep. Biasing (7/14/00) Page 1 4.5 (A4.3) - EMPERAURE INDEPENDEN BIASING (BANDGAP) INRODUCION Objective he objective of this presentation is: 1.) Introduce the concept of a bandgap reference 2.)

More information

Piecewise Curvature-Corrected Bandgap Reference in 90 nm CMOS

Piecewise Curvature-Corrected Bandgap Reference in 90 nm CMOS IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Piecewise Curvature-Corrected Bandgap Reference in 90 nm CMOS P R Pournima M.Tech

More information

CMOS LOGARITHMIC CURVATURE-CORRECTED VOLTAGE REFERENCE BY USING A MULTIPLE DIFFERENTIAL STRUCTURE

CMOS LOGARITHMIC CURVATURE-CORRECTED VOLTAGE REFERENCE BY USING A MULTIPLE DIFFERENTIAL STRUCTURE CMOS LOGARIHMIC CURAURE-CORRECED OLAGE REFERENCE BY USING A MULIPLE DIFFERENIAL SRUCURE COSMIN POPA Key words: emperature behavior, Superior-order curvature-correction techniue, oltage references. A new

More information

0.9V, 5nW, 9ppm/C Resistorless Sub- Bandgap Voltage Reference in 0.18um CMOS

0.9V, 5nW, 9ppm/C Resistorless Sub- Bandgap Voltage Reference in 0.18um CMOS 0.9V, 5nW, 9ppm/C Resistorless Sub- Bandgap Voltage Reference in 0.18um CMOS Oscar Mattia, Hamilton Klimach and Sergio Bampi Microelectronics Graduate Program Electrical Engineering Department & Informatics

More information

A new curvature-corrected CMOS bandgap voltage reference

A new curvature-corrected CMOS bandgap voltage reference A new curvature-corrected CMOS bandgap voltage reference Ruhaifi Abdullah Zawawi a) and Othman Sidek Collaborative Microelectronic Design Excellence Centre (CEDEC), Universiti Sains Malaysia (USM), Engineering

More information

SPICE SIMULATIONS OF CURRENT SOURCES BIASING OF LOW VOLTAGE

SPICE SIMULATIONS OF CURRENT SOURCES BIASING OF LOW VOLTAGE SPICE SIMULATIONS OF CURRENT SOURCES BIASING OF LOW VOLTAGE MONICA-ANCA CHITA, MIHAI IONESCU Key words: Bias circuits, Current mirrors, Current sources biasing of low voltage, SPICE simulations. In this

More information

A High-Order Compensated Op-amp-less Bandgap Reference with 39 ppm/ºc over -260~125 ºC Temperature Range and -50 db PSRR

A High-Order Compensated Op-amp-less Bandgap Reference with 39 ppm/ºc over -260~125 ºC Temperature Range and -50 db PSRR A High-Order Compensated Op-amp-less Bandgap Reference with 39 ppm/ºc over -26~125 ºC Temperature Range and -5 db PSRR Hechen Wang, Student Member, IEEE, Fa Foster Dai, Fellow, IEEE, and Michael Hamilton,

More information

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS 1

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS 1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS 1 BiCMOS-Based Compensation: Toward Fully Curvature-Corrected Bandgap Reference Circuits Yi Huang, Student Member, IEEE, Li Zhu, Student Member,

More information

A Novel Sub-1 Volt Bandgap Reference with all CMOS

A Novel Sub-1 Volt Bandgap Reference with all CMOS A Novel Sub-1 Volt Bandgap Reference with all CMOS SAMEER SOMVANSHI Dr.S.C.BOSE Dr. ANU GUPTA EEE Department IC Design Group EEE Department BITS-Pilani CEERI-Pilani BITS-Pilani Rajasthan Rajasthan Rajasthan

More information

A low-voltage band-gap reference circuit with second-order analyses

A low-voltage band-gap reference circuit with second-order analyses INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. 2011; 39:1247 1256 Published online 12 July 2010 in Wiley Online Library wileyonlinelibrary.com)..699 A low-voltage band-gap

More information

PT5108. High-PSRR 500mA LDO GENERAL DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATIONS. Ripple Rejection vs Frequency. Ripple Rejection (db)

PT5108. High-PSRR 500mA LDO GENERAL DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATIONS. Ripple Rejection vs Frequency. Ripple Rejection (db) GENERAL DESCRIPTION The PT5108 is a low-dropout voltage regulator designed for portable applications that require both low noise performance and board space. Its PSRR at 1kHz is better than 70dB. The PT5108

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences

A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences 392 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017 A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences Yi Huang, Student Member, IEEE, and Laleh Najafizadeh,

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012 1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

GENERAL DESCRIPTION The PT5128 is a dual channel low-dropout voltage regulator designed for portable and wireless applications that require high PSRR, low quiescent current and excellent line and load

More information

Compact, very low voltage, temperature-independent reference circuit

Compact, very low voltage, temperature-independent reference circuit Compact, very low voltage, temperature-independent reference circuit P.S. Crovetti and F. Fiori Abstract: A compact, very low voltage, temperature-independent reference circuit, which is based on the thermal

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

Microelectronics Main CMOS design rules & basic circuits

Microelectronics Main CMOS design rules & basic circuits GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

More information

Simulation of the Temperature Influence in IC-EMC

Simulation of the Temperature Influence in IC-EMC Simulation of the Temperature Influence in IC-EMC E. Sicard INSA-GEI, 135 Av de Rangueil 31077 Toulouse France Contact : etienne.sicard@insa-toulouse.fr web site : www.ic-emc.org Abstract: We investigate

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

Chapter 3 Output stages

Chapter 3 Output stages Chapter 3 utput stages 3.. Goals and properties 3.. Goals and properties deliver power into the load with good efficacy and small power dissipate on the final transistors small output impedance maximum

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

RP mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator. General Description. Features. Applications. Ordering Information. Marking Information

RP mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator. General Description. Features. Applications. Ordering Information. Marking Information RP122 3mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator General Description The RP122 is designed for portable RF and wireless applications with demanding performance and space requirements. The RP122

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

5-V Low Drop Fixed Voltage Regulator TLE

5-V Low Drop Fixed Voltage Regulator TLE 5-V Low Drop Fixed Voltage Regulator TLE 427-2 Features Output voltage tolerance ±2% 65 ma output current capability Low-drop voltage Reset functionality Adjustable reset time Suitable for use in automotive

More information

Chapter 20. Current Mirrors. Basics. Cascoding. Biasing Circuits. Baker Ch. 20 Current Mirrors. Introduction to VLSI

Chapter 20. Current Mirrors. Basics. Cascoding. Biasing Circuits. Baker Ch. 20 Current Mirrors. Introduction to VLSI Chapter 20 Current Mirrors Basics Long Channel Matching Biasing Short Channel Temperature Subthreshold Cascoding Simple Low Voltage, Wide Swing Wide Swing, Short Channel Regulated Drain Biasing Circuits

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3 ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

More information

MOS Transistors Models

MOS Transistors Models MOS Transistors Models Andreas G. Andreou Pedro Julian Electrical and Computer Engineering Johns Hopkins University http://andreoulab.net The MOS transistor Levels of Abstraction- Model Equations If V

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers 6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

Tutorial #4: Bias Point Analysis in Multisim

Tutorial #4: Bias Point Analysis in Multisim SCHOOL OF ENGINEERING AND APPLIED SCIENCE DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING ECE 2115: ENGINEERING ELECTRONICS LABORATORY Tutorial #4: Bias Point Analysis in Multisim INTRODUCTION When BJTs

More information

Successive approximation time-to-digital converter based on vernier charging method

Successive approximation time-to-digital converter based on vernier charging method LETTER Successive approximation time-to-digital converter based on vernier charging method Xin-Gang Wang 1, 2, Hai-Gang Yang 1a), Fei Wang 1, and Hui-He 2 1 Institute of Electronics, Chinese Academy of

More information

SOME USEFUL NETWORK THEOREMS

SOME USEFUL NETWORK THEOREMS APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem

More information

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

More information

*1. Attention should be paid to the power dissipation of the package when the output current is large.

*1. Attention should be paid to the power dissipation of the package when the output current is large. S-1313 Series www.ablic.com www.ablicinc.com SUPER LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR ABLIC Inc., 211-216 Rev.2.1_1 The S-1313 Series, developed by using the CMOS technology, is

More information

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

More information

The current source. The Active Current Source

The current source. The Active Current Source V ref + - The current source Minimum noise euals: Thevenin Norton = V ref DC current through resistor gives an increase of /f noise (granular structure) Accuracy of source also determined by the accuracy

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

More information

Preamplifier in 0.5µm CMOS

Preamplifier in 0.5µm CMOS A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling

More information

A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load

A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1 Outline

More information

THERMAL EFFECTS ON ANALOG INTEGRATED CIRCUIT DESIGN MD MAHBUB HOSSAIN. Presented to the Faculty of the Graduate School of

THERMAL EFFECTS ON ANALOG INTEGRATED CIRCUIT DESIGN MD MAHBUB HOSSAIN. Presented to the Faculty of the Graduate School of THERMAL EFFECTS ON ANALOG INTEGRATED CIRCUIT DESIGN by MD MAHBUB HOSSAIN Presented to the Faculty of the Graduate School of The University of Texas at Arlington in Partial Fulfillment of the Requirements

More information

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions

Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Ralf Brederlow 1, Georg Wenig 2, and Roland Thewes 1 1 Infineon Technologies, Corporate Research, 2 Technical

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

P-MOS Device and CMOS Inverters

P-MOS Device and CMOS Inverters Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short

More information

A 51pW Reference-Free Capacitive-Discharging Oscillator Architecture Operating at 2.8Hz. Sept Hui Wang and Patrick P.

A 51pW Reference-Free Capacitive-Discharging Oscillator Architecture Operating at 2.8Hz. Sept Hui Wang and Patrick P. A 51pW Reference-Free apacitive-discharging Oscillator Architecture Operating at 2.8Hz Sept. 28 2015 Hui Wang and Patrick P. Mercier Wireless Sensing Platform Long-Term Health Monitoring - Blood glucose

More information

A Leakage Control System for Thermal Stability During Burn-In Test

A Leakage Control System for Thermal Stability During Burn-In Test A Leakage Control System for Thermal Stability During Burn-In Test Mesut Meterelliyoz, Hamid Mahmoodi, and Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,

More information

ECE315 / ECE515 Lecture 11 Date:

ECE315 / ECE515 Lecture 11 Date: ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

More information

LD A high PSRR ultra low drop linear regulator with reverse current protection. Datasheet. Features. Applications.

LD A high PSRR ultra low drop linear regulator with reverse current protection. Datasheet. Features. Applications. Datasheet 2 A high PSRR ultra low drop linear regulator with reverse current protection Features Input voltage from 1.25 V to 6. V Ultra low drop: 13 mv (typ.) at 2 A load 1 % output accuracy at 25 C,

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

70 mv typ. (2.8 V output product, I OUT = 100 ma)

70 mv typ. (2.8 V output product, I OUT = 100 ma) S-1335 Series www.ablicinc.com HIGH RIPPLE-REJECTION SOFT-START FUNCTION CMOS VOLTAGE REGULATOR ABLIC Inc., 212-214 Rev.1.3_2 The S-1335 Series, developed by using the CMOS technology, is a positive voltage

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

SC70, 1.6V, Nanopower, Beyond-the-Rails Comparators With/Without Reference

SC70, 1.6V, Nanopower, Beyond-the-Rails Comparators With/Without Reference 19-1862; Rev 4; 1/7 SC7, 1.6V, Nanopower, Beyond-the-Rails General Description The nanopower comparators in space-saving SC7 packages feature Beyond-the- Rails inputs and are guaranteed to operate down

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level

More information

Chapter 5. BJT AC Analysis

Chapter 5. BJT AC Analysis Chapter 5. Outline: The r e transistor model CB, CE & CC AC analysis through r e model common-emitter fixed-bias voltage-divider bias emitter-bias & emitter-follower common-base configuration Transistor

More information

5 V/10 V Low Drop Voltage Regulator TLE 4266

5 V/10 V Low Drop Voltage Regulator TLE 4266 5 /1 Low Drop oltage Regulator TLE 266 Features Output voltage 5 or 1 Output voltage tolerance ±2% 12 ma current capability ery low current consumption Low-drop voltage Overtemperature protection Reverse

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

MOS PTAT Floating reference voltage circuit for PTAT current generation using subthreshold MOS characteristics

MOS PTAT Floating reference voltage circuit for PTAT current generation using subthreshold MOS characteristics MOS PTAT Floating reference voltage circuit for PTAT current generation using subthreshold MOS characteristics Ken Ueno Tetsuya Hirose Tetsuya Asai Yoshihito Amemiya Department of Electrical Engineering,

More information

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

More information

Delay and Energy Consumption Analysis of Conventional SRAM

Delay and Energy Consumption Analysis of Conventional SRAM World Academy of Science, Engineering and Technology 13 8 Delay and Energy Consumption Analysis of Conventional SAM Arash Azizi-Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, and Ali Barati Abstract

More information

IH5341, IH5352. Dual SPST, Quad SPST CMOS RF/Video Switches. Description. Features. Ordering Information. Applications. Pinouts.

IH5341, IH5352. Dual SPST, Quad SPST CMOS RF/Video Switches. Description. Features. Ordering Information. Applications. Pinouts. SEMICONDUCTOR IH, IH2 December Features Description Dual SPST, Quad SPST CMOS RF/Video Switches R DS(ON) < Ω Switch Attenuation Varies Less Than db From DC to 00MHz "OFF" Isolation > 0dB Typical at 0MHz

More information