A 51pW Reference-Free Capacitive-Discharging Oscillator Architecture Operating at 2.8Hz. Sept Hui Wang and Patrick P.
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1 A 51pW Reference-Free apacitive-discharging Oscillator Architecture Operating at 2.8Hz Sept Hui Wang and Patrick P. Mercier
2 Wireless Sensing Platform Long-Term Health Monitoring - Blood glucose - Gastric PH Environmental Monitoring - Temperature - Water quality Energy Harvesting - Power extracted from the inner ear Nature Biotechnology 2012 ourtesy of Prof. Patrick Mercier Ultra-Low-Power Timer with Low Supply Voltage 2
3 Outline On-hip Oscillators Reference-Free apacitive-discharging Topology Frequency Stability, Area, Power Measurement Results onclusions 3
4 Review: Relaxation Oscillator Basic Relaxation Oscillator Reference Generator Required Temperature stable voltages V 1, V 2, V 3 Accurate frequency Temperature compensated references Hard to achieve pw R defines frequency Hard to scale to Hz V 1 V 2 V 3 4
5 Review: One-Hot Topology Schmitt Trigger Based One-Hot Oscillator Gate-Leakage as urrent Reference ü ompact ü Low power Ø High temperature sensitivity 5 Lin, I 2007
6 ompared to onventional Solutions onventional oscillators A ramp voltage is created by charging a capacitor with a temperature-stabilized current source Hard to make it stable, low-current, and low-area for pw-level, Hz-range applications 6
7 ompared to onventional Solutions onventional oscillators A ramp voltage is created by charging a capacitor with a temperature-stabilized current source Proposed Architecture A decaying voltage is obtained by discharging a pre-charged capacitor through a temperature-stable resistor Hard to make it stable, low-current, and low-area for pw-level, Hz-range applications Easy to implement a low temperature-coefficient resistor, enabling stable, low-power, low-area solution Proposed Architecture Provides a Low-Power, Low-Area, Low- omplexity Solution for Next-Generation Wireless Sensing Platforms 7
8 Reference-Free apacitive-discharging Topology Proposed Architecture and Target Ultra-Low Power ompact Sufficient Frequency Stability pw-level power consumption On-chip Hz-range timer < ±500 ppm/ o 8
9 Oscillator Operation at Φ = 1 V c1, p p = V DD c1, p + c2, p V = V e - n DD R t dn, dn, 9
10 Oscillator Operation at Φ = 2 c1, p Vp VDD c1, p + c2, p V = V e - n = DD R t dn, dn, V c1, n n = V DD c1, n+ c2, n V = V e - p DD R t p d, p 10
11 Frequency VS. Supply + 1, 2, 2,, ln c n c n ideal = d n d n c 1, n T R No V DD term in the equation à Rejected as common mode noise, by over 75 db A reference voltage and a decaying voltage initialized from the same source Intrinsic relaxation-like operation ensures accurate frequency 11
12 Frequency VS. omparator Delay omparator delay varies w.r.t. temperature à The variation in comparator delay impact oscillation frequency omparator delay < 10 ppm of oscillation period à The impact of comparator delay is minimized Gate-leakage employed to bias comparator 12
13 Frequency VS. omparator Offset Offset is rejected through averaging, by over 25 db t T t t osc = + ( - ) ideal + V os -V os Small residue error exists due to exponential profile of the decaying voltage t = T - = 2 t ideal f 1 -V os t T = = + 2 t ideal f 2 + V os ì ï + í ï ï î Vn = VDDe c1, p Vp = VDD c1, p c2, p - R t dn, dn, + V OS ì ï Vp = VDDe í ï = ïî - R t dn, dn, + V OS c1, p Vn VDD c1, p + c2, p 13
14 Frequency VS. Switch Leakage Ultra-Low-Leakage Switch Oscillator operates at Hz-range harge leakage can significantly impact oscillation frequency harge leakage is reduced by over 68 db by employing ultra-low-leakage switch O Halloran, ISAS
15 Area and Power onsumption apacitors are sized to be 1.1 pf Dynamic power due to the charging of capacitors is 27 pw Moderate area consumption + 1, 2, 2,, ln c n c n ideal = d n d n c 1, n T R 300 GΩ Resistor for Hz-range Too large for normal resistors How to implement this resistor? 15
16 Implementing a large, temperature-stabilized resistance using gate-leakage devices Temperature-ompensated Gate-Leakage à ompact Design Achieved Proposed Topology is Reference Free à pw Power onsumption Gate-leakage becomes prevalent as technology scales Employed to serve as resistor Dynamic Power omparator Power Buffering Stages 27 pw 20 pw 4 pw Lee, VLSI
17 Measured Frequency VS. Temperature Across a temperature of -40 o to 60 o, the frequency deviates down to ±0.05%/ o 17
18 Measured Power VS. Temperature Across a onsumes temperature 51pW of -40 at o 20 to o 60 o, the -40 frequency o to 60 o, deviates consumes dow to 16pW ±0.05%/ 129pW o 18
19 Measured Allan Deviation Achieves an Allan deviation floor under 500 ppm at room temperature 19
20 Performance Summary Process 65 nm MOS Area µm 2 Frequency Power Supply Temperature Accuracy Temperature Range Supply Sensitivity Allan Deviation Floor 2.8 Hz (nom.) 51 pw 0.5 V 937 ppm/ o -40 o to 60 o offset < 500 ppm 20
21 21 Hz-Range Oscillator omparison
22 onclusion Reference-free capacitive-discharging structure ensures pw-level power consumption Intrinsic relaxation-like operation enables accurate frequency - omparator offset cancellation through averaging Temperature-compensated gate-leakage as resistor ensures small area for Hz-range oscillator Acknowledgement STMicroelectronics for chip fabrication 22
23 A 51 pw Reference-Free apacitive-discharging Oscillator Architecture Operating at 2.8 Hz Hui Wang and Patrick P. Mercier Questions
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