Energy efficient A/D converter design

Transcription

1 Energy efficient A/D converter design Akira Matsuzawa Tokyo Institute of Technology A. Matsuzawa,Titech Matsuzawa & Okada Lab.

2 Outline Overview of ADs OpAmp based AD design omparator based AD design : SAR ADs Flash and sub-ranging ADs Summary A. Matsuzawa,Titech

3 Performance and architectures of ADs 3 onversion frequency (Hz) 0G G 00M 0M M 00k AD has a suitable performance domain. SAR AD expands the performance area Flash omparator based Sub-ranging Pipeline OpAmp based SAR Delta-sigma 0k Resolution (bit) A. Matsuzawa,Titech 8

4 Strategy of energy efficient AD design 4 Reducing static power Reducing capacitance E d T n Reducing voltage G Resistor DA apacitor DA A. Matsuzawa,Titech OpAmp based Dynamic comparator based # of MP TR size Noise lock Flash Sub-range SAR Large TR Small TR with compensation Use complementally ckt. Use self clocking Effective to digital gates Use forward or adaptive body biasing

5 SNR vs. signal bandwidth 5 SNR (db) SNR of ADs is inversely proportional to signal bandwidth, f b. Higher bandwidth results in lower SNR and effective resolution SNR( db) SNR0( db) 0 log B D E F G H I J K [8] O [9] O [0]T []DT []T [3]T/DT [4]DT [5]T [6]T [7]DT SNR 0 50 db/hz f b P SNR( db) 0 log P P N SNR N s N P' ( spectrumdensity) P s ( db) 0 log P' N 0 log SNR( db) SNR0( db) 0 log f b f f b b db/hz 35 db/hz f b (MHz) A. Matsuzawa,Titech

6 Fundamental power of sampling circuit 6 Fundamental power of sampling is often used. However this neglects power for comparison. Sampling circuit Switch apacitor Signal Quantization voltage qn FS N Quantization noise power Noise balance P s 4kTf s qn FS Pqn N n P qn N Track n kt Hold Electrical energy=thermal energy kt n apacitance P d s kt P d of sampling circuit FS f 4kTf N FS s N A. Matsuzawa,Titech

7 Energy consumption of AD 7 onsumed energy of AD is mainly determined by the resolution. Energy of AD is reaching 00x of the fundamental sampling energy, and 0x of the fundamental AD energy consumption. E AD E s P s 4kTf s N P s N Es 4kT f s E s N 0 9 onventional fundamental sampling energy E AD N N 0 9 Fundamental AD conversion energy involving energy consumption of comparator A. Matsuzawa,Titech Timmy Sundstrom, PhD thesis, Linkoping 0.

8 8 OpAmp based AD design A. Matsuzawa,Titech

9 Mega-technology trend of ADs 9 Major conversion scheme is now changing from pipeline to SAR. st stage nd stage Pipeline AD f - + f - + Op amp Op amp s Sample s Amplify OpAmp based design MP DA MP DA onsumes static power st stage nd stage SAR AD omparator based design No static power A. Matsuzawa,Titech

10 Amplifier for pipeline AD 0 An OpAmp realizes an accurate voltage amplification. f I/O transfer characteristics stage out sig DA s OpAmp out Unit conversion circuit ref out omp Data s s sig DA sig f f DA sig DA ref,0 onventionally s = f = A. Matsuzawa,Titech

11 Low voltage OpAmp: Headroom and Pd In A two stage cascade OpAmp can realize low voltage operation. However, the output voltage swing become lower at low voltage operation. bn bp I g m s _ pp I I g m I Out Two stage OpAmp eff eff s eff P GBW g I g I P m tot da I gm 4 5 eff 0 I 0 4 Nf I Nf c tot eff Total Pd of AD c 0 Nf c 5 Nfc m gm I 4 4 I 0 eff n _ th Nfc kt n eff n _ th Nfc eff GS eff 0. 5 n=4 kt n kt n _ th eff dpipe Pdamp 0 n _ th n kt T n A. Matsuzawa,Titech

12 Required performances Required gain and bandwidth of OpAmp and capacitance are determined by the resolution and conversion frequency. Open loop gain G db ( ) 6N 0 70dB: 0b 94dB: 4b N: Resolution f c : onversion freq. Quantization voltage Thermal noise Unit capacitance GBW q 3 n sig N 3 ENOB _ th q 0 n GBW Nf c kt n _ th N eff γ n β : noise : # of : ENOB: Effective # of bit ENOB :Degradation from noise feedback coefficien t sources factor ideal A. Matsuzawa,Titech

13 0 and P d at low voltage operation 3 apacitance should be larger at low voltage operation to keep sufficient SNR. This results in rapid increase of power dissipation. f c s _ pp GBW Low voltage doesn t make sense for pipeline AD. g m 0 eff 0 I D eff s _ SNR kt P d 0 pp 0 I D kt 0 f c eff eff f c 0 T SNR kt SNR eff eff eff 0 (F) eff P d (W) 0 0. bit, 00MHz AD P d eff dd dd A. Matsuzawa,Titech

14 FoM: Figure of Merit of AD 4 FoM stands for consumed energy normalized by the effective steps. Low voltage operation for OpAmp based AD increases FoM. FoM ( J ) f c P d ENOB P d f c ENOB N P d 30Nf c n kt N ENOB eff eff FoM 30 n kt ENOB ENOB eff eff ENOB :Degradation from ideal 0 FoM (J/conv. steps) 0 bit, 00MHz AD () A. Matsuzawa,Titech

15 5 omparator based AD design : SAR AD A. Matsuzawa,Titech

16 Basic idea for low energy analog design 6 onventional analog circuits consume larger energy. Dynamic circuits doesn t consume larger energy. MOS: onsumed energy is independent of delay time. ML, OpAmp R L R L o- o+ L L i+ i- f P togle d I I s s L i R O MOS L o P d f E togle d fe T d r L R f o L L I s f togle P d L f togle R o L A. Matsuzawa,Titech

17 SAR AD 7 in SAR can be designed to consume no static power. SAR can realize larger signal swing compared with pipeline AD. 4 apacitors S S S 3 S 4 S 5 S N A S 0 omparator Switches ref ref in Logic Sample Generating subtracted signal E n Q in N A x n Not OpAmp based, but comparator based No resistors No static current! Potentially full swing x ref sig 0 n n ref A. Matsuzawa,Titech

18 Performance overview of SAR ADs 8 FoM has lowered rapidly due to the progress of SAR AD. /00 during three years. FoM trend of 0bit AD 000 FoM (fj/conv. steps) 00 0 Recent FoM range several 0 fj / conv. steps A. Matsuzawa,Titech

19 Issue of comparator for SAR ADs 9 A comparator has noise and this results in conversion error. 5b harge Redistribution (R) SAR AD ref INp b0 b b b3 b4 OK! in INp INn 0/ SAR 7 ref LK Noise Distribution INn INp 0 b0 b b b3 ERROR! b omparator Threshold INn 0 0. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. van der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant Dynamic-SAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.38-39, Feb A. Matsuzawa,Titech

20 Dynamic comparator 0 A dynamic comparator is widely used to reduce static power. The difference in input voltages causes a difference in discharging speed. FN INP i LK FP I INN D I D i L LK L SN SP LK LK D. Schinkel, E. Mensink, E. Klumperink, Ed an Tuijl, B. Nauta, A Double-Tail Latch-Type oltage Sense Amplifier with 8ps Setup-Hold Time, ISS Dig. of Tech. Papers, pp.34-35, Feb., A. Matsuzawa,Titech

21 Deriving noise equation i g m i Transistor noise S in I D L L Sampling noise ) Sampling noise of Switch v v d kt n k n, δt L I D L T I L D ) Transistor noise Equivalent circuit td t I L D v Noise voltage of output by current noise L v n L t d 0 i n dt L t d vn I D I D t d 0 i ndt / t d time i n t d oltage and timing TR noise kt L dd I ds eff A. Matsuzawa," IEEE 8th International onference on ASI(ASION), pp. 8-, Oct A. Matsuzawa,Titech t d δ in eff δ 4kT td eff dd αγ α td α Ldd eff

22 Match with noise simulation The derived equation has a good match with simulation. δ in 4kT eff dd αγ α Ldd eff Noise in comparator P (out=high) [%] in kt L eff δin(σ) [m] Estimation(α=) Estimation(α=) Simulation Δin [m] L [ff] A. Matsuzawa,Titech

23 Required capacitance and consumed Energy 3 Node capacitances should be increased to realize higher AD resolution. This results in increase of consumed energy of the dynamic comparator. Flash AD: E c determines the minimum FoM SAR AD: E c cannot be neglected for higher resolution AD =, eff =0. E c : conversion energy L (ff), E c (fj) E c L ff & 40fF & 0.6pF & 0pF & Resolution (bit) A. Matsuzawa,Titech

24 Noise improvement of dynamic comp. 4 Noise of comparator can be reduced by complementary ckt. and an optimization of the node capacitance. Dynamic comparator Noise of comparator Offset AL MOS input dd 4.0 onventional LK W Pa W Pb W Nb W Na INP_a INP_b INN_b INN_a Gate weighted interpolation outp outn n( ) [m] Proposed cm [] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low-Noise Self-alibrating Dynamic omparator for High-Speed ADs," A-SS, Nov nm MOS A. Matsuzawa,Titech Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, and Akira Matsuzawa, "A 6bit, 7mW, 50fJ, 700MS/s Subranging AD," A-SS, 5-3, pp. 4-44, Taiwan, Taipei, Nov. 009.

25 P d estimation of SAR AD 5 Divide SAR AD into three different circuits. s N ) S/H&DA ) omparator p ds fcs p dc N f c L apacitors omparator Logic L N 3 Switches ref in ) Logic gates and switch drivers p dc Nfcg g : const Akira Matsuzawa, ISS Forum, San Francisco, A, Feb A. Matsuzawa,Titech s : Total sampling capacitance L : Load capacitance of comparator g : Effective capacitance of gates and switches

26 Equations to estimate the AD performance 6 Quantization voltage q 3 N Permitted thermal noise ENOB n _ th q Thermal Noise of OMP. 4kT n _ th L eff eff Sampling capacitor P d of S/H P d of OMP. P d of Gate p p p s ds dc dg 4kT n _ th f cs N f c L Nf cg Load apacitor Of OMP. L 4kT FoM n _ th P ds eff P dc f c eff P dg N ENOB A. Matsuzawa,Titech

27 , P d, and FoM vs. 7 Sampling capacitance s and load capacitance L increase with reducing, since the quantization voltage decreases with reducing. P d of S/H is constant for, however P d of comparator increases with reducing. P d of logic gate decreases rapidly with reducing. s, L (F) 0 0 L s L dd () s P d (W) omp g =0.3pF P dc g =0.pF Pdg P ds const dd () Logic S/H A. Matsuzawa,Titech

28 FoM vs. 8 FoM can be lowered by reducing, if P d of logic gate is dominant. Thus the voltage lowering is effective to reduce P d for low resolution AD, However, it is still difficult to reduce P d by reducing for high resolution AD, even if SAR AD architecture is used. 0 4 FoM (J) Gate dominant OMP dominant dd () g =0.3pF g =0.pF N bit F c 00MHz ENOB 0.5bit T 300K 0.5 eff A. Matsuzawa,Titech

29 Example: An ultra-low power D 9 We have developed an ultra-low power apacitance to Digital onverter.. 0b SAR like architecture. Self-clocking 3. Single to differential 30 times/sec Tuan Minh o,yasuhide Kuramochi, Masaya Miyahara,Takashi Kurashina, and Akira Matsuzawa A 0-bit, 90 fj/conv. Steps, 0.3mm, Zero-Static Power, Self-Timed apacitance to Digital onverter. SSDM 009, OT A. Matsuzawa,Titech

30 Self clocking technique 30 Self-clocking scheme is very useful ) Reducing power consumption (lock circuits, routing clock, ) ) Just an enable command signal is required. No need of clock. Suitable for micro controller. omparison is ended if the output voltages are not same. Output voltage of dynamic comparator Self-clocking scheme b A. Matsuzawa,Titech

31 3 Flash and sub-ranging ADs A. Matsuzawa,Titech

32 Flash AD 3 Expecting highest speed omparator determines the AD performance omparator Array Flash AD 6b: 63 q FS N N 6 Offset mismatch mainly determines the effective resolution. Thermal noise can be neglected because of low resolution. 6b: 63 FS =.0 q =6m, Mismatch <3m 0 0 Offset mismatch A. Matsuzawa,Titech

33 FoM of Flash AD 33 FoM of flash AD is determined by energy consumption of unit comparator and the degradation of effective bit. Reduction of consumed energy and increase of ENOB are very important. FoM P E N d c s ENOB E ENOB N ENOB c f s f s f E c E c : Energy/omparator ENOB log off ( ) q n( ) q Offset mismatch Thermal noise (can be neglected) A. Matsuzawa,Titech

34 Performance of flash AD 34 FoM is degraded by the offset mismatch voltage of the comparator. Offset mismatch voltage should be reduced at low voltage operation. ENOB [bit] ENOB FoM log P d f c ENOB N off ( ) q off (): Offset mismatch q : LSB voltage A. Matsuzawa,Titech

35 Tradeoff: mismatch and energy consumption 35 Serious tradeoff between mismatch of transistor and gate area. Larger transistor is required to reduce mismatch voltage and results in increase of gate area and consumed energy. Example Offset mismatch (m) m 0 Mismatch compensation E c =50fJ Transistor size (um ) オフセット消費電力 E c (fj) 6bit AD: off <3m E <50fJ0.um off =0m Needs mismatch compensation 0m 3m o ffset ( ) LW E c E c c offset LW A. Matsuzawa,Titech

36 FoM vs. Area 36 Occupied area should be reduced to lower the FoM. We must pay much attention to the occupied area. 0 E c Area FoM (pj/conv.step) 0. 5bit and 6bit ADs Area (mm ) A. Matsuzawa,Titech

37 Digital calibration methods for mismatch 37 Resistor ladder type apacitor array type Binary weighted capacitor array Y. Asada, K. Yoshihara,T. Urano, M. Miyahara and A. Matsuzawa, A 6bit, 7mW, 50fJ, 700MS/s Subranging AD A-SS, pp. 4-44, Nov A. Matsuzawa,Titech

38 Effect of digital mismatch compensation 38 The mismatch voltage can be reduced from 4m to.7m. Measured result offset offset offset M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low- Noise Self-alibrating Dynamic omparator for High-Speed ADs," A-SS, Nov A. Matsuzawa,Titech

39 Area comparison 39 Penalty area for digital compensation will be reduced with technology scaling. 4.5 m 5 m 30 m omprator 90 m Strage apacitor & harge Pump 0 m 5 m 30 m 30 m omprator Decorder Register 4b MUX 85 m Resistor ladder 90 nm 5 m 5 m 0 m 30 m apacitor array omprator AP Array 65 m Register 4b.9 m 9 m omprator &ap Array m UpDownounter 5b apacitor array 40 nm 4 m A. Matsuzawa,Titech

40 Issue of resistor DA to generate REF 40 IN ref Resistor DA consumes static power and has a serious tradeoff between Pd and speed. max R 4 T/H R on pr 4I ref ref R on pr τ oarse scale I Fine scale Upper bit 7 7 Lower bit 7 Previous fine scale 7 t LATH t DA A. Matsuzawa,Titech oarse conversion t LK Fine conversion

41 4 Advantage of capacitor DA to generate REF apacitor DA doesn't consume static power and has no trade off between Pd and speed. out IN n REF R on p E tot d Operating as S/H circuit No static power consumption ( 360W@GHz ) Smaller u realize faster settling time (t DA = 3.4 r on U < r ON = k, U = 5fF) A. Matsuzawa,Titech

42 Settling time and power 4 DA realizes faster settling time to RDA with low power consumption DA DA DA RDA α=0.5 vout(da) α=5 vout(da) α=0 vout(da) RDA time [ps] Time response Power dissipation A. Matsuzawa,Titech

43 6bit sub-ranging AD using DA 43 6 bit AD has been realized in a 90 nm 0MP MOS technology with a chip area of 0.3mm Y. Asada, K. Yoshihara,T. Urano, M. Miyahara and A. Matsuzawa, A 6bit, 7mW, 50fJ, 700MS/s Subranging AD A-SS, pp. 4-44, Nov A. Matsuzawa,Titech

44 Performance comparison 44 Attain lowest FoM at that time [] [] [3] [4] [6] This Work Resolution(bit) fs(gs/s) SNDR(D/Nyq.) 35/3 34/33 3/30 34/8 35/33 35/34 Pd (mw) Active area(mm ()...../.0. FoM(pJ) MOS Tech.(nm Architecture Flash Flash Pipeline b-sar Subrange Subrange [] -Y. hen, LSI ircuits 008. [] B-W. hen, A-SS 008. [3] F.. Hsieh, A-SS 008. [4] Z. ao, ISS 008. [6] Y.. Lien, A-SS A. Matsuzawa,Titech

45 oltage lowering: FoM vs. 45 FoM can be reduced drastically by reducing supply voltage. ENOB is degraded by the reduction of, however little affects the FoM. Energy reduction by reducing is dominant. ENOB ENOB (bit) FoM (fj) E c (fj) off ( ) = 6m E ENOB c c log off ( ) q I c exp S fc T FoM E c ENOB E c :Energy consumption for each comparator and followed logic circuits. () A. Matsuzawa,Titech

46 FoM delay (FD) product 46 The FD product suggests the balance between the number of interleaving and decrease of energy consumption. Delay is increased and the operating speed is lowered by reducing We should investigate the optimum by FD product. T = 0.4 FD FoM Delay Delay time Optimum range T d k T A. Matsuzawa,Titech

47 Forward body biasing 47 Forward body biasing can decrease the delay time (/) and can be used easily at 0.5 operation. 0 8 W/O FBB BB IN TP = 60m OUT / W/ FBB (0.5) FBB Supply voltage () TN = 00m Increased leakage current in the proposed AD is 0.3 ma by forward body biasing A. Matsuzawa,Titech

48 AD Structure 48 5bit MSps Flash AD is designed and fabricated in 90nm MOS. S/H circuits use gate boosted switches. Block diagram of AD hip microphotograph A. Matsuzawa,Titech M. Miyahara, J. Lin, K. Yoshihara, and A. Matsuzawa, A 0.5,.mW, 60fJ, 600 MS/s 5 bit Flash AD A-SS, pp , Nov. 00.

49 Performance Summary 49 A high speed and low FoM 0.5 flash AD has been realized. Reference # [7] [8] [9] [0] This work Resolution (bit) fs (GS/s) SNDR (db) Pd (mw) Active area (mm ) dd () FoM(fJ) MOS Tech. (nm) Architecture SAR Fold+Flash Flash Flash Flash [7] B. P. Ginsburg, J. Solid-State ircuits 007. [8] B. erbruggen, ISS 008. [9] B. erbruggen, LSI ircuits 008. [0] J. E. Proesel, I 008. FoM Fmax = 600MSps FoM Best = 0 360MSps A. Matsuzawa,Titech

50 Summary of energy efficient AD design 50 Reducing static power Reducing capacitance E d T n Reducing voltage G Resistor DA apacitor DA OpAmp based omparator based # of MP TR size Noise lock A. Matsuzawa,Titech Flash Sub-range SAR Large TR Small TR with compensation Use complementally ckt. Use self clocking Effective to digital gates and low resolution AD Use forward or adaptive body biasing