Introduction to Embedded Data Converters

Transcription

1 Introduction to Embedded Data onverters Akira Matsuzawa Tokyo Institute of Technology VLSI symposia 006, A. Matsuzawa, Tokyo Tech.

2 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. ontents. Introduction. haracterization of data converters 3. Overview of high-speed A/D converters 4. Overview of high-speed D/A converters 5. Overview of over-sampling sigma-delta data converters 6. Basic design considerations

3 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 3. Introduction Mixed signal systems Software defined radio Digital read channel Mixed Signal So Progress of AD and DA Power and area Embedding

4 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 4 Basic mixed signal system Mixed signal systems basically consist of DSP, AD, DA, and pre/post filters. The signals are converted between continuous time and discrete time. ontinuous time =Analog Discrete time =Digital ontinuous time =Analog AG Pre Filter AD DSP DA Post Filter lock

5 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 5 Software defined radio Future wireless systems need powerful AD and DA for software defined radio. Future cellular phone needs wireless standards!! Multi-standards and multi chips IMT-000 RF IMT-000 BB urrent GSM RF GSM BB Bluetooth RF Bluetooth BB MU GPS RF GPS BB Power Yrjo Neuvo, ISS 004, p.3 Multi-bands and Multi-standards on a single chip Mixer RF filter LNA X Filter AD Future On a chip Frequency Synthesizer DSP PA Filter X Filter DA Mixer

6 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 6 Mixed signal tech. ; Digital read channel DVD Digital storage needs high speed mixed signal technologies. For the reduction of error rate, high speed AD is the key. Variable Variable Gain Gain Amp. Amp. Analog Analog Filter Filter A to to D onverter onverter 7b 400MHz Digital Digital FIR FIR Filter Filter Viterbi Viterbi Error Error orrection orrection Data Out Data In (Erroneous) Pickup signal Voltage Voltage ontrolled ontrolled Oscillator Oscillator lock lock Recovery Recovery Analog circuit Digital circuit Data Out (No error)

7 Mixed signal So Mixed signal So can realize full system integration for DVD application. Embedded analog is the key. 0.3um, u 6Layer, 4MTr PU System ontroller VO AD PU Front-End Analog FE Digital R/ PRML Read hannel Servo DSP AV Decode Processor Pixel Operation Processor IO Processor Gm- Filter Back -End Analog Front End Okamoto, et al., ISS VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 7

8 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 8 Progress of high-speed AD High speed AD can be embedded in MOS resulting in power reduction. ISS 99 ISS 000 ISS 00 6b, GHz AD W,.5um Bipolar Matsuzawa, ISS 99 6b, 800MHz AD 400mW, mm 0.5umMOS Pd/ N Gsps [mw] Sushihara, et al, ISS World lowest Pd HS AD 7b, 400MHz AD 50mW, 0.3mm 0.8umMOS Pd of high speed MOS ADs 0mW/ N Gsps This Work mw/ N Gsps /8 0 onversion rate [x00msps] Sushihara and Matsuzawa, ISS 00

9 Progress of A/D converter; video-rate 0b AD /000 in Power and /00,000 in cost during past 0 years AD was the bottle-neck for the digital TV and Video systems Technology progress has solved this problem Now onventional product World st Monolithic World lowest power So ore Board Level (Disc.Bip) 0W $ 8,000 Bipolar (3um) W $ 800 MOS (.um) 30mW $.00 MOS (0.5um) 0mW $0.04 T. Takemoto and A. Matsuzawa, JS, pp.33-38, 98. K. Kusumoto and A. Matsuzawa, ISS VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 9

10 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 0 Power and area reduction of video-rate 0b ADs Power and area of AD have been reducing continuously. urrently, AD can be embedded on a chip Power (mw) Power reduction Flash Two-step 000 Subranging 000 Folding/Interpolating 500 Pipeline 00 Look-ahead Pipeline 00 Others Year Area size (mm) Area reduction 00.0 Flash 50.0 Two-step 0.0 Subranging Folding/Interpolating 0.0 Pipeline 5.0 Look-ahead Pipeline Others Year

11 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. Power and area reduction of video-rate 0b ADs Power/MHz (mw/mhz) Flash 5.0 Two-step.0 Subranging.0 Folding/Interpolating Pipeline 0.5 Look-ahead Pipeline 0. Others Process node (μm) Area size (mm) Flash.0 Two-step Subranging.0 Folding/Interpolating 0.5 Pipeline 0. Look-ahead Pipeline Others Process node (μm) M. Hotta et al. IEIE 006. June

12 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. Embedding AD on a MOS chip MOS AD and DA has been embedded on a MOS chip. This has realized low cost and low power digital portable AV products. 993 Model: Portable VR with digital image stabilizing 6b Video AD Digital Video filter A. Matsuzawa, JS, pp , 993. System block diagram 8b low speed AD;DA 8b PU

13 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 3. haracterization of data converters Basic functions of AD and DA Static performance INL, DNL, monotonicity Quantization noise Dynamic performance SNR, SFDR, THD, SNDR, ENOB Sampling Jitter ERB Glitch Figure Of Merit Performances and applications Needed performances for wireless systems

14 Basic functions of AD Sampling: Sampling the analog signal with accurate timing. Quantization: Express the converted data with certain accuracy. Sampling Quantization Voltage Voltage Time Time Analog Sampling AD Quantization oding Digital oding LK VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 4

15 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 5 INL: Integrated Non-Linearity Static performance INL and DNL are the major static performance indicators of AD and DA. DNL: Differential Non-Linearity INL DNL j INL j DNL j Width Transfer j = k = j k = 0 = INL DNL j k ATUAL, j Width function INL j Width IDEAL ATUAL, j IDEAL Transfer fuction IDEAL, j

16 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 6 DNL and INL DNL profile INL profile

17 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 7 Monotonicity in DA Binary coded DA often degrades monotonicity. The monotonicity stands for the qualitative characteristics of data converters of which transfer function keep the monotonic increase or decrease. At the change of MSB bit 0->0000 Binary weight /3 /6 If the converter can not guarantee the monotonicity, The feedback loop doesn t work properly and results in backrush. Out Out /8 / / / Large DNL In In /4 /4 /8 /6 /3 Keep monotonic Degrade monotonicity

18 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 8 Quantization noise Quantization causes noise Higher SNR needs higher resolution Quantization noise P n Transfer characteristics Δ / Δ / = e P( e)de = Δ / Δ / QP( e) = Δ, 0,all other e e e de Δ Δ < Δ = P s = SNR SNR N ( Δ ) db P P s n = N ( Δ ) P = 0log P s n =. 5 Δ N = 6. 0 N. 76

19 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 9 Dynamic performance Dynamic performance indicates the ratio between signal and noise or distortion. We should use the suitable terms depending upon the type of application. SNR = 0log Signal power Total noisefloor power SFDR = 0log Signal power L arg est spurious power THD = 0log Total harmonic distortion power Signal power SNDR = 0log Signal power Noise and distortion power ENOB = SNDR F c =40MHz, f in =4MHz SFDR=49.8dB SNDR=44.9dB, ENOB=7.7-bit ndhd=-49.8db, 3rdHD=-56.7dB

20 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 0 Sampling jitter effect Sampling jitter is converted to noise. When the input frequency becomes higher, the SNR becomes lower. SNDR( db ) = 0 log ( π σ ) f in t Input signal V sig Δ V = ΔV dvsig dt σ t ( ) (, σ t ) (, σ t ) (, σ t ) (, ) SNDR 0 0 6, σ t SNDR SNDR SNDR SNDR σ t 40 t t 0 σ t Time σ t

21 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. Effective Resolution Bandwidth ERB is the input frequency where the SNDR has dropped 3dB (or ENOB 0.5 bit) 6 ENOB (bit) 5 4 3dB (0.5bit) down SNDR SNR ERB Input frequency (MHz) 300

22 State : [000]=8 State : [0]=7 I/ I/4 I/8 I/6 I/ I/4 I/8 I/6 Glitch Glitch is the spiky signal at code transition. aused by overlapping of signals This appears within a few psec, However, energy is not negligible. Glitch causes the distortion of signal Glitch 5 P P T g,max g,max g X g = < P N QN T < 3 s N T Δ T Δ = g s Intermediate: []=5 8 I/ I/4 I/8 I/6 urrent T g 7 Time VLSI symposia 006, A. Matsuzawa, Tokyo Tech.

23 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 3 Figure Of Merit Figure of merit shows energy efficiency for data conversion. FOM or = = = Energy onversion step Power ENOB f Power ENOB s BW Power[mW] High Speed AD [Sampling Freq. VS Power] Sampling Freq.[MSps] b 0b JSS,ISS,VLSI,I,ESS & Products ( 0Bit, 0MSps) bit 0.3 mw /MHz 0.5 pj /conv bit mw /MHz Bit(Paper) 0.8 pj /conv 0Bit(Paper) Bit Products 0Bit Products.

24 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 4 Performance and application Needed resolution and conversion rate depending upon the application. 000 onversion Rate (MHz) HDD/DVD Servo Graphics General Purpose (µ-omputer) Video/ ommunication DV/DS/Printer Automobile Audio Meter Resolution (bits)

25 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 5 Needed SNR for certain BER in wireless system Lower Bit Error Rate in the digital modulation needs higher SNR. 6QAM Q n-psk BER erfc SNR sin π n A 0 n-qam BER n erfc SNR ( n ) I 0. QPSK 6QAM 56QAM Noise distribution 0 BER q ( SNR, 6) BER q ( SNR, 64) BER q ( SNR, 56) BER p ( SNR, 4) QAM BER SNR

26 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 6 BER requirement The lower the bit error rate the higher the required AD/DA resolution. Resolution (quantization noise) affects BER. DA requirement for QAM AD requirement for digital read-channel

27 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 7 Signal intensity in wireless system Wireless system has strong unwanted signals. Also, electric circuits generate distortion and noise. Filter A A B Amp. AD Intensity (db) Filter Adjacent signal Wanted signal Far signal B > Needed SNR > Needed dynamic range to the blocker Due to aliasing Due to distortion of AD Thermal noise Thermal noise Frequency Thermal Noise Quantization noise

28 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 8 Needed AD dynamic range Existence of strong blockers results in the need for high dynamic range AD. 5dB Blocker signal Wanted signal -97dBm DS800-6dBm AD dynamic range =86dB (4b) Quantization noise Thermal noise 0dB Quantization noise Adjacent channel Wanted signal -93dBm 8dB -33dB WDMA -5dBm Filter attenuation -85dB AD dynamic range =36dB (6b)

29 VLSI symposia 006, A. Matsuzawa, Tokyo Tech Overview of high-speed A/D converters Performance and AD architecture Integrating AD Successive approximation AD Flash AD Sub-ranging AD Interpolation method Folding AD Pipelined AD

30 AD performance and architectures There are many conversion architectures with varying performance parameters. 0G onversion frequency (Hz) G 00M 0M M 00k Flash Sub-range Successive approximation Pipeline 0k Resolution (bit) Multi-bit sigma-delta Single-bit sigma-delta Integrating VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 30

31 Integrating AD Integrating AD achieves high resolution, but at low speed. Recently it has been used as column-ad in MOS imager. S -v in omparator v ref R v x Water clock -v in PhaseⅠ v ref PhaseⅡ -v in v ref High resolution (0bit and more) Very low speed (D measurement) Small DNL an realize zero offset voltage Small analog elements and area v x v in 大 0 T Time Going to 0 ->, when V x becomes negative. v ( v ) T x (T ) = = in dτ 0 R VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 3 v in R T

32 Successive-approximation AD V in Successive-approximation method is based on a binary search. S/H omparator Successive-approximation resistor and control logic Balance b b b 3 B out V DA Binary search DA V ref V FS V in MSB LSB b b b 3 b 4 b 5 b 6 V DA V FS V in V FS 4 V FS V FS 8 V FS V FS V 8 FS V 6 FS MP in b = b = b =0 b = b 3 = b =0 b = b 3 = b 4 = b =0 V VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 3

33 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 33 harge-redistribution AD harge-redistribution AD draws attention as a suitable AD in the nanometer MOS era. Because it needs no OP-Amp, but just needs capacitors and comparator. ) Sampling V x =0 Q=-V in Binary weighted apacitor array V in V ref ) Hold V x =-V in Q=-V in V in V ref

34 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 34 harge-redistribution AD 3) harge redistribution V x =-V in V ref/ Q=-V in If needed Determine from MSB V in V ref V ref Resistor ladder for higher resolution Higher resolution Ultra low power Low conversion rate Easy calibration No OP amp Needs multi clock

35 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 35 Flash AD Flash AD is very fast, but area and power increase exponentially with resolution. R/ V DD v in Φ Ultra fast operation: Several GHz No sample and hold Low resolution: <8 bit Large input capacitance difficult to drive Scale R R R R R R R R/ omparator Encoder Digital out V ref N Input voltage V ref 0 D D D 3 D 4 D

36 Sub-ranging AD Multi-step conversion can reduce the # of comparators. However, it needs high precision comparators. As a result, small power and area. 0bits : Flash; N twostep; = 03 N = 6 Slide gauge Upper conversion 4 Lower conversion GND Input voltage VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 36

37 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 37 Interpolation method Interpolation can generate accurate intermediate references which are between two references. Thus step sizes are almost equal, even though mismatch voltages are large. Step size Mismatch voltage Step size Small DNL K. Kusumoto and A. Matsuzawa JS, pp , 993.

38 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 38 Folding AD Input signal is folded to the compressed signals of which phases are different. Lower bits are obtained by comparing between these folded signals. Low power and small size, yet still high speed. However, not suitable for higher resolution. <0bit Upper bits AD v in Folding ircuits Folding ircuits Folding ircuits omp omp 3 omp Lower bits Logic Folded signals Parallel Folded signals Folding ircuits omp 4 Analog signal Digital signal Input signal The signal is compressed The # of comparators can be reduced

39 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 39 Folding circuits omposing the folding characteristics by the summation of currents from differential transistor pairs. Output voltage V DD Output voltage V DD V DD V DD V Input voltage V in urrent summation V V V 3 V 4 Input voltage v out V out V V V 3 V 4 V in V v in

40 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 40 Pipelined AD Pipelined AD is the centerpiece of embedded ADs for many applications, such as digital cameras, digital TVs, ADSLs, VDSLs, and wireless LANs. v in MSB Suitable for MOS Switched capacitor operation M-bit DAP DAP DAP DAP LSB High resolution(<5bit) Moderate speed(<00mhz) Low power consumption MSB V ref nd V ref -V ref 0 V ref -V ref 0 0 V ref S/H AD (M bit) Digital Approximater (DAP) X -V ref X -V ref DA M (M bit) onventional M is or.5 Amplifier

41 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 4.5-bit/stage Pipeline AD Amplification at each stage reduces the input referred thermal noise..5b/stage architecture reduces the requirement for the comparator offset drastically. Transfer characteristics V R S f V i V R 4 V R LATH MUX V R -V R s S 3 SUB-AD DA X GAIN - V o -V R s Vi f i f V ref -V R if Vi V < 4 ref V R Unit conversion stage for.5-bit/stage pipeline AD V o = s f V s Vi f i i f V ref if V 4 ref V if Vi > 4 V ref i V 4 ref

42 Pipelining Pipeline action relaxes settling time requirement. Sample & Hold st stage nd stage f f Op amp Op amp Op amp s s MP DA MP DA st stage Sample Amp. Sample Amp. nd Stage Sample Amp. Sample Amp VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 4

43 VLSI symposia 006, A. Matsuzawa, Tokyo Tech Overview of high-speed D/A converters Basic two concepts of DA Binary method R-R based DA apacitor array DA Decoder method Resistor string DA urrent steering DA

44 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 44 Basic two concepts of DA. Binary method. Decoder method Not small DNL Large glitch V Small area V ref ana lg N = Vref i = i D i Small DNL Small glitch Large area V ana lg = V V ref q N i = 0 i D i D 3 D D Digital Binary Weight ckt. Analog D 3 D D Digital Decoder Switch matrix Analog

45 Binary method R-R based DA R-R resistor ladder can generate binary weighted current easily. Resolution: b Large DNL Small area at high resolution Moderate speed Large power consumption A 0 A A A 3 R F v out R R R R Virtual ground -v ref R R R R v out = RF Ir A vref Ir = R 0 Ir A I VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 45 r A I r 3 A

46 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 46 Binary method apacitor array DA apacitor array DA is widely used in MOS technology. Q v out = v Low power and no sample & Hold ref [ A A 4 A 8 A ] Q = Virtual ground 6 A i = 0 or Reset 8 4 v out v ref Enable Q v out A 3 A A A 0 v ref

47 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 47 Decoder method Resistor string DA Decoder method can realizes small DNL, however needs large area at high resolution R R R R R R R R V ref Resolution limit: 0b Good DNL Low speed Small glitch Decoder V out large parasitic capacitance: N Digital value

48 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 48 Decoder method urrent steering DA Widely used for high speed DA. Graphics, communications, etc. High speed, -- GHz Resolution 4 b Small DNL Small glitch V out onventionally large area V DD R D i = V out D i Bias D i Row decoder urrent source D i =0 urrent cell with switch olumn decoder

49 VLSI symposia 006, A. Matsuzawa, Tokyo Tech Overview of over-sampling sigma-delta data converters Sigma-delta modulation method Over sampling Noise shaping Sigma-delta modulator SNR Higher order system Feed forward and feed back compensation MASH (Multi-stage noise shaping)

50 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 50 Sigma-delta AD, DA Sigma delta AD and DA are widely used in high resolution (4b-4b) and not high speed ( <MHz) applications. x(n) Sigma delta AD Integrator z - Analog omparator bit DA Digital Filter Digital Digital Signal Processing Sigma delta DA AVDD LPF DA out v in Integrator Φ Φ Φ Φ Implemented in MOS, easily. v ref v ref bit DA

51 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 5 Over sampling Over sampling can reduce effective quantization noise. Band limiting filter x(n) Δ y (n) H(f) y (n) Quantization noise power P e f / s = Se ( f ) H( f ) df = f s / f b f b Δ h e (x) f s df H(f) Δ f = f s b Δ = OSR Total noise power is invariant f s OSR f b f -f s / -f b f b f s / In-band noise Reduction of bandwidth by filter Reduction of effective noise power

52 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 5 Noise shaping Spectrum of quantization noise is shaped by differentiator. In-band noise can be reduced. Input signal Integrator Quantizer Differentiator Output signal Signal intensity Low pass filter Noise High pass filter Noise Noise BW f Signal: Low pass filter x High pass filter Flat Quantization noise: High pass filter Lower in low frequency Only quantization noise is shaped in frequency characteristics f S In-band noise is reduced f S The spectrum of the quantization noise increases with frequency increase.

53 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 53 Sigma-delta modulator Sigma-delta modulator shapes the frequency characteristics of the quantization noise X(z) X(z) Integrator z The signal will overflow Equivalent transform Integrator Quantizer Q(z) X( z ) z Differentiator Quantizer Q(z) Differentiator z Y ( z ) = Output signal Y(z) Y(z) X( z ) Input signal ( z )Q( z ) Differentiator (High pass filter) Quantization noise z X Q Z z Y ( z ) = X( z ) ( z )Q( z ) No overflow

54 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 54 Generic expression of sigma-delta modulator We can use not only LPF but also BPF and complex BPF. This gives us an excellent opportunity for wireless applications. Input signal X(z) Filter H(z) Quantizer Q(z) Output signal Y(z) z H( z ) Y ( z ) = X( z ) H( z )z H( z )z Q( z ) Ex. H( z ) STF (Signal Transfer) NTF (Noise transfer) = z STF( z ) =, NTF( z ) = z No filter High pass filter

55 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 55 Noise power in sigma-delta modulator L th order filter f b 0 Y ( z ) = X( z ) ( ) L z Q( z ) -0 SNR = 3.8dB -40 h N q q ( = f f b b f ) Δ = f fb L hq ( f ) z f z = e b Δ f s jπf f s s L df j πf / fs Δ = 3π ( L ) dbfs π OSR Digital Filter fs=6mhz Frequency (MHz) L

56 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 56 nd order sigma-delta AD X ( z ) Y ( z ) - DA z z z Q( z ) Q( z ) X ( z ) Y ( z ) - - DA DA st order SD AD st order SD AD z z Q ( z ) Quantizer is replaced by st order SD AD z ( z ) Q ( z ) Y ( z ) = X( z ) Q ( z ) Y ( z ) = X( z ) = ( z ) Q( z ) ( ) z Q( z ) X ( z ) Y ( z ) z z DA - - DA nd order SD AD

57 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 57 Multi bit sigma-delta AD X( z ) z DA z - - DA z DA z - - a a a a 3 4 DA Y ( z ) Feedback type NTF( z ) = ( z ) 4 X( z ) - DA z z z z z z b b b 3 b4 Y ( z ) Feedforward type

58 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 58 Dynamic range of sigma-delta AD Higher order SD modulator seems effective to increase the dynamic range. However it is not easy, because of instability, signal saturation, and thermal noise. Dynamic Range (db) DR 3π = n=bit N ( ) ( L ) OSR π 5 th L 4 th OSR 3 rd nd st

59 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 59 Noise-shaping characteristics Higher order sigma-delta modulator can realize higher dynamic range, theoretically. 0 0 SNDR = 99.5dB -0-0 SNR = 00.dB dbfs st order dB/dec nd order 40dB/dec fs=6mhz Frequency (Hz) Dynamic Range (db) th order, bit 00dB/dec Thermal noise In-band OSR=64 00kHz Frequecy (Hz)

60 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 60 ascade (MASH) sigma-delta modulator ascaded SD modulator can realize higher order noise shaping without stability issues. However, high dynamic range is difficult, due to severe mismatch requirement. X( z ) z z - - Q ( z ) DA - z - DA Q ( z ) Y Q Y ( z ) H ( z ) Q ( z ) Y ( z ) H ( z ) Y ( z ) ( z ) Q ( z ) ( z ) Q ( z ) Y( z ) = X( z ) Y( z ) = Q ( z ) H ( z ) = H ( ) ( z ) = z 3 ( z ) Q ( z ) ( z ) Q ( z ) ( z ) Q ( z ) Y ( z ) = YH YH = X( z ) 3 ( z ) Q ( z ) Y ( z ) = X( z )

61 VLSI symposia 006, A. Matsuzawa, Tokyo Tech Basic design considerations Accuracy urrent mismatch and DA accuracy V T mismatch apacitor mismatch omparator Offset compensation Op-Amp Gain and GBW kt/ noise

62 urrent mismatch and DA accuracy Larger resolution requires smaller mismatch. I Δi 0 I Δi I Δi I Δi N INL yield 0. 0% 50% σ( I I ) N sigma ( 3.0, N) sigma (, N) sigma (.3, N) % 99.7% N: resolution sigma ( 0.8, N) : constant determined by INL yield N Van den Bosch,.. Kluwer VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 6

63 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 63 V T mismatch Larger gate area is needed for smaller V T mismatch. Technology scaling reduces V T mismatch if the gate area is equal. ΔV T (mv ) 00 δ VT ( LW) 0 0 ΔV T T ox LW δ VT ( LW) δ VT ( LW) 0.4um Nch 0.3um Nch Boron, w. Halo 0.3um Nch In w/o Halo* LW LW ( μm )

64 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 64 Mismatch current and transistor size ( ) T gs ds V V L W K' I = = L W L W I K' K' I V V I I ds ds T T ds ds Δ Δ Δ Δ = L W L W K' K' V V V I I T gs T ds ds Δ Δ Δ Δ WL K' VT T L W A L W L W LW A K' K' LW A V = Δ Δ Δ = L W K' I V V ds T gs Mismatch WL K ds VT ds ds L W A WL A I L A 4K' I I = Δ Smaller mismatch requires larger L and W.

65 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 65 apacitor mismatch Smaller capacitor mismatch requires larger capacitance Δ (3σ ) = ( pf ) Typical MIM capacitor oefficient depends Fab. 0bit: 0.4pF bit: 4pF 4bit: 40pF Δ ( 3σ ) 0bit, ¼ LSB bit, ¼ LSB 4bit, ¼ LSB apacitance (pf)

66 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 66 MOS comparators There are many types of comparator circuits

67 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 67 Low power MOS comparators MOS comparator are low power because of the lack of static current. LK No static current Differential comparison Interpolation action High speed T.B.ho., et al., J.S.., Vol.30, No.30, pp.66-7, Mar V DD V in mm9 m5 m7 m0 m8 m6 m m m3 m4 W W W W m Out Out- G G = K = K p p W L W L Interpolation action m n ( V V ) ( V V ) in ( V V ) ( V V ) V in V in- V in- if W : W = : m m then, ( m n ) Vin nvin = ( m n ) Vin nvin in n th th W L W L in in th th V SS

68 Design rule and Speed in omparator Gain bandwidth (=Speed) is inversely proportional to the L (channel length). Technology scaling is still effective in increasing the comparator speed, if we are not concerned with the signal s dynamic range. GBW I = π W sin k = j μ ox gm 3 W L V ox eff LW = π W ox κ = L j I sin k 3 ox LW V 0 eff GBW = πl μv 3 eff k j R R R R Relative bandwidth I sink I sink Feature size ( μm ) VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 68

69 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 69 V in Offset compensation Two ways for suppressing offset voltage. Store the offset voltage in capacitors and subtract it from the signal. - V A Latch a V o V out V in - LK a) Offset cancel at input nodes Feedback= High gain type ( Va VosA) V o = V a ( A) = = V A V A o osa = V V osa : Offset of the amplifier V osl : Offset of the latch a Feed forward =Low gain type V in V in - A - Latch V out V os _ in = V A osl LK b) Offset cancel at output nodes

70 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 70 Operational amplifier V in Higher resolution requires higher open loop gain. Higher conversion frequency requires higher closed loop GBW. Sampling D gain f p Vn - G error G β Gβ Op amp f p Vn - β f N:AD resolution M G M:Stage resolution Amplify s N G ( db) > 6N 0 for.5b pipeline AD Equivalent circuit s ω f p s pi gm po RL OL losed loop gain-bandwidth GBW _close gmβ = π L N fc > 3 f β= f s pi L = po ol f f ( ) s s pi pi

71 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 7 kt/ noise Larger SNR requires larger capacitance and larger signal swing. Low signal swing increases required capacitance. φ R v n L L v out dω = 4kTR π vn = ( ωr ) ( ) SNR,, SNR (db) ( ) SNR,, ( ) SNR 3,, ( ) SNR 5,, kt v n nkt = n: configuration coefficient V = FS SNR( db ) 0 log 8nkT 4bit bit n= 0bit apacitance (pf) V FS =5V V FS =3V V FS =V V FS =V

72 Basic design consideration Small mismatch Δ or ΔV V off FS Increase apacitance Δ or ΔVoff N Very tough tradeoffs, so let s keep up the design effort. N Results in LW Decrease speed and Increase Power gm gm I d I f s GBW GBW N N d V di d f s f s P I d f s N N Pd f s g Solutions VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 7 d N ) Architecture Pipeline, Parallel ) Redundancy 3) Error compensation 4) ircuit design However, kt/ issue remains SNR V sig V Solutions N sig N ) Increase signal swing ) Increase OSR SNR OSR

73 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 73 Acknowledgement The author thanks Mr. T. Matsuura from Renesus for some slides provision.

74 VLSI symposia 006, A. Matsuzawa, Tokyo Tech. 74 Study-aid books B. Razavi, Data conversion system design, IEEE press. P. E. Allen and D. R. Holberg, MOS Analog ircuit Design, nd Edition, OXFORD University Press. D. A. Johns and K. Martin, Analog integrated circuit design, John Wiley & Sons. R. J. Baker, MOS mixed-signal circuit design, IEEE Press. R.van de Plassche, MOS Integrated Analog-to-Digital and Digitalto-Analog onverters, nd Edition, Kluwer Academic Publishers. M. Gustavsson, J. J. Wikner and N. N. Tan, MOS data converters for communications, Kluwer Academic Publishers.. Shi and M. Ismail, Data converters for wireless standards, Kluwer Academic Publishers. A. Rodriguez-Vazquez, F. Mederio, and E. Janssens, MOS Telecom Data onverters, Kluwer Academic Publishers.