Analog and Mixed-Signal Center, TAMU

Transcription

1 Analog and MixedSignal enter, TAMU

2 SampleandHold ircuit S/H: S H S H S H S H S t i S/H circuit o o S/H command i Block Diagram Idealized Response t

3 Performances of S & H Realistic Transient Response: Input & Output oltage Track Error Pedestal oltage Drift t t a t h t

4 S/H ircuit Waveforms and Performance Parameters H S H i i o Droop o i Hold step Feedthrough Desired output t ap o t s Droop t ac

5 Design of Track and hold Performance Definition Acquisition Time: the required time for the output transient after the sampling signal Hold Settling Time: the time after the hold signal required for the output to settle within an acceptable error Pedestal Error: due to the transition of sample to hold mode oltage Drift: the rate of discharge of the sampling capacitor during the hold mode Dynamic Range: the ratio of the maximum and minimum input level, which can be sampled with a given resolution

6 Performance Definition Nonlinearity Error: the maximum deviation of the / characteristic from the straight line passed through the end points Gain Error: the deviation of the slope of the straight line from unity Q Nonlinearity Error 1 G Gain Error= 1 G 0 P 0 Analog and MixedSignal enter, TAMU

7 Track and hold Performance Definition Hold Mode Feedthrough: the percentage of the input signal that appears at the output during the hold mode Parasitic capacitors S p S

8 Performance Definition Aperture Error: the random variation of the turn off time of the switch results in an uncertain sampling time f 10nsec 1nsec Maximum Allowable Aperture Error for 1/2 LSB: t max = Sampling Error π f in 1 2 N 1 Ideal sampling point t 100psec 10psec 8 bits 10 bits 12 bits 6 bits Aperture Error t 1MHz 10MHz 100MHz 1GHz f in

9 Performance Definition Performance Definition SignaltoNoise Ratio (SNR): the ration of the signal power to the noise power at the output The sources of noise are the input and output buffer, switch, and clock jitter Signal to Noise Distortion Ratio (SNDR): the ration of signal power to the total noise and harmonic power at the output The source of harmonics are the nonlinearity of the buffers and the switch * n Bin n sw * * S n Bout in out

10 Q 1 Fig 1 An openloop track and hold realized using MOS technology φ clk Q 1 in φ clk hld 1 1 hld SampleandHold Basic Architectures Analysis Q H OXWL Q = = hld 2 2 where is given by eff 1 = = eff GS1 Q 1 hld OX hld WL tn OX WLeff = 2hld ( DD SS) O = hld DD eff tn 1 1 in = OX WL( DD tn in ) 2 hld φ clk Fig 2 An openloop track and hold realized using a MOS transmission gate φ clk Q 2 φ clk Q 1 hld 1 Input Output Buffer Buffer 1 1 S X H Fig 3 An openloop track and hold realized using an nchannel switch along with a dummy switch for clockfeedthrough cancellation Analog and MixedSignal enter, TAMU

11 Buffered Sample & Hold ircuit Input and Output Buffer: The capacitor voltage during the hold mode can be affected by the current drawn by the following circuit Therefore, the output voltage is buffered B in S B out in out Analog and MixedSignal enter, TAMU

12 Unity Gain Buffer ircuit: BJT and MOS implementations Bipolar Technology cc MOS Technology DD R c M 3 M 4 Q 3 Q 1 Q 2 M 1 M 2 I EE I F I SS I F

13 Track & Hold (T&H) ircuit Simple losedloop Architecture: During the sampling time, the drain and source voltage of MOS switch are closed to ground Thus the charge injection and clock feedthrough introduce an offset voltage at the output and is independent of the input voltage in G m S A 1 out Disadvantage: stability problems and low speed

14 T&H ircuit: losedloop Architecture Offset oltage ancellation: The charge injection and clock feedthrough can be cancel out by applying a replica of the offset voltage to the positive terminal of the second amplifier (commonmode voltage) in G m M 1 1 A s out M 2

15 T&H ircuit: Switched apacitor Switchedapacitor Architecture: This architecture consists of sampling capacitor S, amplifier G m, and MOS switches M 3 S G m Track Mode (=1) M 2 M 1 S G m G m S out Hold Mode (=0)

16 Evolution of S/H Architectures G m S X H A0 φ clk Q 1 1 hld Fig A losedloop sampleandhold architecture φ clk Fig B Including an opamp in a feedback loop of a sample and hold to increase the input impedance Q 2 φ clk Q 3 φ clk 1 Opamp 1 φ clk Q 2 φ clk Q 1 hld Opamp 2 Q 1 hld Adding on additional switch to the S/H of Fig B to minimize slewing time Fig D An improved configuration for an S/H as compared to that of Fig

17 Design of Track and hold T&H ircuit: urrentmode urrentmode Architecture: Advantages: highspeed (over 100MHz) and low voltage (<12) The speed depends on the time constant given by: I in M 1 I S DD S M 2 AI I out I in I out τ g = S m1 g = = S m1 2 3 µ ox ox (1 W L A)W ( GS 1 L 1 Tn )

18 Two Op Amps S/H ircuit R F D 1 D 2 A 2 A 1 SW o i H S/H Switch driver

19 i R 1 2kΩ A 1 LT118A 1 50pF A 1 LT11010 R 2 2kΩ R 3 20Ω S G ds Q 1 D 2N5432 gd 3 100pF A 3 LT118A A 4 LT118A D 2 62 o R 7 2kΩ R 8 R 9 R 10 S/H R pF Q 3 1kΩ 2N2907 D 1 HP2810 R 6 1kΩ Q 2 2N2222 H 1nF 5kΩ 5 10pF 10kΩ 50kΩ R 11 62kΩ R 7 200kΩ EE A 5 MHz trackandhold circuit, using discrete components, with charge compensation to minimize the hold step

20 t s1 actual t s1 ideal φ clk t s 2 ideal t s2 actual Sampling jitter Fig The clock waveforms for and φ clk used to illustrate how a finite slope for the sampling clock introduces samplingtime jitter H G m M X 1 A 0 in M 2 2 Fig losedloop sampleandhold architecture with pedestal cancellation

21 S/H Open Loop Architecture with Miller apacitance Y A 0 M 1 M 2 X 1 Z Y A 0 X 1 Z 2 (a) Y A 0 X 1 Z 2 out (b) 2 (c) Fig Openloop architecture with Miller capacitance (a) Basic circuit; (b) equivalent circuit in the acquisition mode; (c) equivalent circuit in the hold mode The openloop architecture with Miller capacitance employs two different values of capacitance in the acquisition and hold modes to achieve high speed and small pedestal error This is accomplished using a Miller amplifier that multiplies the effective value of the sampling capacitor by a large number when the SHA enters the hold mode

22 Switchedapacitor S/H Implementations φ 1 φ 2 v in φ φ 1 v out A switchedcapacitor sample and hole and lowpass filter φ 2A φ 1A S v in S 1 φ1b S 4 S 2 OF φ 1B S 3 φ 2B H S 5 out X 1 φ 2S S 6 φ 1B S 7 A switchedcapacitor S/H

23 MULTIPLEXEDINPUT ARHITETURES G m1 R G m2 (a) H R 1 R 2 G m1 R G m2 1 S 1 X Y 2 S 2 A X R out H Fig 15(a) Dualloop multiplexed architecture Multiplexedinput architecture (a) Basic (singleended) circuit; (b) equivalent circuit in the hold mode R 1 R 2 G m1 R 1 R G m1 1 X Y (b) (c) 2 2 Equivalent circuits of dualloop multiplexedinput architecture (b) Acquisition mode; (c) hold mode

24 T&H ircuit: urrentmode losedloop urrentmode Architecture: This architecture needs stability and speed considerations The distortion of G m2 affects directly the output current [21] G m1 M 1 A I in s G m2 I out

25 T&H ircuit: Example BiMOS Track & Hold Amplifier (12Bit & 50Msps): This circuit consists of input buffer, hold section, and output buffer [3] cc BB1 M 1 M 3 BB2 M 2 M 4 S =3pF FF is a feedforward compensation capacitor for the charge injection of Q 4 BB3 GND Q 10 Q 1 Q 2 FF Q 11 Q 12 R 1 R 2 Q 5 (Track) Q 3 Q 4 Q 13 Q 6 R 3 S (Hold) Q D 9 1 Q 8 Q 7 Q 15 Q 14 R 5 R 4

26 REYLING S/H ARHITETURE S 1 S 5 X 1 B 1 B 2 S 3 X 1 B 1 B 2 X 1 B 1 B 2 1 S 4 Y Y Y 1 2 X G m Y X G m Y X G m Y S (a) (b) Fig 16 Recycling architecture Fig 17 Equivalent circuits of recycling architecture (a) Sampling mode; (b) hold mode

27 Integratating Amplifier S/H ircuit R Offset R i A 1 SW H gd A 2 o S/H SW driver

28 Improved S/H ircuit SW 3 R R i Buffer SW 1 H o S/H SW driver SW 2 (= H )

29 LDai and R Harjani, MOS SwitchedOpAmp Based Sample and Hold ircuit,ieee JSS, January 2000, pp

30 harge injection and clock feedthrough mechanism φ ON OFF R gs gd q 1 v i M 1 h vo Q ch = WL ox ( GS T ) ' = k Q h ch = kwl ox ( h GS T ) '' = ( DD para SS ) h para

31 hannel charge in (top) triode and (bottom) saturation S G D S G D G S G D S G D G

32 SOP A h 1 in SwitchedOpAmpBased S/H ircuit 1m Gm R1=100k φ S1 φ M1 4/2 dd=5 Ib=5u 1 h1=1p out R2=100k Gm 1m φ S2 φ M2 4/2 Ib=5u dd=5 h2=1p 1 in out Simplified model of the pseudodifferential SOPbased S/H

33 Folded cascode switched opamp in the unitygain feedback configuration dd clk pbias M19 M3 M4 1 pcas M5 M18 M6 M8 M1 M2 in M9 3 ncas M10 M11 2 nbias M7 clk M16 M12 M13 M17 h clk buf clk M14 M15 out Nerr Perr = = h h Npara Ppara Npara Ppara N GS P GS

34 Simulation results for a complete cycle of sampledandheld waveform Simulation results of the spectrum of the sampledandheld waveform Differential Input / Output () PSD of Input (db/hz) Time(us) Frequency (khz)

35 References [1] UL Mcreary and PR Gray, AllMOS charge redistribution analogtodigital conversion techniques, IEEE J SolidState ircuits, vol S10, pp , Dec 1975 [2] P an Peteghem and W Sanaen, Single versus complementary switches: A discussion of clock feedthrough in S circuits, in Proc 12th Eur SolidState ircuits onf (ESSIR 86), Delft, the Netherlands, Sept 1986, pp 1618 [3] Eichenberger and W Guggenbuhl, Dummy transistor compensation of analog MOS switches, IEEE J SolidState ircuits, vol 24, pp , Aug 1991 [4] M Nayebi and BA Wooley, A 10bit video BiMOS trackandhold amplifier, IEEE J SolidState ircuits, vol 24, pp , Dec 1989 [5] PJ Lim and BA Wooley, A highspeed sampleandhold technique using a miller hold capacitance, IEEE SolidState ircuits, vol 26, pp , Apr 1991 [6] G Temes, Y Huang, and PF Ferguson Jr, A highfrequency trackandhold stage with offset and gain compensation, IEEE Trans ircuits Syst II, vol 42, pp Aug 1995 [7] S Brigati, F Maloberti, and G Torelli, A MOS sample and hold for highspeed AD s, in Proc IEEE Int Symp ircuits and Systems ircuits and Systems onnecting the World, vol 1, May 1996, pp [8] JH Shieh, M Patil, and BJ Sheu, Measurement and analysis of charge injection in MOS switches, IEEE J SolidState ircuits, vol S22, pp , Apr 1986 [9] G Wegman, EA ittoz, and F Rahali, harge injection in analog MOS switches, IEEE J SolidState ircuits, vol S22, pp , Dec 1987 [10] D Jons and K Martin, Analog Integrated ircuit Design New York: Wiley, 1997 [11] J rols and M Steyaert, Switchedopamp: An approach to realize full MOS switchedcapacitor circuits at very low power supply voltages, IEEE J SolidState ircuits, vol 29, no 8, Aug 1994