Compact, very low voltage, temperature-independent reference circuit

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1 Compact, very low voltage, temperature-independent reference circuit P.S. Crovetti and F. Fiori Abstract: A compact, very low voltage, temperature-independent reference circuit, which is based on the thermal properties of bipolar junction transistors in the saturation region is presented. The new circuit operates from a minimum power supply of less than 1V and provides a reference voltage with a nominal thermal drift of 30 ppm/8c in the temperature range between 240 and 1108C. The proposed circuit has been integrated on silicon by a 0.35 mm CMOS technology and a reference voltage with a measured untrimmed thermal drift of 100 ppm/8c has been reported. The new voltage reference occupies a silicon area of only 3,500 mm 2, shows a power consumption of,30 mw and its DC power supply rejection is better than 65 db. 1 Introduction The decrease of power supply voltages, imposed by geometrical scaling in ultra-deep submicron (UDSM) CMOS technology, has brought about new challenges in analogue integrated circuit (IC) design. In present-day ICs, in particular, analogue functions must be implemented by cells that operate from a power supply voltage of 1 V or less and most standard analogue circuit topologies do not fulfill this requirement. As a consequence, the development of very low voltage analogue cells has become one of the main issues in present-day and future analogue micro- and nanoelectronics. Traditional bandgap circuits [1 3] are not suitable to provide accurate voltage and current references in a very low voltage (,1 V) environment. Therefore, new low voltage and very low voltage temperature-compensated reference circuits have been proposed in the literature over recent years [4 15]. The accuracy over temperature of low-voltage reference circuits is sometimes worse than traditional bandgap topologies and most of them are particularly complex and area consuming. A novel very low voltage (,1V), very compact reference circuit, which exploits the thermal properties of bipolar junction transistors (BJTs) in the saturation region is now presented. The new circuit, which provides a temperature independent voltage reference with a nominal thermal drift of 30 ppm/8c, has been integrated on silicon, and a reference voltage with a measured untrimmed thermal drift of 100 ppm/8c has been reported. 2 Thermal compensation technique The proposed very low voltage, temperature-independent reference circuit employs a novel thermal compensation technique based on the properties of BJTs in the saturation region. In this section, the proposed technique is illustrated # The Institution of Engineering and Technology 2007 doi: /iet-cds: Paper first received 16th December 2005 and in revised form 19th June 2006 The authors are with the Dipartimento di Elettronica, Politecnico di Torino, Turin, corso Duca degli Abruzzi, 24, I-10129, Italy paolo.crovetti@polito.it on the basis of the schematic in Fig. 1a. More precisely, it is shown that the different thermal properties of the base-to-emitter voltage (V BE ) and the collector-to-emitter voltage (V CE ) of the bipolar transistor Q1 in Fig. 1a, which is biased in the saturation region by the constantcurrent source I 0 and by resistors R 1 and R 2, can be exploited to obtain a first-order or a second-order temperature-independent reference voltage V OUT. After a short presentation of the Ebers Moll model, which is employed to describe the operation of a BJT, the expression of the output voltage V OUT is derived, its thermal drift is evaluated and finally the design equations that should be satisfied to achieve first-order and second-order temperature compensation are presented. 2.1 BJT model In the proposed derivation, the bipolar transistor Q1 is described by the Ebers Moll model [16, 17] and the BJT collector (I C ), emitter (I E ) and base (I B ) currents are assumed to be expressed as I C ¼ a F I 1 I 2 I E ¼ I 1 a R I 2 I B ¼ I E I C where a F and a R are the forward and reverse current gains and I 1 ¼ I SE ðe V BE =V T 1Þ I 2 ¼ I SC ðe V BC =V T 1Þ where V BE and V BC are, respectively, the base emitter and base collector voltages, V T ¼ kt/q is the thermal voltage (k is Boltzmann s constant, T is the absolute temperature and q is the electron charge) and I SE and I SC are the reverse saturation currents of the base-to-emitter and of the base-to-collector junctions, respectively. On the basis of (1) and (2), the equivalent circuit of a BJT transistor in the dashed rectangle of Fig. 1b is considered hereafter. Even though the Ebers Moll model is rather simple and does not include second-order effects (high injection level effect, Early effect, and so on [16]), it is sufficiently accurate ð1þ ð2þ IET Circuits Devices Syst., 2007, 1, (1), pp

2 Therefore the temperature drift of the output voltage is related to the temperature drift of the collector-to-emitter voltage and of the base-to-emitter voltage, which are derived in the following. Assuming that the circuit is designed so that the current I 1 is temperature independent, the expression of the thermal drift of V BE is known in the literature [17] and takes the form dv BE dt ¼ V BE V BG av T T þ dv BG dt ð8þ Fig. 1 New temperature compensation technique operation where V BG is the silicon bandgap voltage and a is a parameter which is related to the thermal drift of the mobility of minority carriers. More precisely, if T h mðtþ ¼mðT 0 Þ where T 0 is a reference temperature, a is expressed as T 0 to describe the operation of integrated BJTs under typical bias conditions and to discuss the thermal compensation mechanism highlighted in this paper. Furthermore, the validity of the novel thermal compensation technique and the accuracy of the proposed analysis are discussed on the basis of computer simulations, which are carried out with reference to semiempirical BJT models, which include all second-order effects, and on the basis of experimental results. 2.2 Thermal drift of output voltage With reference to Fig. 1a, the output voltage V OUT can be expressed as V OUT ¼ V BER 2 þ V CE R 1 R 1 þ R 2 ¼ c 1 þ c V BE þ 1 1 þ c V CE ð3þ in which c ¼ R 2 /R 1. Since Q1 is biased in the saturation region, that is both its base emitter and base collector junctions are forward biased, on the basis of the Ebers Moll model (Fig. 1b), V BE and V CE can be expressed as where V BE ¼ V T log I 1 I SE V CE ¼ V T log I 1 V I T log I 2 SE I SC ¼ V T log a F logða a F xþ R ð4þ ð5þ a ¼ 4 h To evaluate the thermal drift of V CE it can be shown that the forward and the reverse current gains a F and a R which appear in (5) are almost temperature-independent. From solid-state physics [17], with reference to an npn BJT, a F and a R can be expressed as a F ¼ a R ¼ 1 1 þðm p;e N B W B =m n;b N E x E Þ 1 1 þðm p;c N B W B =m n;b N C x C Þ ð9þ ð10þ where N E, N B, N C are emitter, base and collector doping concentrations, W B, x E, x C are related to the geometry of the device and m p,e, m n,b, m p,c are the mobilities of minority carriers in the emitter (holes), base (electrons) and collector (holes) regions, respectively. Since the only temperaturedependent quantities in (9) and (10) are the mobility ratios m p,c /m n,b and m p,e /m n,b, the residual thermal drifts of a F and a R are only related to the asymmetry in the thermal drifts of minority carrier mobilities. To highlight the entity of this thermal drift, the ratio m p,c /m n,b is plotted against temperature in Fig. 2 on the basis of the expression of the bulk mobility of electrons and holes in silicon which is reported in [18] for reasonable values of collector and base dopant concentrations (N B ¼ cm 23, N C ¼ cm 23 ). x ¼ I C I 1 ¼ V BE V OUT R 1 I 1 ¼ V BE V OUT R 1 I 0 a R ðv BE V OUT Þ ð1 a Fa R Þ Since the resistance ratio c is not influenced by the thermal drift of resistors, the thermal drift of the reference voltage V OUT can be expressed as 64 dv OUT dt ¼ c dv BE 1 þ c dt þ 1 dv CE 1 þ c dt ð6þ ð7þ Fig. 2 Mobility ratio m n,b /m p,c against temperature, after [18], for typical doping concentrations IET Circuits Devices Syst., Vol. 1, No. 1, February 2007

3 From Fig. 2, the residual thermal drift of m p,c /m n,b is,5% in the temperature range between 240 and 1608C. The drift shown in Fig. 2 is further attenuated in (9) and (10) and it gives a negligible contribution to the thermal drift of V CE. In consideration of these results, the quantities a F and a R are assumed to be temperature-independent hereafter. On the basis of these assumptions the thermal drift of V CE is evaluated as dv CE dt ¼ V CE T þ V T x a F x V BE k V BE V VBE k R OUT ð11þ where k X is the first-order relative temperature coefficient of the quantity X, i.e. k X ¼ 1 dx X dt and, according with the adopted notation, k R is the resistance temperature coefficient, that is assumed to be equal for all resistors. From (11), the thermal drift of V CE is expressed as the sum of a positive term V CE /T and of a term which is related to the thermal drift of V BE. The first term is dominant for typical process parameters and as a consequence under realistic bias conditions the overall V CE voltage has a positive temperature coefficient and it is substantially proportional to the absolute temperature (PTAT). 2.3 First-order temperature compensation On the basis of (7), (8) and (11) it can be observed that V OUT is expressed as the weighted sum of a PTAT voltage and of a term that is proportional to the V BE voltage, therefore, as in traditional bandgap voltage references, first-order temperature compensation can be achieved by a proper choice of the weighting factors, which are related to the resistance ratio c. From (7) the reference voltage is first-order temperature independent if the resistance ratio c is c ¼ ðdv CE=dTÞ ðdv BE =dtþ ¼ þ x a F x V CE V BG V BE þ av T ðdv BG =dtþt! V T V k T R1 V BE V OUT V BE k VBE ð12þ Furthermore, a reference voltage with either a positive or a negative linear thermal drift can be obtained as well by a different choice of c. For a given value of the bias current I 0 and of the factor x, being some algebraic derivations, which are detailed in the Appendix (Section 7.1), it can be observed that the second-order derivative of V OUT is zero if where ðc stþx 2 þ a F ½t ðs þ k 2 xþ 2cŠx þ a 2 Fc ¼ 0 s ¼ k xx þ 2k x T V t ¼ T ðd 2 V BE =dt 2 Þ ð14þ ð15þ ð16þ and k XX is the second-order relative temperature coefficient of the quantity X, that is k XX ¼ 1 d 2 X X dt 2 1 dx 2 X 2 ¼ dk X dt dt All the quantities that appear in (14) can be expressed in terms of the output voltage V OUT, of the bias current I 0,of the design parameters x, c and in terms of technology parameters. As a consequence, (3), (12) and (14) can be solved for a given value of the bias current I 0 to get the values of x, c and V OUT which make the output voltage V OUT second-order temperature independent. For typical process parameters, and under realistic bias conditions, the output voltage V OUT, obtained employing the proposed temperature compensation technique, is between 30 and 100 mv and it is suitable to be employed as a reference voltage in very low voltage integrated circuits. 3 Reference circuit implementation The new temperature compensation technique is now employed to design the very low voltage reference circuit whose principle schematic is shown in Fig. 3. The proposed circuit includes the building block (R 1 ¼ R 1a þ R 1b, R 2 and Q1) in Fig. 1a, that is designed to achieve first-order and second-order thermal compensation in accordance with (3), (12) and (14), as illustrated in the Appendix (Section 7.2) by a numerical design example. In this section the opamp-based bias circuit, which implements the current source I 0, is first presented. Then the opamp circuit in Fig. 3 is designed and finally the I 1 ¼ I 0 1 þ a R x a F a R ð13þ the values of V BE, V CE and k VBE, which appear in (12), are given by (4), (5) and (8), therefore (3) and (12) can be solved to find out the values of c and of the reference voltage V OUT which achieve first-order temperature compensation. 2.4 Second-order temperature compensation On the basis of the results presented so far, a first-order temperature independent reference voltage can be obtained from the circuit in Fig. 1a for an arbitrary choice of the parameter x. Nonetheless, the dependency of the reference voltage on the factor x can be advantageously exploited to achieve second-order temperature compensation. After Fig. 3 Reference circuit simplified schematic IET Circuits Devices Syst., Vol. 1, No. 1, February

4 reference voltage and a reference current with a low thermal drift from the same circuit. In the preceding derivation, the opamp circuit in Fig. 3 has been assumed to be ideal. The effects of opamp offset voltage on the accuracy of the new reference circuit are discussed in the Appendix (Section 7.3). 3.2 Complete reference circuit schematic Fig. 4 complete schematic of the new reference circuit in Fig. 4 is described, its minimum power supply voltage is evaluated and startup issues are discussed. 3.1 Bias circuit implementation The opamp-based circuit in Fig. 3 is designed to implement the bias current source I 0 in Fig. 1, which provides a power supply and temperature-independent bias current I 1 to the base emitter diode in Fig. 1b, in accordance with the hypotheses that have been considered in Section 2. With reference to Fig. 3, the bias current source I 0 in Fig. 1 is implemented by M1, which mirrors the drain current of M2 that is equal to the current which flows in R 3. Since the opamp nulls its input differential voltage by negative feedback, the current which flows in R 3 can be expressed as I R3 ¼ I 0 ¼ V OUT þ R 1b I C R 3 As a consequence from (13) the current I 1 is given by I 1 ¼ I 0 a R I C 1 a F a R ð17þ ¼ 1 R 1 ðr 1 =R 3 ÞV OUT þðr 1b =R 3 a R ÞðV BE V OUT Þ 1 a F a R ð18þ and it can be made temperature independent if R 1b ¼ a R R þ k R 1 3 k VBE x 1 V OUT V BE ð19þ If (19) is satisfied the hypothesis about I 1 considered in the previous section is exactly met. Nonetheless, the accuracy over temperature of the reference voltage is not substantially impaired even if this hypothesis is not met exactly. Furthermore, if a R x 1, from (13), I 1 ¼ ki 0 where k is a temperature-independent quantity. As a consequence, if I 1 is designed to be temperature independent, the current I 0 shows a low thermal drift and it can be mirrored as a reference current. For this reason the circuit implementation proposed in Fig. 3 is particularly attractive for the reduction of silicon area occupancy, since it is suitable to obtain both a very accurate temperature independent 66 New reference circuit complete schematic To complete the design of the new reference circuit the opamp circuit in Fig. 3 is implemented by a standard twostage pmos-input opamp cell and the complete transistorlevel schematic shown in Fig. 4 is obtained. In this circuit, the Miller capacitor C is employed to achieve closed-loop stability and the reference current I REF is mirrored by transistors M3 and M4 to provide the bias current to the differential pair and to the gain stage of the opamp, respectively. Since the minimum power supply voltage of the pmos-input opamp cell is less than 1 V, the implementation in Fig. 3 fully exploits the very low voltage features of the thermal compensation scheme in Fig. 1a and the minimum power supply voltage which is required for the correct operation of the overall reference circuit is only limited by the sum of the voltage V BE of Q1 and of the drain-to-source voltage which is required to operate M1 in the saturation region, V DS,sat. Under typical bias conditions and process parameters V BE þ V DS;sat, 0:9V in the temperature range between 240 and 1108C, as a consequence the new circuit is suitable to be employed in a very low voltage environment. Furthermore, the self-biased architecture adopted in Fig. 4 does not require an additional startup circuit for proper operation. This feature can be highlighted with reference to Fig. 4, in which, from Kirchhoff s voltage law V DD ¼ V SG3 þ V C þ V GS9 ð20þ where V SG3 and V GS9 are the source-to-gate and gate-to-source voltages of transistors M3 and M9 and V C is the voltage across the Miller capacitor C. Since C is much larger than gate-to-source parasitic capacitances C GS3 and C GS9, at startup, when the initial voltage across C is zero, the power supply voltage V DD is divided between V SG3 and V GS9 and transistors M3 and M9 are turned on, making the bias current flow in each branch of the circuit. As a consequence, the pmos-input opamp circuit, whose common-mode input range includes the ground voltage, is biased as soon as the power supply is switched on and it provides the negative feedback which is necessary to the circuit for its correct operation. 4 Voltage reference circuit performance The new very low voltage reference circuit presented has been designed and integrated on silicon by a 0.35 mm BiCMOS technology process and its performance over temperature verified by computer simulations [19] and by on-chip measurements. The specific integrated reference circuit, which is considered hereafter, occupies a silicon area of only 3500 mm 2, operates at 1 V with a power consumption of 30 mw and it is designed to provide a reference voltage of 47 mv and a reference current of 6 ma. The new circuit has also been IET Circuits Devices Syst., Vol. 1, No. 1, February 2007

5 compared with other voltage reference circuits proposed in the literature [5 10]. 4.1 Computer simulation results The performance over temperature of the new reference circuit and its very low voltage operation have been verified by computer simulations performed by ELDO [19], a SPICE-like circuit simulator, on the basis of accurate semiempirical models of active and passive circuit elements. The main results of such simulations are discussed in the following and are summarised in Table 1. The simulated reference voltage is plotted against temperature in Fig. 5. It can be observed that the simulated reference voltage shows a residual drift of about +110 mv (+2300 ppm) in the temperature range between 240 and þ1108c, that is in this interval it shows a mean thermal drift of 30 ppm/8c. Computer simulations have been carried out over different process corners and it has been observed that the nominal value of the reference voltage is rather sensitive to process spreads (about þ10% in the slow corner), while its temperature drift, even though it is worsened, is less affected by technology spreads and it is of 150 ppm/8c in the worst case (fast corner). Moreover, it has been observed that a +5% mismatch in resistors affects the output voltage of +1.5% and affects its thermal drift of about +2.5 mv/8c. Errors due to process corners and device mismatch can be fully compensated by chip trimming. In Fig. 6, the simulated reference current I REF is plotted against temperature. Such a current, which is obtained from the same circuit that provides the reference voltage considered in Fig. 5, shows a residual drift of about +125 na (+1.8%) in the temperature range between 240 and þ1108c, that is its residual thermal drift is about 100 ppm/8c. As a consequence the results in Fig. 6 confirm that the new topology is suitable to obtain both a very accurate temperature independent reference voltage and a reference current with a low thermal drift from the same circuit. Finally, the simulated reference voltage for different values of the power supply voltage is plotted in Fig. 7. In this plot, the very low voltage features of the new circuit are highlighted and it can be observed that the circuit operates correctly with a power supply voltage as low as 850 mv. 4.2 Experimental results The reference circuit described has been laid out and integrated on silicon by a 0.35 mm CMOS technology and its performance in terms of thermal drift, power supply rejection and startup behaviour have been tested by on-chip measurements. Experimental results are discussed in the following and are summarised in Table 1 In Fig. 8, the measured reference voltage of an untrimmed sample of the new circuit is plotted over temperature (continuous line). It can be observed that the circuit shows a nominal reference voltage of 39.1 mv, with an untrimmed thermal drift of +310 mv in the temperature range between 220 and þ1208c, that is it shows a mean thermal drift of 100 ppm/8c. The measured thermal drift shows a systematic linear component which Table 1: Reference circuit performance Parameter Symbol Simulations Measurements Nominal power supply voltage, V V DD 1 1 Nominal reference voltage, mv V OUT Nominal reference current, ma I REF Reference voltage thermal drift, ppm/8c (1/DT) DV OUT /V OUT Thermal drift w/o linear component, (1/DT) DV OUT /V OUT N/A 21 ppm/8c Reference current thermal drift, ppm/8c (1/DT) DI REF /I REF 100 N/A Minimum power supply voltage, mv V DD,min DC ref voltage power supply rejection, db (V OUT /V DD ) DV DD /DV OUT % startup time, ms Fig. 5 Simulated reference voltage thermal drift Fig. 6 Simulated reference current thermal drift IET Circuits Devices Syst., Vol. 1, No. 1, February

6 Fig. 7 Simulated reference voltage against power supply voltage Fig. 9 Measured power supply rejection against frequency Fig. 8 Measured reference voltage thermal drift can be fully compensated after fabrication by trimming. If the systematic linear drift component is subtracted to the measured reference voltage, the thermal drift which is shown in Fig. 8 (dashed line) is obtained. It can be observed that the residual thermal drift of the measured circuit, if its linear component is removed, is 25 ppm/8c, in accordance with the results of computer simulations. In Fig. 9 the measured power supply rejection of the reference circuit is plotted. It can be observed that the power supply rejection is 65 db at very low frequency and it is.35 db in the frequency range from 5 khz to 1 MHz. Finally, in Fig. 10, the transient waveform of the reference voltage at startup is plotted. It can be observed Fig. 10 Measured reference voltage waveform at startup that when the power supply voltage is turned on the reference voltage settles to its nominal value with a 10 90% delay of 5.5 ms. As a consequence, the new reference circuit, which does not include any specific startup circuit, correctly operates at system power on, as discussed in Section 3. Finally, in Table 2, the main measured and simulated performance parameters of the new reference circuit are summarised and compared with other voltage reference topologies in the literature [5 10]. Table 2: Voltage reference circuits performance Parameter This work Song [5] Leung I [6] Leung II [7] Annema [8] Jiang [9] Giustolisi [10] Min. supply, V Ref. voltage, V Temp. coeff. (untrimmed), 30 (100) 22.3 (N/A) 5.3 (N/A) 15 (N/A) N/A (+28.5) +30 (+100) N/A (119) ppm/8c Temp. range, 8C 240/þ110 0/þ60 0/þ100 0/þ /þ /þ /þ125 Silicon area, mm N/A Technology, mm PSR (DC), db N/A Startup circuit not req. N/A req. req. req. N/A req. 68 IET Circuits Devices Syst., Vol. 1, No. 1, February 2007

7 5 Conclusions An accurate, compact, reference circuit, which is suitable for very low voltage, low power operation has been presented. The new reference circuit, based on the thermal properties of bipolar transistors in the saturation region, operates from a power supply of,1 V, occupies a silicon area of,3500 mm 2 and provides a reference voltage with a nominal thermal drift of 30 ppm/8c in the temperature range 240 to þ1108c. The new circuit has been integrated on silicon and an untrimmed thermal drift of 100 ppm/8c and a DC power supply rejection.65 db have been measured. The accuracy over temperature of the measured sample could be further improved by trimming. 6 References 1 Widlar, R.J.: New developments in IC voltage regulators, IEEE J. Solid-State Circuits, 1971, SSC-6, pp Kuijk, K.E.: A precision reference voltage source, IEEE J. Solid-State Circuits, 1973, SSC-8, pp Brokaw, A.P.: A simple three-terminal IC bandgap reference, IEEE J. Solid-State Circuits, 1974, SSC-9, pp Meijer, G.C.M., et al.: A new curvature-corrected bandgap reference, IEEE J. Solid-State Circuits, 1982, SSC-17, pp Song, B., and Gray, P.R.: A precision curvature-compensated CMOS bandgap reference, IEEE J. Solid-State Circuits, 1983, SSC-18, pp Leung, K.N., Mok, P.K.T., and Leung, C.Y.: A 2-V 23 ma5.3-ppm/8c curvature-compensated CMOS bandgap voltage reference, IEEE J. Solid-State Circuits, 2003, 38, (3), pp Leung, K.N., and Mok, P.K.T.: A sub-1-v 15-ppm/8C CMOS bandgap voltage reference without requiring low threshold voltage device, IEEE J. Solid-State Circuits, 2002, 37, (4), pp Annema, A.-J.: Low-power bandgap references featuring DTMOSTs, IEEE J. Solid-State Circuits, 1999, 34, (7), pp Jiang, Y., and Lee, E.K.F.: Design of low-voltage bandgap reference using transimpedance amplifier, IEEE Trans. Circuits Syst. II, Analog Digit. Signat. Process., 2000, 47, (6), pp Giustolisi, G., Palumbo, G., Criscione, M., and Cutri, F.: A low-voltage low-power voltage reference based on subthreshold MOSFETs, IEEE J. Solid-State Circuits, 2003, 38, pp Dehghani, R., and Atarodi, S.M.: A new low-voltage precision CMOS current reference with no external components, IEEE Trans. Circuits Syst. II, Analog Digit. Signal. Process., 2003, 50, pp Dijkmans, E.C.: Hearing instruments go digital. Proc. 23rd European Conf. on Solid-State Circuits, 1997, ESSCIRC 97, Southampton, UK, Sept. 1997, pp Banba, H., Shiga, H., Umezawa, A., Miyaba, T., Tanzawa, T., Atsumi, S., and Sakui, K.: A CMOS bandgap reference circuit with sub-1 V operation, IEEE J. Solid-State Circuits, 1999, 34, (5), pp Leung, K.N., and Mok, P.K.T.: A CMOS voltage reference based on weighted DV GS for CMOS low-dropout linear regulators, IEEE J. Solid-State Circuits, 2003, 38, pp Dai, Y., Comer, D.T., Comer, D.J., and Petrie, C.S.: Threshold voltage based CMOS voltage reference, IEE Proc., Circuits, Devices Syst., 2004, 151, pp Massobrio, G., and Antognetti, P.: Semiconductor device modeling with SPICE (McGraw-Hill, New York, 1993) 17 Sze, S.M.: Physics of semiconductor devices (Wiley, New York, 1969) 18 Arora, N.D., Hauser, J.R., and Roulston, D.J.: Electron and hole mobilities in silicon as a function of concentration and temperature, IEEE Trans. Electron Devices, 1982, ED-29, p ELDO v4.5 user s manual, Analog Standard Cell Data Sheet, OP LN CMOS Operational Amplifier, AustriaMicroSystems (AMS) Rev. A, Oct Appendix 7.1 Second-order thermal drift The second-order thermal drift of the output voltage can be evaluated as d 2 V OUT dt 2 ¼ c d 2 V BE 1 þ c dt 2 þ 1 d 2 V CE 1 þ c dt 2 ð21þ Therefore d 2 V OUT dt 2 ¼ 0 () c d2 V BE dt 2 þ d2 V CE dt 2 ¼ 0 ð22þ From (8), the second-order derivative of V BE can be expressed as d 2 V BE dt 2 ¼ av T T 2 þ 1 T dv BG dt þ d2 V BG dt 2 ð23þ The second-order derivative of V CE, instead, can be expressed in terms of the factor x and its temperature coefficients k x and k xx as d 2 V CE x dt 2 ¼ V T a F x 2k x T þ k xx þ a Fx ða F xþ 2 k2 x ð24þ With the notation introduced in (15) and (16), (14) is obtained from (22), replacing the values of the second-order thermal drifts of V BE and V CE in (23) and (24). The temperature coefficient of x, on the basis of (6), can be expressed as V k x ¼ BE k V BE V VBE k R ð25þ OUT V k xx ¼ BE k V BE V VBE V BE V OUT V BE OUT ðv BE V OUT Þ 2 k2 V BE k RR ð26þ 7.2 Design example A numerical design example is proposed which illustrates how the design parameters of the basic building block in Fig. 1a (R 1 and R 2 ) can be obtained in practice on the basis of the implicit design equations in Section 2. For a given bias current I 0, design parameters can be evaluated iteratively from (3), (12) and (14), starting from an initial guess, which can be obtained considering x ¼ 0, that is assuming that Q1 is biased in deep saturation. Under this assumption, and I 0 I 1 ¼ 1 a F a R V BE ¼ V T log I 1 I SE V CE ¼ V T log a R ð27þ For example, if a bias current I 0 ¼ 6.6 ma is chosen and a BJT with a forward current gain a F ¼ 0.98, a reverse current gain a R ¼ 0.85 and a base emitter reverse saturation current I SE ¼ 60 aa is considered (values of technology parameters obtained with reference to vertical BJTs in a 0.35 mm BiCMOS technology), (27) gives V BE ¼ 711 mv and V CE ¼ 42.2 mv. Under these assumptions, (12) explicitly gives an initial guess of c, that is of the ratio of resistances R 1 and R 2, c ¼ R 2 V ¼ CE R 1 V BG V BE þ av T ðdv BG =dtþt ð28þ Since V T ¼ 26 mv, V BG ¼ V, dv BG /dt ¼ 2273 mv/8c and a, which is related to the mobility thermal drift [18], is 3 in the previously considered numerical example, (28) gives an initial guess c ¼ On the basis of the initial guess of c, the value of x that is required for second-order temperature IET Circuits Devices Syst., Vol. 1, No. 1, February

8 compensation is evaluated by (14) as qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2c t ðs þ kxþþ 2 4ctk 2 x þ t 2 ðs þ kxþ 2 2 x ¼ a F 2ðc stþ ð29þ where s, t and k x are given by (15), (16), (25) and (26) in terms of previously calculated quantities and in terms of technology parameters. In the numerical design example considered, s ¼ K 22, t ¼ K 2, k x ¼ K 21 and, from (29), x ¼ The absolute values of R 1 and R 2 are expressed in terms of x by (6) and (13) as R 1 ¼ ðv BE V OUT Þð1 þ a R x a F a R Þ xi 0 R 2 ¼ cr 1 ð30þ In the proposed example, R 1 ¼ 123 kv and R 2 ¼ 794 V. The value of x just evaluated can be iteratively employed in (3), (5) and (12) to affinate the initial guess of c. The values of c, f, R 1 and R 2 obtained in the first iterations of the proposed scheme are given in Table 3. It can be observed that the iterative procedure rapidly converges and three iterations are sufficient for design purposes. The same approach can be employed performing parametric DC computer simulations with reference to the circuit in Fig. 1a. 7.3 Effect of opamp offset The effects of the opamp input offset voltage and of its thermal drift on the accuracy of the reference circuit implementation in Fig. 3 are now investigated. Since the opamp offset voltage can be considered as a small perturbation of the nominal DC operating point, the small-signal equivalent circuit in Fig. 11 is considered, in which v off is the input offset voltage source and r be, r bc are the Table 3: differential resistances of the base-to-emitter and of the base-to-collector junctions. With reference to this circuit, the perturbation (small letters with small subscripts, e.g. v out, indicate small perturbations of electrical quantities with respect to the nominal DC bias point, for example V OUT ) of the opamp inverting input voltage v 2 due to the input offset generator v off can be expressed as v ¼ i 0 er in which i 0 ¼ g m v p as shown in Fig. 11 and where Iterative solution of design equations Iteration c x R 1,kV R 2,kV # # # # # r er ¼ be a 1 a R a 0 F R 1a r bc F ðr bc þ R 1 þ R 2 Þð1 a R a 0 F Þ a 0 F ¼ a F R 1 þ R 2 r bc þ R 1 þ R 2 while the perturbation of the non-inverting input voltage v þ is given by v þ ¼ v off þ R 3 i 0 Fig Evaluation of effect of opamp offset voltage on reference voltage: small-signal equivalent circuit IET Circuits Devices Syst., Vol. 1, No. 1, February 2007

9 Since the opamp nulls its differential input voltage v off i 0 ¼ er R 3 and the contribution of the opamp input offset voltage v off to the output voltage v out is v out ¼ v off r be er R 3 1 a R a 0 F a F R 1 r bc ðr bc þ R 1 þ R 2 Þð1 a R a 0 F Þ ¼ hv off ð31þ Since the offset voltage changes with temperature, its thermal drift affects the thermal coefficient of the output voltage, which can be expressed as V 0 OUT k VOUT ¼ k V 0 OUT VOUT 0 þ hv þ k voff off hv off V 0 OUT þ hv off ð32þ where VOUT 0 and k V 0 out are, respectively, the output voltage and the temperature coefficient of a reference circuit which includes an offset-free opamp, h is the offset propagation factor defined in (31) and k voff is the temperature coefficient of the opamp input offset voltage. With reference to the design that is proposed in this paper, in which R 1a ¼ 100 kv, R 1b ¼ 15 kv, R 2 ¼ 5.9 kv, R 3 ¼ 40 kv and the nominal output voltage is 47.1 mv, the offset propagation factor h given by (31) is An opamp input offset voltage of +2mV with a thermal drift of 4 mv/8c (reasonable values for a CMOS opamp in a 0.35 mm technology [20]) induces an error in the reference voltage of +240 mv and affects its thermal drift of 10 ppm/8c. Since the contribution of the opamp offset voltage to the output voltage thermal drift depends on random quantities, it requires chip trimming for cancellation. Nonetheless, the opamp input offset voltage can be minimised either by proper opamp design or by any offset cancellation technique proposed in the literature. IET Circuits Devices Syst., Vol. 1, No. 1, February