A simple subthreshold swing model for short channel MOSFETs

Transcription

1 Solid-State Electronics ) 391±397 A simple subthreshold swing model for short channel MOSFETs A. Godoy *, J.A. Lopez-Villanueva, J.A. Jimenez-Tejada, A. Palma, F. Gamiz Departamento de Electronica, Facultad de Ciencias, Universidad de Granada, Granada, Spain Received 14 September 2000; received in revised form 24 January 2001; accepted 25 January 2001 Abstract A new approach to calculate the subthreshold swing of short channel bulk and silicon-on-insulator metal oxide semiconductor eld e ect transistors is presented. The procedure utilizes a channel-potential expression appropriate for submicron dimensions. The nal result is similar to that used for long channels except for a factor k which represents the short channel e ects. Comparison with di erent published results reveals excellent quantitative agreement. Ó 2001 Elsevier Science Ltd. All rights reserved. 1. Introduction * Corresponding author. Tel.: ; fax: address: agodoy@ugr.es A. Godoy). The gain in integrability and speed is the main reason for the continuous miniaturization of metal oxide semiconductor eld e ect transistors MOSFETs). Bulk CMOS remains as the main technology for submicron gate ULSI systems. However, thin- lm silicon-on-insulator SOI) MOSFETs are of great interest due to improved isolation and reduced parasitic capacitances compared to bulk silicon technology. As device dimensions are reduced, the so-called short channel e ects SCE) become increasingly important due to the penetration of the lateral eld into the channel region. From these e ects, degradation of threshold voltage and the increase in subthreshold swing, S, are the most signi cant [1±3]. Much work has been focused on the study of threshold voltage and di erent approaches have been used to make an analytical model of the behavior of this parameter [4±6]. However, despite its importance, few articles have dealt with the modeling of S, a key factor for transistor performance. Deterioration of the subthreshold behavior increases the o -current level and standby power dissipation and reduces noise immunity [2]. Such characteristics become particularly important for low voltage portable electronics [7]. Two-dimensional device simulators are usually used, though a simple analytical model would be very valuable to understand the device physics. Here, a short channel subthreshold swing model is derived for three di erent structures: bulk, thin lm fully depleted and double-gate DG) SOI MOSFETs. The nal expression is the same for the three devices. The only di erence is a factor l, a natural length scale introduced as a scaling parameter. With this model, the accelerated S increase observed in the very short channel range can be accurately predicted. Because of its simple functional form and computational eciency, this model is suitable for the guidelines of technology design and can be used in circuit simulation. 2. Analytical model In this section, we provide the analytic framework necessary to develop a subthreshold swing model for a conventional MOSFET. After that, fully depleted and DG SOI structures are analyzed. For all these devices a negligible interface state density has been assumed /01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S )

2 392 A. Godoy et al. / Solid-State Electronics ) 391± Bulk MOSFETs The subthreshold swing, S, is de ned as the change in gate bias required to change the subthreshold drain current by one decade, and is given by: w y ˆw SL V bi V ds w SL y l L l Ly l V bi w SL ; L l 6 S o log I D ; 1 where V g is the gate voltage and I D the drain current. The key point in this expression lies in the fact that V g and I D are related through the minimum of the surface potential, w S min, since drain current at subthreshold operation is dominated by a di usion process whereby the current may be computed in terms of the probability of a source electron surmounting an energy barrier. The height of this barrier is qw S min, which is a function of the applied gate voltage and where q is the electron charge. Thus, I D is proportional to exp w S min =V T where V T is the thermal voltage. Therefore, it is more convenient to represent S as: S ˆ o ln I D ln 10 : 2 At this point, the calculation of the second derivative in Eq. 2) is straightforward. For a long channel MOSFET in the subthreshold regime, if the mobile channel charge is neglected, it is possible to state: V g V FB ˆ w SL Q dep ; 3 where V FB is the at band, w SL is the long channel surface potential, Q dep is the depletion charge and is the oxide capacitance. As for a long channel device the surface potential is constant along the channel, it follows that: ˆ 1 C dep ; 4 where C dep is the depletion capacitance. Hence, we can conclude that for a long channel transistor: S ˆ 1 C dep V T ln 10 : 5 Nevertheless, we are mainly interested in including the SCEs. Since subthreshold conduction is governed by the potential distribution, it is necessary to consider an analytical expression that is appropriate for such dimensions. A widely employed model for the electrical potential along the channel is given by [5]: where y is the parallel coordinate to the Si±SiO 2 interface, V bi is the built-in potential between the source± substrate and drain±substrate junctions, V ds is the drain±source voltage, L is the channel length and l is the characteristic length de ned as: r Si t ox X dep l ˆ ; 7 ox where Si and ox are the permittivity of Si and SiO 2 respectively, t ox is the oxide thickness and X dep is the depletion layer thickness. In order to simplify calculations, X dep is assumed to be a constant for which the surface potential is set at its average value at subthreshold operation: 1:5/ B ˆ 1:5V T ln N sub =n i with N sub representing the substrate doping concentration and n i the intrinsic carrier concentration. In order to take into account the e ect of the substrate voltage, 1:5/ B should be substituted by 1:5/ B V sub in the X dep calculation which also modi es the Q dep, C dep and l values. The dependence of the surface potential, 6), on V g is implicit in w SL, which is given by Eq. 3). Expression 6) predicts a large variation in potential along the channel for submicron devices. The injection of source electrons into the channel and therefore the device current is determined by the minimum value of the potential. This minimum is located at y 0 and can be expressed as [9]: y 0 ˆ l 2 " # V bi w log SL exp L l Vbi w SL V ds : V bi w SL V ds V bi w SL exp L l 8 Now, in the calculation of S we make use of the identity: ˆ ow y 9 yˆy 0 which can be obtained deriving Eqs. 6) and 3): ow y ˆ 1 ov 1 g yˆy 0 ; C dep k 10 where, k ˆ 1 y 0 l Ly 0 l : 11 L l

3 Finally, substituting Eq. 8) in Eq. 11) we obtain: 2 V bi w k ˆ 1 SL V ds tgh L 2l q : 4 V bi w SL V bi w SL V ds 2 L 2l V 2 ds 12 Thus, we have obtained a new expression for the subthreshold swing which resembles the long channel one and where k is the only di erence: S ˆ 1 k C dep V T ln 10 : 13 Therefore, the in uence of the SCE on the subthreshold swing is concentrated on the k factor and due to its simplicity, it is possible to carry out a fast estimation of its importance. Further simpli cation is possible if the drain voltage is small V ds V bi w SL, when expression 12) reduces to: 1 k ' 1 : 14 cosh L 2l Moreover, if L 2l: k ' 1 2 exp L : 15 2l 2.2. Fully-depleted SOI MOSFETs In this structure, the substrate has been replaced by a thick buried oxide to dramatically reduce the junction capacitance and a silicon lm of thickness t Si is grown over the oxide. To obtain improved short-channel performance in SOI over conventional MOS transistors, t Si must be smaller than the bulk depletion depth X dep, originating a fully-depleted silicon lm. As we are dealing with a di erent structure it is necessary to use di erent boundary conditions which will in uence the potential distributions. However, an expression similar to Eq. 6) can be used to reproduce the lateral potential distribution from source to drain. Yan et al. [8] assumed that the electric eld at the Si±SiO 2 buried interface is approximately zero. This is equivalent to considering an in nite buried oxide thickness t box. A more general calculation was developed by Banna et al. [10] since an arbitrary t box is included in their calculations. Thus, di erent expressions for the natural length scale are found in both papers. However, since t box is usually much thicker than the front gate oxide t ox both expressions lead to the same results, as proved in our numerical calculations.therefore, we nally write: A. Godoy et al. / Solid-State Electronics ) 391± r Si t ox t Si l ˆ : 16 ox This expression is equivalent to that employed for bulk MOSFETs 7) where X dep is replaced by t Si. For thin lm transistors, since the silicon lm is fully depleted we have to modify Eq. 3) to state that: V g V FB ˆ w SL qn subt Si : 17 There is no variation of the depletion charge with the front gate voltage and, as a consequence, using Eqs. 6) and 17): ˆ 1 k : 18 Therefore, we are able to write: S ˆ 1 k V T ln where k is similar to expression 12) using the appropriate parameters for the device under consideration. Then, for a long channel transistor, the inverse subthreshold slope should reach its theoretical lower limit of 60 mv/dec. However, higher values of S have been found. To explain subthreshold swing values higher than 60 mv/dec for long channels it must be considered [11,12] that S is modi ed by parameters such as the buried oxide thickness, which is not included in our model since the former derivation did not account for the capacitive coupling between the front and back interfaces. In order to consider this e ect, it is possible to use a more elaborate model [11,12]: C box C Si ˆ 1 ow SL C Si C box 20 where C Si ˆ Si =t Si is the silicon lm capacitance and C box ˆ ox =t box is the back gate oxide capacitance. This expression should be multiplied by Eq. 19) to take into account the correction factor. Nevertheless, our numerical calculations have demonstrated that the e ect of Eq. 20) is negligible when SCE becomes important, namely, when factor k Double-gate SOI MOSFETs In this structure, the buried oxide is replaced by a gate oxide and we will further consider the symmetrical device for which equal voltages are applied at both front and back gates. For this device: V g V FB ˆ w SL qn sub t Si 2 and using Eqs. 6) and 21): 21

4 394 A. Godoy et al. / Solid-State Electronics ) 391±397 ˆ 1 k : 22 Again, expression 6) can be used for the surface potential where the characteristic length is now de ned as: r Si t ox t Si l ˆ ; 23 ox 2 where the silicon lm thickness is halved. Therefore, for the same device parameters this structure would have a better subthreshold behavior than the fully depleted one [8]. Again, we are able to write: S ˆ 1 k V T ln with k similar to Eq. 12) using the expressions appropriate for double-gate SOI MOSFETs. 3. Validation of the model Fig. 1. Comparison between results from Ref. [13] and our model, for a bulk MOS transistor with t ox ˆ 7:5 nm, L ˆ 0:25 lm and V ds ˆ 0:1 V. Fig. 2. Comparison between 2D numerical simulation and our model for a bulk conventional MOS transistor with t ox ˆ 10 nm, N sub ˆ cm 3 and V ds ˆ 0:1 V. Solid line corresponds to subthreshold swing calculated for k equal to expression 12) and dashed line is for k equal to expression 15). In this section, the former theory is compared with experimental and numerical results presented by di erent authors. Firstly, we compare the results obtained with expression 13) for a conventional bulk MOSFET with the data presented by Biesemans et al. [13]. Fig. 1 shows the subthreshold swing versus the substrate doping concentration, N sub. Solid squares represent the data obtained through Biesemans's model while the solid line depicts expression 13). For high substrate doping, S increases because of the increase in the depletion capacitance C dep. In the low N sub region, the SCE originate an increase in S since in this situation the lateral eld is unscreened by the dopants. Both models show the same behavior as a function of N sub, although Eq. 13) is considerably easier to calculate and therefore computationally more ecient and useful for computer simulations. We also used a two dimensional device simulator, MEDICI [14], in order to study the variation of S with the channel length. In Fig. 2, solid squares represent the data obtained from MEDICI, while the solid line is obtained from our analytical model. As can be seen, S increases as the channel length is reduced and a very good agreement is achieved for the whole range of lengths employed. As can be deduced from the general de nition of S in Eq. 2), this parameter evaluates the sensitivity of the surface potential to gate voltage variations. Thus, the reduction of channel length and hence the appearance of SCE reduces this sensitivity, provoking an increase in S. In this gure, the dashed line represents the results obtained when approximation 15) is employed. As can be observed, Eq. 15) is not appropriate for very short channel lengths where L becomes comparable with 2l and the complete expression 12) is necessary to reproduce the 2D simulation successfully. It is important to note that when channel lengths approximate 2l, and high drain±source voltages are applied, it is possible to get negative S values from Eq. 13). Then, for the correct use of the model, it is necessary to ensure that L > 2l. This phenomenon could be

5 A. Godoy et al. / Solid-State Electronics ) 391± Fig. 3. Comparison between results from Ref. [15] j and our model Ð for a thin lm SOI device with t ox ˆ 5 nm, t Si ˆ 50 nm, t box ˆ 500 nm and N sub ˆ cm 3. a) V ds ˆ 0:1 V and b) V ds ˆ 2V. Fig. 4. Comparison between results from Ref. [13] j and our model Ð for a fully-depleted SOI MOSFET with t ox ˆ 7 nm, t Si ˆ 30 nm, t box ˆ 80 nm, N sub ˆ cm 3 and V ds ˆ 0:1 V. Fig. 5. Subthreshold swing as a function of the silicon lm thickness in a double-gate SOI MOSFETs with t ox ˆ 3 nm, L ˆ 50 nm, V ds ˆ 50 mv and N sub ˆ cm 3. Dashed line shows results from Ref. [16] and solid line our model. considered an extreme case of SCE where the behavior of the device is not appropriate. To con rm the validity of our analytical model for SOI devices, we rst used the results presented by Horiuchi et al. [15]. Their data are shown in Fig. 3 as solid squares, while the solid line represents our model. As can be seen from this gure, expression 19) reproduces satisfactorily channel lengths as short as 50 nm. The S roll-up when higher drain±source voltages are applied is understood as the penetration of the lateral drain eld into the channel region. The di erences in S values for long-channel devices could be caused by the presence of traps at the Si±SiO 2 interfaces neglected in our model. Moreover, as shown in Fig. 4, we have successfully reproduced the experimental results presented by Biesemans [13] for an SOI device with N sub ˆ cm 3, t ox ˆ 7 nm, t Si ˆ 30 nm, t box ˆ 80 nm and V ds ˆ 0:1 V. Fig. 5 presents the dependence of the subthreshold swing on the silicon lm thickness in a double gate SOI MOSFET with L ˆ 50 nm, N sub ˆ cm 3 and V ds ˆ 50 mv. Solid squares represent the data obtained

6 396 A. Godoy et al. / Solid-State Electronics ) 391± Conclusions This work presents a simple and accurate analytical model derived from fundamental device physics for subthreshold swing of short channel bulk and SOI MOSFETs. The expression obtained is identical to that used for long channels except for a factor k which includes the e ects of reducing the channel length. This term, k, is easily calculated, so that the model is computationally ecient and appropriate for circuit simulators where simple and accurate models are required. This model can be used for comparison of MOSFET scaling limits in bulk and SOI technologies. Acknowledgements Fig. 6. Variation of S with the silicon lm thickness for a fullydepleted double-gate Ð SOI MOSFETs with t ox ˆ 3 nm and L ˆ 0:1 lm. This work has been carried out within the framework of research project PB , supported by the Spanish Government. by Rauly et al. [16] through numerical simulation, while the solid line shows our model. The minimum silicon lm thickness used by these authors is 10 nm, which corresponds to the limit of validity of classical models in single- and double-gate SOI MOSFETs [16]. Below this thickness, quantum e ects should be taken into account. Thinning the silicon lm enhances the controllability of the gate potential on the channel region, resulting in a reduction in SCE and therefore a decrease in the subthreshold swing, as shown in the gure. Furthermore, it should be stressed that the sensitivity of S to variations of the silicon lm thickness is lower in double-gate than in single-gate SOI MOSFETs. To show this behavior explicitly, we have represented in Fig. 6 ds=dt Si where the dashed line represents a fully depleted and the solid line, a double-gate SOI transistor. To evaluate its magnitude, we have employed expression 15) to simplify the calculations. Finally, we have also reproduced the numerical results presented by Suzuki et al. [17] for double-gate SOI MOSFETs where S is represented as a function of the channel length. In their model, SCE are expressed by function exp L=2l, which is similar to our simpli ed expression 15) obtained when L 2l. As shown in Fig. 2, this approximation leads to inaccuracies when short channels are considered. Moreover, in Ref. [17] a center potential expression w c y rather than a surface one was used to calculate S. However, at weak inversion the di erences between the two expressions are negligible since for a typical device with t Si ˆ 200 A and N sub ˆ cm 3 the di erence is about 80 lv. References [1] Fiegna C, Iwai H, Wada T, Saito T, Sangiorgi E, Ricco B. Scaling the MOS transistor below 0.1 lm: methodology, device structures, and technology requirements. IEEE Trans Electron Dev 1994;41:941. [2] Agrawal B, De VK, Pimbley JM, Meindl JD. Short channel models and scaling limits of SOI and bulk MOSFETs. IEEE JSolid State Circuits 1994;29:122±5. [3] Deshpande DR, Dutta AK. A new uni ed model for submicron MOSFETs. Microelectron J1998;29: 565±70. [4] Viswanathan CR, Burkey BC, Lubberts G, Tredwell TJ. Threshold voltage in short-channel MOS devices. IEEE Trans Electron Dev 1985;32:932±40. [5] Liu ZH, Hu C, Huang JH, Chan TY, Jeng MC, Ko PK, Cheng YC. Threshold voltage model for deep-submicrometer MOSFETs. IEEE Trans Electron Dev 1993;40: 86±94. [6] Biesemans S, Kubicek S, de Meyer K. New current-de ned threshold voltage model from 2D potential distribution calculations in MOSFETs. Solid-State Electron 1996; 39:43±8. [7] Chandrakasan AP, Sheng S, Brodersen RW, Low-power CMOS digital design. IEEE JSolid State Circuits 1992;27:473±84. [8] Yan RH, Ourmazd A, Lee KF. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans Electron Dev 1992; 39:1704±10. [9] I~niguez B. Comments on ``Threshold voltage model for deep-submicrometer MOSFETs''. IEEE Trans Electron Dev 1995;42:1712. [10] Banna SR, Chan PCH, Ko PK, Nguyen CT, Chan M. Threshold voltage model for deep-submicrometer fully

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