Accurate analytical delay expression for short channel CMOS SOI inverter using Monte Carlo simulation

Transcription

1 Solid-State Electronics 43 (999) 869±877 Accurate analytical delay expression for short channel CMOS SOI inverter using Monte Carlo simulation S. Galdin*, M.-E. Arbey, P. Dollfus, P. Hesto Institut d'electronique Fondamentale, CNRS UMR 86, Universite Paris XI, BaÃtiment 0, F-9405 Orsay cedex, France Received 9 November 998; received in revised form 9 April 999 Abstract This paper reports on an analysis of propagation delay t D for deep sub-micron CMOS/SOI inverters. We derive simple propagation delay expressions for step and ramp inputs, using Monte Carlo simulation. These expressions consist of linear combinations of time constants. As a physical device simulation tool, the Monte Carlo method is well adapted to such a study, since it does not require any analytical model of electrical device parameters. The validity of the above expressions is critically checked via Monte Carlo simulation of a wide range of inverters under various load conditions. The discrepancy between calculated and simulated propagation delay is less than 0%. # 999 Elsevier Science Ltd. All rights reserved.. Introduction The switching speed of circuits is a very important parameter to be considered in the design of ULSI systems. Since pioneering work of Burns [], many authors have addressed the issue of delay modelling [±0]. Analytical propagation delay expressions are usually derived from MOS transistor models and veri- ed by comparison with SPICE simulation. The choice of the transistor model is thus the starting point that determines the accuracy of the delay calculation. First work on delay expression for long channel CMOS inverter was based on the classical Shockley MOS model for the case of input step [] or input ramp []. Some authors extended these expressions for submicron MOSFETs by using an alpha-power model that takes care of carrier velocity saturation e ect, or by including the in uence of short-circuit current and * Corresponding author. Tel: ; fax: address: sylvie.galdin@ief.u-psud.fr (S. Galdin) input-to-output coupling capacitance [3±5]. Others investigated the special case of slow input ramps by introducing empirical parameters [6±8]. Recently, delay models were derived from a BSIM drain current equation that takes into account carrier velocity saturation and vertical eld dependence of carrier mobility [9]. In this paper, we propose a quite di erent method to derive a delay expression for deep-submicron CMOS/SOI inverters (L G =0. mm). Our approach is based on physical device modelling of transistors, so that it does not need any transistor macro-model. The expression obtained takes into account all relevant physical phenomena which a device simulator is able to describe, which may be of importance to study ultra-short transistors. In fact, downscaling the active region of devices gives rise to signi cant geometric and non-stationary transport phenomena, e.g. velocity overshoot, which strongly in uence the device operation [,]. These e ects must be taken into account, not only for analysing the performance and operation of discrete deep-submicron components, but also for predictive studies of basic logic gates. The simulator /99/$ - see front matter # 999 Elsevier Science Ltd. All rights reserved. PII: S0038-0(99)0047-

2 870 S. Galdin et al. / Solid-State Electronics 43 (999) 869±877 used is the D particle Monte Carlo software we have developed [±3]. The Monte Carlo transport model consists in describing stochastically the individual motion of each carrier inside the device as a function of time, a carrier being drift by the local eld and scattered by phonons, impurities and surfaces. Ensemble Monte Carlo software is the most accurate device simulation technique that takes naturally into account non-stationary transport phenomena and is very suitable to investigate the transient behaviour of components [3,4]. In return for this accuracy, the technique requires tremendous computation time and memory resources and is mainly used for analysing single device operation. This work is thus limited to the delay analysis of the inverter, which is an unusual utilization of Monte Carlo modelling. At the present time, study of more complex gates is not reasonably conceivable using this technique, except for instance by using methods proposed for reducing a gate to an equivalent inverter [5]. In this paper, we propose simple delay expressions, as a linear combination of time constants weighted by k i factors determined from Monte Carlo device simulation. Similar delay expressions are widely used for CML and ECL gates [3,6,7]. We follow the same approach to nd a solution for CMOS/SOI inverter response, rst to an input voltage step and next to an input voltage ramp. Because of extremely large computation time needed by transient Monte Carlo modelling, we limit our investigation to quite fast input ramps (t r < 40 ps). The Monte Carlo simulation software, named MONACO and the main characteristics of the simulated CMOS/SOI transistors are described in the next Section. In Section 3, we carefully study the inverter transient behaviour and the propagation delay after applying an input voltage step. The derived delay expression is critically checked over a wide range of submicron transistors (0.±0.4 mm gate lengths). In Section 4, a similar study is made for an input voltage ramp, which leads to an expression for the propagation delay as a function of the input ramp time being in excellent agreement with a wide range of Monte Carlo results.. Model and simulated devices The Monte Carlo transport model describes the motion of each carrier in the semiconductor under the in uence of the electric eld and scattering mechanisms. For device modelling, the Monte Carlo description of carrier transport is coupled with a twodimensional Poisson equation solver. At each metal/ semiconductor interface the boundary conditions x the electrostatic potential, and in each cell contiguous Table Electrical characteristics of simulated inverters. Currents and coupling capacitance are given for W N = mm G 0. G 0. 3 G 0. 4 G 0. 5 G 0. 6 G 0. 7 G 0. 8 G 0. G 0.4 G 0.4 Units V DD V W P /W N I Dmax-N ma I Dmax-P ma V TN V V TP V C GDM ff ff C ox to an ohmic contact the average majority carrier density is xed to the impurity concentration. The latter condition is the only condition for injection of carriers, whose initial energy and momentum are speci ed by a Maxwellian distribution weighted by the velocity component perpendicular to the contact surface. Furthermore, a carrier that reaches a contact is free to leave the device. At other boundary surfaces, the normal component of the electric eld is assumed to be zero and a particle that reaches these surfaces is re ected. The instantaneous current at an electrode is calculated as the sum of the particle ow through the contact and the displacement current resulting from time variations of the electric eld at the contact. To perform CMOS inverter transient simulations, electrodes have to be loaded by an impedance. After each time step (Dt = fs) electrode potentials are updated according to the load line and to the instantaneous current. In spite of the two-dimensional (D) nature of the simulator, the simulation of two transistors with di erent widths is possible. W N and W P being respectively the N and P channel transistor widths, the ratio of W P to W N is taken into account by applying a factor W P /W N to the instantaneous P-MOSFET currents used for the time adjustment of potential at loaded electrodes. Complementary details on this D Monte Carlo simulator have been given elsewhere []. All studied structures are SOI MOSFETs. Most of them are 0. mm N and P channel fully depleted SOI MOSFETs with elevated source and drain. This source and drain geometry is recognized to improve shortchannel device characteristics [8] and hot carrier degradation [9]. The supply voltage V DD is equal to.5 V. The simulated 0. mm MOSFETs di er in the junction depth, in the gate material or in the gate oxide capacitance. A partially depleted 0.4 mm CMOS/ SOI inverter (having conventionally designed source and drain) has been also simulated with a supply voltage equal to 5 V. The nomenclature of simulated inverters is G i 0: for 0. mm gate lengths and Gi 0:4 for 0.4 mm one, where superscript i distinguishes the inver-

3 S. Galdin et al. / Solid-State Electronics 43 (999) 869± Fig.. Variations of output voltage and load current during the switching of G 0. after applying at t = 0 a falling input step with C L =4 ff. ters. The characteristics of the transistors forming the di erent inverters are summarized in Table. The D character of the simulation implies that all admittances and currents should be naturally expressed per unit of the third dimension. In order to express these quantities in units commonly used in circuit design, we arbitrarily x W N to mm for all transistors throughout this work. The con guration ratios W P / W N are given in Table. C L is the output load capacitance, representing the wiring capacitance between two stages and the input capacitance of the next stage. C GD-N and C GD-P are the gate-to-drain capacitances of N- and P-MOSFETs respectively. We de ne C GD as the input-to-output coupling capacitance of the inverter, formed by the gate-to-drain capacitances connected in parallel: C GD ˆ C GD-N C GD-P. We will use a speci c value of C GD, called C GD-M and de ned as the sum of C GD-N and C GDP values obtained respectively for jv GS jˆjv DS jˆv DD. I N-max and are the maximum source±drain static current of both transistors, de ned for jv GS jˆjv DS jˆv DD. In the CMOS inverter, the convention chosen for positive direction of source and drain currents is from V DD to the ground. To characterize the switching speed of an inverter, we choose the standard de nition of the delay time t D, i.e. the time from the half-v DD point of the input to the half-v DD point of the output. A distinction is made between t Df, the high-to-low delay (output falling) and t Dr, the low-to-high delay (output rising). The propagation delay t D is then the average of t Df and t Dr. 3. Step response The rst purpose of this paper is to express the propagation delay of CMOS inverter t D-st in response to a voltage step. The result obtained will be useful to analyze the more realistic case of an input voltage ramp (Section 4). An example of the output voltage response to a falling input step is plotted in Fig., for G 0. with a load capacitance C L of 4 ff. The output voltage variation results from the charging of the load capacitance C L through the inverter. The load current I L, calculated as the di erence between the P-MOSFET drain current and the N-MOSFET one, is also plotted in Fig.. The total propagation delay may be broken-down in two parts corresponding to two regions well distinct in Fig.. Region : there is an output voltage overshoot lasting a time t Dr-st.. Region : the output voltage increases from 0 to V DD /=0.75V during a time t Dr-st, corresponding to the charging of the load capacitance C L by a nearly constant current I L-max. The study of these two delay times t Dr-st and t Dr-st will lead to express the total rise delay t Dr-st (t Dr-st ˆ t Dr-st t Dr-st) as a linear combination of time constants of the circuit, with each of them weighted by a factor determined by the inverter topology. The nal expression of t D-st will only depend on the supply voltage V DD, the load capacitance C L, the maximum drain current of both transistors I N-max and and the above de ned characteristic value of the input-tooutput coupling capacitance C GDM. From their de nition, the transistor parameters I N-max,, C GDM used in the analytical expression of t D-st are independent of the inverter switching conditions. The variations of these electrical parameters during the switching are taken into account by universal weighting factors. Their values will be determined from data points of a particular inverter, for example G 0. Veri cation of their uniqueness, that is to say their independence of transistor geometry, will be made by comparing the propagation delay expression with data. points obtained from di erent transistor geometries (G i 0: and Gi 0:4, with ir). 3.. Region : determination of t D-st The output voltage variation DV o results from the charging of the load capacitance C L with the load current I L. During the rst part of the propagation delay, t Dr-st, the load current I L increases up to a maximum value I L-max, as shown in Fig.. We assume that the variation of the load current may be simply taken into account by introducing a universal weighting factor k si, so that t Dr-st corresponds exactly to the charging of C L by a constant current I L-max=k si that is the average load current over t Dr-st. We have then

4 87 S. Galdin et al. / Solid-State Electronics 43 (999) 869±877 Fig.. Output voltage, source and drain currents of complementary transistors as a function of time, for G 0. after applying a falling input step with C L = ff. t Dr-st ˆ DV o k si I L-max C L with DV o ˆ V over The output voltage overshoot V over is due to the application of an input voltage step at one side of the inverter coupling capacitance C GD. Its value is given by the voltage divider formed by the capacitances C GD and C L ksc 0 V over ˆ V C GDM DD C L ksc 0 C, GDM where k' sc is the ratio of the C GD value at the beginning of the switching to C GDM. The value of k' sc factor is determined in order to satisfy Eq. () for the considered inverter G 0.. We nd k 0 sc ˆ :48: For several inverters the values of the output voltage overshoot V over calculated from Eq. () have been compared with corresponding values deduced from transient Monte Carlo simulation. The agreement is very good, with an error inferior to 0%. We have now to express the maximum value of the load current I L-max as a function of static currents that are easily extractable in practice. In Fig., the variations of source and drain currents for both N- MOSFET (I S-N and I D-N ) and P-MOSFET (I S-P and I D-P ) are plotted as a function of time in the case of a falling step with a load capacitance C L of ff. The N- channel transistor is initially on and the P-channel is o, thereby keeping the output low. As the input step is falling, the N-channel transistor is turned o and electrons go out of the channel by source and drain as shown in Fig.. The P-channel transistor is turned on and holes are injected into the transistor by source and drain electrodes simultaneously (Fig. ). In the region, the N-MOSFET is o, the load current is equal to the drain P-MOSFET current: I L ˆ I D-P. 3 Fig. 3. Variations of the P-MOSFET source and drain transient currents (noisy solid and dashed lines) as a function of output voltage during the switching of G 0. for C L = ff. Static drain characteristics of the P-MOSFET are superimposed (dots connected by smooth curves). The di erence between drain and source currents originates from the displacement gate currents through the gate-to-drain capacitances C GD-N and C GD-P of both transistors. In region, the CMOS inverter can be modeled by the current divider structure formed by C GD and C L, that leads to the relation between I L and I S-P I L ˆ I S-P C L C L ksc 00 C, 4 GDM where k0 sc is a weighting factor taking into account the variation of C GD during the time t Dr-st. In Fig. 3, the variations of the transient source (I S-P ) and drain (I D- P) currents during the switching (noisy solid and dashed lines), with C L = ff as in Fig., are superimposed upon the static drain current characteristics of the P-MOSFET (symbols connected by smooth curves). In region, the output voltage V 0 varies from 0toV DD /=0.75 V. As we can observe in Fig. 3, the P-MOSFET source current I S-P is close to the maximum drain current de ned at jv GS jˆjv DS jˆv DD. In this region, the load current I L is nearly also constant and equal to I L-max. Eq. (4) becomes I L-max ˆ C L C L k 00 sc C GDM According to the previous remarks, i.e. I L and I SP are constant in region, the capacitance C GD does not vary signi cantly in this region (Eq. (4)) and k0 sc is thus the ratio of the C GD value in region to C GDM. The value of k0 sc factor is determined to satisfy Eq. (5) for the device G 0. used as reference. We nd k 00 sc ˆ :95: 5 6

5 For several inverters the values of the maximum load current I L-max calculated from Eq. (5) have been compared with corresponding values deduced from transient Monte Carlo simulation. In the latter case of rising steps, Eq. (5) is of course modi ed by changing into I N-max. The agreement is good, with an error inferior to 5%. Substituting Eq. () and Eq. (5) in Eq. () yields the following t Dr-st expression S. Galdin et al. / Solid-State Electronics 43 (999) 869± k si ksc 0 C L ksc 00 t Dr-st ˆ V DD C C GDM GDM C L ksc 0 C GDM 7 The value of the k si factor is determined to satisfy Eq. (7) for the reference device G 0.. We obtain k si ˆ :3: 8 Considering the values of k' sc and k0 sc (Eq. (3) and Eq. (6)) and realistic C L values (C L > C GDM ), the member (C L ksc 00 C GDM = C L ksc 0 C GDM is always close to. Hence, Eq. (7) is nicely simpli ed as k si ksc 0 t Dr-st ˆ V DD C GDM with k si ˆ :3 and k 0 sc ˆ :48: Symetrically, the part of the propagation delay associated to the region, in response to a rising step can be written as k si ksc 0 t Df-st ˆ V DD C GDM I N-max with k si ˆ :3 and k 0 sc ˆ :48: 9 0 Finally, the part of the propagation delay t D-st,in region, is given by t D-st ˆ VDD I N-max 3.. Region : determination of t D-st :9C GDM In this region, the load current has reached a maximum value I L-max and the associated part t Dr-st of the propagation delay is given by t Dr-st ˆ DV o C L I L-max withdv o ˆ VDD Substituting Eq. (5) in Eq. () yields t Dr-st ˆ VDD with k 00 sc ˆ :95: C L k 00 sc C GDM 3 Fig. 4. Propagation delay for an input step applied to many inverters. The computed values (symbols) are compared to calculated ones from Eq. (6) (straight lines). Symetrically, the part of the propagation delay associated to region, in response to a rising step can be written t Df-st ˆ VDD C L ksc 00 I C GDM N-max with ksc 00 ˆ :95: 4 The part of the propagation delay t D-st, in region is thus given by the expression t D-st ˆ VDD 4 I N-max C L :95C GDM : 3.3. Validation of the analytical total delay expression in response of a voltage step 5 Considering Eqs. () and (5), the total propagation delay in response to a step voltage t D-st is nally given by t D-st ˆ VDD 4 with k s ˆ 5:8: I N-max C L k s C GDM 6

6 874 S. Galdin et al. / Solid-State Electronics 43 (999) 869±877 Fig. 5. Computed total propagation delay as a function of input ramp time for G 0. and with di erent load capacitance values. Validation of the propagation delay expression (Eq. ()) in response to a ramp voltage. The computed values (symbols) are compared to calculated ones (straight lines). Closed triangles separate region from region (t=t r0 ) and closed circles separate region 3 from region (t r =t r-lim ). The validation of this propagation delay expression derived for downscaled SOI transistors is carried out by comparing, in Fig. 4, t D-st values given by Eq. (6) with the corresponding results of Monte Carlo simulation (symbols). The veri cation is made for several CMOS inverters G i 0: and Gi 0:4 not used to establish Eq. (6). Their electrical parameters are listed in Table. The values predicted by Eq. (6) agree well with the simulation with an error less than 5%. 4. Ramp response The second purpose of this paper is to get an accurate expression of propagation delay t D-rp resulting from an input voltage ramp characterized by the input ramp time t r. We plot in Fig. 5 for G 0. the computed total propagation delay t D-rp as a function of input ramp time t r. Several values of the load capacitance C L are considered. For now, ignore the close symbols. Three regions are well de ned:. Region : as long as t r < t r0 the propagation delay remains constant and equal to the step-response propagation delay (t r =0), previously determined in Eq. (6). This threshold ramp time t r0 seems to be independent of the load capacitance.. Region : the propagation delay is a linear function of the input ramp time t r as long as t r < t r-lim.as we can observe in Fig. 5, the value of t r-lim seems to be dependent on C L.. Region 3: for t r >t r-lim, the propagation delay is less and less linear as a function of the input ramp time t r. This case occurs for long input transition times Fig. 6. Superposition of di erent falling input ramp (dashed straight lines) and corresponding output voltage responses for G 0. with C L =4 ff. (R: t r =0, q: t r =5 ps, r: t r =0 ps). The time scale is chosen so that t = 0 is the starting time for the ramp propagation delay. and/or for small capacitive loads. Despite it is an important feature for designers, we do not develop any speci c expression for the delay in this region that requires tremendous CPU times to be fully investigated by using our approach. Comprehensive studies of slow input ramp transitions may be found in Refs. [5±9]. To summarize, the ramp-response propagation delay t D-rp can be written t D-rp ˆ td st for t r <t r0, region t D-st a t r t r0 for t r0 <t r, region, 7 where a and t r0 have to be determined. 4.. Region : determination of t r0 We plot in Fig. 6 the output voltage responses for di erent falling ramp times ranging from 0 to 0 ps. The time scale is chosen so that t=0 is the starting time for the propagation delay (V I =0.75 V). For each input ramp, the time axis is displaced so that all the input voltages intersect at a common point M de ned by t(m)=0 and V I (M)=V DD /. The point M is thus the propagation delay starting point. To determine the value of t r0, it is also useful to de ne in Fig. 6 the point P corresponding to the overshoot ending in the case of input step. This point P is thus de ned by V o (P)=0 and t P ˆt D-st. If, in Fig. 6, the intersection of the input ramp with time axis is on the left of point P, e.g. for t r =5 ps, the resulting output voltage is superimposed, after the overshoot, with that corresponding to the input step and is the same for all input ramps meeting this condition: t r =<t D-st. As a consequence, the propagation delay remains independent of t r and identical to the input step delay. On the contrary, if the intersection of

7 S. Galdin et al. / Solid-State Electronics 43 (999) 869± Fig. 7. Superposition of di erent falling input ramp (dashed straight lines) and corresponding output voltage responses for G 0. with C L =4 ff. (q: t r =5 ps, r: t r =0 ps, r: t r =0 ps, t: t r =00 ps). The time scale is chosen so that t = 0 is the end of the ramp propagation delay. the input ramp with time axis is on the right of P, i.e. for t r = > t D-st, the propagation delay obviously increases with t r. The threshold ramp time t r0 that separates region from region is thus de ned as twice t D-st. According to Eq. (), this yields t r0 ˆ V DD :9C GDM 8 I N-max We can notice that, as predicted from Fig. 5, this threshold ramp time t r0 is independent of the load capacitance. 4.. Region : determination of t D-rp Fig. 8. Description of gate contacts surfaces in G 0. (b). G 0. ne the limit ramp time t r-lim as the input ramp ending at t = 0, i.e., t r-lim= ˆ t D-rp. Applying Eq. (7), this de nition yields t r-lim ˆ t D-st ˆ at r0 a (a) and 9 Fig. 7 is a plot of output voltage responses for a number of di erent falling input ramp times, ranging from 5 to 00 ps. In this gure, the di erent output voltages are displaced on the time axis so as to intersect at a common point L de ned by V o (L)=V DD /. The time origin is de ned at the point L, with t(l)=0 and is thus associated, by de nition, to the end of all propagation delays. The basic point to notice in Fig. 7 is that for the smallest ramp times, i.e., for t r lying between 5 and 0 ps, the input voltages intersect at a common point, noted N. Simple geometric considerations imply that for such switchings, the propagation delay increases linearly with the ramp time t r, which is in agreement with Eq. (7) for t r >t r0 (region ). We also observe that these input ramps intersect the time axis on the left of point L (i.e. at t < 0). On the contrary, for high values of t r, e.g. 00 ps in Fig. 7, the input ramps intersect the time axis on the right of point L (i.e. at t>0). Furthermore, these input ramps do not intersect the point N, so that the propagation delay is no more a linear function of t r. These observations lead to de- The linearity of the propagation delay as a function of the ramp time over a limited range of ramp times has been demonstrated. We have now to determine the coe cient a, de ned in Eq. (7), as a function of electrical parameters of both transistors as the threshold voltages V TN and V TP, the inverter coupling capacitance C GDM and the load capacitance C L. To investigate the dependence of a on these electrical elements, we have changed their values one by one. To study the C GD dependence of propagation delay, we have changed the oxide capacitance C ox, without modifying the threshold voltages. This has been obtained by reducing the gate contact surface as shown in Fig. 8: the gate contact surface of G 0. transistors (Fig. 8b; C ox =C ox ) is smaller than that of G 0. transistors (Fig. 8a; C ox =C ox ), but the gate control of the channel remains unchanged. The variation of C ox yields a shift of the step propagation delay t D-st but does not modify the slope a of t D-rp. Similarly, the slope remains independent of the load capacitance C L. Therefore, this slope a is independent of C GD and C L. To analyze the symmetrical e ect of both threshold voltages, V TN and V TP, we have modi ed each of them independently of each other. We have shifted the applied gate voltage of one transistor that is equivalent to a shift DV T of its threshold voltage. a depends on the threshold voltages of both transistors and this dependence is symmetrical because the same shift DV T applied to the threshold voltages of the N or P channel transistors yields the same propagation delay. Hence a

8 876 S. Galdin et al. / Solid-State Electronics 43 (999) 869±877 Fig. 9. Validation of the propagation delay expression (Eq. ()) in response to a ramp voltage. The computed values (symbols) are compared to calculated ones (straight lines). Closed triangles separate region from region (t=t r0 ) and closed circles separate region 3 from region (t r =t rlim ). can be written as VTN a ˆ k r0 k r jv TPj V DD V DD 0 With two inverters presenting two di erent values of slope a, we have determined the values of in uence coe cients k r0 and k r. In the considered region the ramp-response propagation delay t D-rp can be nally written VTN t D-rp ˆ t D-st t r t r0 k r0 k r jv TPj V DD V DD with k r0 ˆ 0:09 and k r ˆ 0:3: 4.3. Validation of the analytical delay expression in response of a ramp voltage The validation of the propagation delay expression (Eq. ()) for downscaled SOI transistors is carried out by comparing, in Figs. 5 and 9, the values predicted by the new propagation delay expression (Eq. ()) with the results of Monte Carlo simulation. The open plots are the results of Monte Carlo simulation for di erent values of load capacitance (Fig. 5) or for di erent inverters (Fig. 9). The closed triangles are the calculated values of t r0 (from Eq. (8)) and the closed circles are those of t r-lim (from Eq.(9)) delimiting the three di erent regions previously described. The straight line is plotted from the predicted expression (Eq. ()) of the ramp response propagation delay derived for the region. We notice that even for the asymmetric inverter G 0. with di erent threshold voltage values for 3 complementary transistors, the predicted delays agree very well with results of Monte Carlo simulations with an error less than 0%. In the region 3 (t r >t r-lim ), the propagation delay is no more a linear function of the input ramp time. In this region the output voltage varies more rapidly than the input one: the output voltage reaches V DD / before the end of the input ramp. In the extreme case of in nite input switch time and zero capacitive load, that is to say the quasi-static conditions, the propagation delay may become zero and even negative. Hence, it cannot be modelled in all the region 3 by a linear ascending function of the input ramp time. But, as may be seen in Fig. 5, the straight line remains a good approximation over a wide range of input ramps and may be used even in this region with a reasonable error for an e ective limit time about t r-lim. We have not checked this e ective limit time for high C L and we have not derived any speci c delay expression for this region because of terri c CPU time needed. At the present time, studies of propagation delay for ramp times higher than those simulated in this work are actually not reasonably conceivable using Monte Carlo technique. 5. Conclusion Simple and accurate analytical expressions for the step response and the ramp response propagation delay of CMOS/SOI inverters have been derived. The step response propagation delay expression is a linear combination of time constants weighted by universal factors determined from Monte Carlo simulation. The ramp response propagation delay expression is, over a wide range of ramp time values, a linear function of the input ramp time with a slope depending only on the threshold voltage of both N and P transistors. These expressions are simple to use since they require only the knowledge of some electrical parameters of N and P channel transistors. They do not depend on a model for the transistor currents. These new timing expressions include the e ects of the inverter coupling capacitance, no more negligible for short channel transistors and they are valid for asymmetric inverters in which the absolute value of threshold voltage is not the same for N-MOSFET as for P-MOSFET. We have limited our investigation to SOI technology, where junction capacitances between substrate and source/ drain contacts are weak. In the case of bulk technology, these capacitances could in uence the timing model. This should be studied in future work. The downscaling of device geometry (from 0.4 to 0. mm) has led us to use an accurate physical simulator. The particle Monte Carlo technique was the most powerful tool for such investigation. The propagation delays calculated from the predictive expressions agree

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