NRAM: High Performance, Highly Reliable Emerging Memory
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1 NRAM: High Performance, Highly Reliable Emerging Memory Sheyang Ning,2, Tomoko Ogura Iwasaki, Darlene Viviani 2, Henry Huang 2, Monte Manning 2, Thomas Rueckes 2, Ken Takeuchi Chuo University 2 Nantero Inc. Santa Clara, CA
2 Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 2
3 Introduction of NRAM Performance DRAM NRAM Nano-RAM, Carbon nanotube based resistive memory NAND flash Santa Clara, CA 3
4 Compare with Conventional Memories = good Performance Scalability Endurance Non-volatile = bad DRAM NAND flash NRAM 20 ns pulse [] Single cell 5 nm [2] Single cell 0 2 [3] 000 years@ 85ºC [2] []. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp [2]. Nantero Presentation for ITRS ERD/ERM, International Technology Roadmap for Santa Clara, CA Semiconductors (ITRS), 203. [3]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept
5 Compare with Emerging Memories Material Resistive switching on read ReRAM [] PRAM [2] NRAM [3] Al x O y Ge 2 Sb 2 Te 5 Filament size Phase change Carbon nanotube (CNT) Tunneling current between CNTs Endurance Current High High Low []. S. Ning et al., Solid-State Electronics, vol. 03, pp , Jan., 205. [2]. H. Y. Cheng et al., IEEE Int. Electron Devices Meeting, 203, pp [3]. S. Ning et al., Symp. on VLSI Tech., 204, pp [4]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp Santa Clara, CA 5
![, Jun. 204, pp. 20 2. Santa Clara, CA [2].](/docs-images/75/71831985/images/6-3.jpg "Nantero presentation, Int. Tech.")
6 Physical Mechanism R cell 800 kω Small distance R cell GΩ Large distance []. S. Ning et al., in VLSI Symp. Tech. Dig., Jun. 204, pp Santa Clara, CA [2]. Nantero presentation, Int. Tech. Roadmap for Semiconductors (ITRS),
7 Physical Mechanism Set: attraction force Reset: repulsive force Electrical induction + Heat caused phonon vibration []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept Santa Clara, CA 7
8 Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 8
9 Single NRAM Cell and Cell Array Test 40 nm NRAM single cell 6 nm, 4 Mbits NRAM cell array V d NRAM cell WL BL 0 SL 0 BL N SL N V g NRAM cell BL SL Oscilloscope NRAM testchip Set voltage Reset voltage +V Set 0 V 0 V +V Reset []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept Santa Clara, CA [2]. G. Rosendale et al., Proceedings of the European Solid-State Circuits Research Conference (ESSCIRC), Sept. 200, pp
10 Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 0
11 I d (µa) DC-IV Curve Single cell bi-polar program Set Reset Butterfly curve V d (V) V d (V) []. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp Santa Clara, CA I d (µa) Current vibration due to long term voltage stress on CNTs Same cell, reset curve Trigger voltage
12 Low Program Current Single cell DC I compliance = 5 µa, 30 µa, and 00 µa Current (A) µa 30 µa 5 µa Set Voltage Reset Single cell AC I peak < 20 µa Reset Current (µa) Time (ns) 0.72pJ Time (ns) []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept Santa Clara, CA [2]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp Set Current (µa) pJ Voltage (V) Voltage (V)
13 Reset Characteristic l Cell array measurement, Reset is driven by both voltage and current BL = 0 V SL=V program WL= V gate Reset BER (a.u.) WL=0.4 a.u., SL from 0 to a.u Santa Clara, CA []. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp
14 Program voltages (a.u.) Program voltages (a.u.) Set and Reset Voltages l Use incremental pulse programing on single cell Reset voltage Set voltage (absolute value) Write cycles Write cycles Cumulative program success l Three randomly chosen NRAM cells 00% 80% 60% 40% 20% 0% Reset []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept Santa Clara, CA 4 cell cell 2 cell 3 Reset voltage (V) Cumulative program success 00% 80% 60% 40% 20% 0% Set cell cell 2 cell 3 Set voltage (V)
15 l Single cell measurement Large On/Off Ratio > 00 times on/off ratio Possible for multi-level cell (MLC) Resistance (Ω) Read at V Resistance Ω 0 5 Ω Read cycles []. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp Santa Clara, CA 5
16 High Temperature Program l Single cell measurement, stable program voltage at different temperatures Reset failure rate (a.u., log scale) Reset Reset voltage (a. u.) Set voltage (a.u.) Santa Clara, CA []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept Set failure rate (a.u., log scale) Set
17 Resistance (Ω) High Endurance Single cell Cell array Reset BER 0 7 HRS.25MΩ 4 Set BER LRS 200kΩ Write cycles Program BER (a.u.) Write cycles []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp , Sept Santa Clara, CA [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp
18 High Endurance l Cell array does not wear-out after 0 8 write cycles Set BER (a.u.) Set BER after 0 3 write cycles Set BER after 0 8 write cycles Set voltage Verify-set pulses Set BL voltage (a.u.) Reset BER after 0 3 write cycles Reset BER after 0 8 write cycles Reset voltage Verify-reset pulses []. S. Ning et al., Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 206. Santa Clara, CA [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp Reset BER (a.u.) Reset SL voltage (a.u.)
19 Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 9
20 Conclusion l NRAM is an emerging nonvolatile memory cell which has performance between DRAM and NAND flash. l Compared with other emerging nonvolatile memories, NRAM has competitive characteristics, including, lower program current, large on/off ratio, large endurance, high temperature stability and long retention time. Santa Clara, CA 20
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