SEU RADIATION EFFECTS ON GAA-CNTFET BASED DIGITAL LOGIC CIRCUIT

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1 International Journal of Mechanical Engineering and Technology (IJMET) Volume 9, Issue 7, July 2018, pp , Article ID: IJMET_09_07_039 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed SEU RADIATION EFFECTS ON GAA-CNTFET BASED DIGITAL LOGIC CIRCUIT Singh Rohitkumar Shailendra Student (M.Tech. by Research), Department of Micro and Nanoelectronics, SENSE, VIT, Vellore, Tamilnadu, India V N Ramakrishnan Associate Professor, Department of Micro and Nanoelectronics, SENSE, VIT, Vellore, Tamilnadu, India ABSTRACT Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) based digital logic circuits are studied in this paper for their soft error performance using Cadence simulations. Four different topologies Single Chirality Single Channel (SCSC), Single Chirality Dual Channel (SCDC), Dual Chirality Single Channel (DCSC) and Dual Chirality Dual Channel (DCDC) based digital logic circuits are studied to find out their minimum radiation dose required to flip the digital circuits output. A double-exponential current pulse is induced at respective sensitive node of the digital circuits. The digital gates retain its original state after radiation dose is removed. The simulation result shows SCDC and DCDC based topology for inverter is more reliable because its highest threshold current value is 5.4 µa and 5.8 µa respectively where as SCSC and DCSC topology for inverter is less reliable with lowest threshold current value 2.95 µa and 2.80 µa respectively. In NAND and NOR gate circuits similar result is given in this paper. Key words: Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA- CNTFETs), Single Event Upset (SEU), Radiation, Digital gates, Threshold current. Cite this Article: Singh Rohitkumar Shailendra and V N Ramakrishnan, SEU Radiation Effects on GAA-CNTFET Based Digital Logic Circuit, International Journal of Mechanical Engineering and Technology 9(7), 2018, pp INTRODUCTION The scaling down of the devices was the driving force towards technological progress. The size of the individual devices in an integrated circuit followed by Moore's law [1]. Today Silicon based MOSFETs have a technological dimension less than 45 nm are common in the semiconductor world industry. Since the size becomes very small, the scaling of traditional silicon MOSFETs turns out to be progressively harder. Any scaling has featured serious limits involving fabrication technology and device performance. These limits incorporate the quantum mechanical tunneling of carrier through the thin layer of gate oxide, quantum editor@iaeme.com

2 Singh Rohitkumar Shailendra and V N Ramakrishnan mechanical tunneling of carrier from source to drain terminal and from drain terminal to body, control of the thickness and area of doping atoms in the MOSFET channel and source-drain region to give high on-off current ratio and finite sub-threshold slope. The Researcher proposed many solutions to overcome these limitations. Some solutions include modification of the traditional existing structures and technologies with an expectation of extending their scalability. Different solutions involve the use of new materials and technologies to replace the traditional silicon MOSFETs. Researchers are currently concentrated on distinguishing the alternatives that could enable continued improvement in the performance of device are high dielectric material (High-K), metal gate electrode and double gate FET. High-K dielectric materials are very useful for gate insulators as they will give efficient charge injection into channel of the device and decrease direct tunneling leakage currents. The Very Large Scale Integration (VLSI) systems depend on traditional Si-MOS technology has expected that in the nano regimes the expected high density can encounter substantial difficulties in terms of physical phenomena and technology limitations, possibly preventing the continued improvements in figures of merit such as low power and high performance. They have focused alternative devices such as bulk silicon transistors and ultrathin body devices such as FinFETs. These limits may be overcome to some extent and modifying the channel material with a single-walled carbon nanotube instead of Si in the traditional MOSFET structure. Despite all the challenges related with scaling of transistor, they have focused towards improving carrier transport in the transistor channel region [2]. One potential possibility is to use Carbon Nanotube (CNT) to realize high channel mobility in the device [3] Carbon Nanotube (CNT) Figure 1 Structure of (a) Graphene (b) SWCNTs (C) MWCNTs Carbon Nanotubes are rolled sheet of graphene having cylindrical shapes. Planar structure of graphite is organized in a hexagonal structure due to its Sp 2 hybridization. Carbon nanotubes also have this honeycomb structure on a molecular level. S.Ijima observed first Carbon nanotube in 1991 which have unique mechanical, thermal and electrical properties [4]. Fig.1 shows the structure of single-walled carbon nanotube. Carbon nanotubes offer alternative uses in various applications such as electron source in field emission devices, interconnects and FETs [5]. The Carbon Nanotube in Fig.1 (b) shows that one layer of carbon atoms this is often known as Single-Walled Carbon Nanotubes (SWCNT). There are Multi-Walled Carbon Nanotubes (MWCNT) having different layer of SWCNTs of different diameters. The diameter of Single walled Carbon Nanotube changes between 0.7 nm to 3 nm [6]. The editor@iaeme.com

3 SEU Radiation Effects on GAA-CNTFET Based Digital Logic Circuit importance of CNT diameter is that determine the threshold voltage and bandgap of the tube. The following relation is given to threshold voltage and bandgap of the tube as shown in Eq.1 and Eq.2. V Th =. (1) E gap =. (2) Where q is electronic charge, a=2.49 Å is the lattice constant, bond energy and is the diameter of Carbon Nanotube. =3.033eV, is the carbon 1.2. Gate-All around CNTFET (GAA-CNTFET) Carbon Nanotube Field Effect Transistors (CNTFETs) uses semiconducting behaviour CNT as a channel material instead of Silicon. The behaviour of SWCNT can be either metallic or semiconducting; it depends on the arrangement of the atom in the tube. The arrangement of the atom is referred as the chirality vector and it is represented by the integer pair (n, m). A simple method to find SWCNT is metallic if n=m and n-m = 3K, where K is an integer otherwise the behaviour of SWCNT is semiconducting [7]. The diameter of CNT is calculated as shown in Eq.3. D CNT = (3) Where (n, m) is the chirality indexes of Carbon Nanotube and a = nm inter atomic distance between each carbon atom and its neighbor carbon atom. Similar to the traditional Si-MOSFET, the GAA-CNTFET also has four terminals as shown in Fig. 2(a). Side and top view of GAA-CNTFET is as shown in Fig. 2(b) and Fig. 2(c) respectively. The GAA-CNTFET provides unique property to control the threshold voltage by changing the diameter or changing the chirality of CNT. Quantum Capacitance plays major role in GAA-CNTFET device [8]. The I-V Characteristics of the GAA-CNTFET for different diameter are shown in Fig. 4. The threshold voltage of the device is defined as the minimum voltage required to turn-on the transistor. The threshold voltage of the GAA-CNTFET is an inverse of the diameter of CNT. Figure 2 (a) Structure of GAA-CNTFET (b) side view of GAA-CNTFET (c) Top view of GAA- CNTFET editor@iaeme.com

4 Singh Rohitkumar Shailendra and V N Ramakrishnan 2. GAA-CARBON NANOTUBE FIELD EFFECT TRANSISTORS (CNTFETS) BASED LOGIC GATES The GAA-CNTFET is promising candidate to replace the traditional silicon transistor because of low power and high performance. GAA-CNTFET based device can be used as different application such as memories and all digital circuits [9]. In this paper, we have designed an inverter circuit, NAND circuit and NOR circuit as shown in Fig. 3. The Pull-up network (PUN) is implemented using p-type GAA-CNTFET and the pull-down network (PDN) is implemented using n-type GAA-CNTFET. The current pulse as shown in Fig. 5. is applied to the output node of all digital gates. In this paper, we have analysed the SEU Effect of GAA- CNTFET in digital gates. This digital circuit is investigated and analysed as follows: 1. Single Chirality Single Channel (SCSC) 2. Single Chirality Dual Channel (SCDC) 3. Dual Chirality Single Channel (DCSC) 4. Dual Chirality Dual Channel (DCDC) Figure 3 Structure of (a) NOT Gate (b) NAND Gate (c) NOR Gate Figure 4 I-V Characteristic of GAA-CNTFET for different diameter editor@iaeme.com

5 SEU Radiation Effects on GAA-CNTFET Based Digital Logic Circuit Figure 5 Double exponential current pulse with rise time start=20 ns, rise time constant=1 ns, fall time start=21 ns and fall time constant=1 ns 3. SIMULATION RESULT OF SEU EFFECT ON GAA-CARBON NANOTUBE FIELD EFFECT TRANSISTORS (CNTFETS) BASED DIGITAL GATES The Simulation results of inverter with current pulse are shown in Fig. 6 and Fig. 7 respectively. The simulation result shows that Single Chirality Dual Channel (SCDC) and Dual Chirality Dual Channel (DCDC) based topology for inverter is more reliable because its highest threshold current value is 5.4 µa and 5.8 µa respectively where as Single chirality Single Channel (SCSC) and Dual Chirality Single Channel (DCSC) topology for inverter is less reliable with lowest threshold current value 2.95 µa and 2.80 µa respectively. The flow of electron at output node is very less in single channel due to that threshold current value is very less for SCSC and DCSC topology. The Simulation result of NAND gate with current pulse are shown in Fig. 8 and Fig. 9 and result of NOR gate with current pulse are shown in Fig. 10 and Fig. 11. The threshold current value is more for SCDC and DCDC topology whereas threshold current Value is less for SCSC and DCSC topology for NAND and NOR gate as shown in Fig. 8, 9, 10 and 11. The simulation result of different dielectric material (K) for gate oxide is shown in Fig. 12 and different oxide thickness (t ox ) is shown in Fig. 13. From the simulation result, we can say that threshold current value is more for high dielectric material and greater oxide thickness. Figure 6 Simulation result of inverter for Single Chirality editor@iaeme.com

6 Singh Rohitkumar Shailendra and V N Ramakrishnan Figure 7 Simulation result of inverter for Dual Chirality Figure 8 Simulation result of NAND for Single Chirality Figure 9 Simulation result of NAND for Dual Chirality editor@iaeme.com

7 SEU Radiation Effects on GAA-CNTFET Based Digital Logic Circuit Figure 10 Simulation result of NOR for Single Chirality Figure 11 Simulation result of NOR for Dual Chirality Figure 12 Simulation result of inverter for different dielectric material

8 Singh Rohitkumar Shailendra and V N Ramakrishnan Figure 13 Simulation result of inverter for different oxide thickness 4. CONCLUSIONS The effect of radiation on digital gates based on GAA-CNTFET is investigated. Double exponential studies of different digital gates with different topologies are done to compute the threshold current value and perturbation rate. From the Simulation result we observed that Single Chirality Dual Channel (SCDC) and Dual Chirality Dual Channel (DCDC) based topology for all digital gate is more reliable because its highest threshold current value where as Single chirality Single Channel (SCSC) and Dual Chirality Single Channel (DCSC) topology for all digital gate is less reliable with lowest threshold current value. REFERENCES [1] Moore, G. E. "OTHERS. Progress in digital integrated electronics." IEDM Tech. Digest 11 (1975). [2] Datta S., T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes et al. "85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications." In Electron Devices Meeting, IEDM Technical Digest. IEEE International, pp IEEE, (2005). [3] Dürkop, T., T. Brintlinger, and M. S. Fuhrer. "Nanotubes are high mobility semiconductors." In AIP Conference Proceedings, vol. 633, no. 1, pp AIP,(2002). [4] S. Iijima "Helical microtubules of graphitic carbon." nature 354, no (1991): 56. [5] R.Martel, H-SP. Wong, Kevin Chan, and Phaedon Avouris. "Carbon nanotube field effect transistors for logic applications." In Electron Devices Meeting, IEDM'01. Technical Digest. International, pp IEEE, (2001). [6] Dresselhaus Mildred S., and Phaedon Avouris. "Introduction to carbon materials research." In Carbon nanotubes, pp Springer, Berlin, Heidelberg, (2001). [7] Deng, Jie, and H-S. Philip Wong. "A compact SPICE model for carbon-nanotube fieldeffect transistors including nonidealities and its application Part II: Full device model and circuit performance benchmarking." IEEE Transactions on Electron Devices 54, no. 12 (2007): [8] Singh Rohitkumar Shailendra and V. N. Ramakrishnan. "Analysis of quantum capacitance on different dielectrics and its dependence on threshold voltage of CNTFET." In Nextgen editor@iaeme.com

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