CHAPTER 3 CAPACITANCE MODELLING OF GATE WRAP AROUND DOUBLE-WALLED ARRAY CARBON NANOTUBE FIELD EFFECT TRANSISTOR

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1 52 CHAPTER 3 CAPACITANCE MODELLING OF GATE WRAP AROUND DOUBLE-WALLED ARRAY CARBON NANOTUBE FIELD EFFECT TRANSISTOR 3.1 INTRODUCTION Carbon nanotube is most the expected potential challenger that will replace Si in the near future with high electrical performance. With ballistic transport, larger drive current flow is found in CNTFET compared to its Si counterpart and excels in its output. The strengths of CNT are explored highly in the past decade. It will occupy a greater space in the electronic world with its unique physical, electrical, chemical and mechanical properties. CNTFET hold ballistic transport with high carrier velocity due to ultra-long mean free path (MFP). Highly aligned CNTs were grown on full wafer scale for the construction of complex logic gates with stable and complementary n- and p- channel MOSFETs on a single chip. It is necessary for a device to operate at room temperature. Sander J Tans et al (1998) reported about the fabrication of semiconducting carbon nanotube FET. The device operated at room temperature with high switching speed. Semi-classical band-bending models for explaining the device electrical characteristics were utilized. Ali Javey et al (2003) shared the work on contacts of semiconducting Single-walled Carbon Nano Tube transistor (SWCNT). Using the contacts of Nano tubes with high work function and wetting interactions like palladium, the transport barrier through valence band

2 53 of the tube was greatly reduced. It was found that that diffusive transport model did not suit for the short channel length Nano tube devices and only ballistic transport model was appropriate. A fabrication technic for CNTFETs to show high electrical performance was described by Radosavljevic et al (2004). By exposing potassium (K) vapour and high vacuum device annealing the contact metal was prepared. Current flow was improved due to low device resistance of K metal with the tube and voltage reduction of the Schottky barrier height at the K metal-channel contact. To achieve higher electrical performance for semiconducting CNTFETs, Ali Javey et al (2004) proposed the device with ohmic metal tube contact, high-κ dielectric material for gate-channel insulation and doped source/drain regions. H f O 2 is chosen instead of S i O 2 for the gate insulator. It is found that with the components, the device provides high ON- and low OFF- currents. The parasitic capacitances, screening or imaging of neighbouring channels and low channel density affects the performance of 1-D devices. By optimizing, the advantages of such devices were quantified. Lan Wei et al (2008) followed analytical and numerical simulation models to show the current improvement of 1-D devices. Classification based on the number of enclosed graphene layers, CNTs are categorized into single and multi-walled CNTs. For single-walled CNT substantial work has been done for studying and realizing the devices. But, complex structured multi-walled CNTs need more research work. The resistance was low in multi-walled carbon nanotube (MWCNT) claimed Mizuhisa Nihei et al (2005). It was lowered by optimizing the interface between the inter walls of MWCNTs and by parallel conduction of the channels. It was proved that MWCNT provides low resistance and high tolerance of migration. The density of MWCNT bundles had to be increased

3 54 to reach the resistance of Cu wire. Hong Li et al (2008) explored the details of interconnect performance of MWCNT. The interconnects were calculated and compared with Cu, Single-Walled CNT (SWCNT)-based on local, intermediate and global interconnects. MWCNT experiences lesser signal delay over Cu. With significant improvement through scaling technology and increasing wire lengths, MWCNTs manage smaller signal delay. Moreover, fabrication of MWCNT is easier with little stress about the chirality and density control that was used as horizontal wires in VLSI. To outperform MWCNT, SWCNTs need to be high and densely packed bundles. SPICE model had been reported by Jie Deng et al (2007b) for an array of CNTFET including non-idealities for the channel region and full device. Using HSPICE the work proposed a circuit-compatible model improving CV/I 13 times in the un-doped channel region with respect to bulk MOSFET. Same authors Jie Deng et al in their next paper (2007c), included elastic scattering, the resistance source / drain, Schottky-barrier resistance and parasitic capacitance along with the non-idealities for modelling CNTFET. HSPICE was used and performance comparison was done with standard digital library cells between CNTFET and bulk CMOS random logic. It was found that CNTFET was faster than CMOS circuits by two to ten times with one to ten CNTs per gate. The energy consumption and energy-delay product were lower. Applications and circuit features were also added by the authors. Modelling of gate channel, fringing and gate to gate capacitance for array of planar gate CNTFET was done by Jie Deng et al (2007a). The screening and imaging effects of neighbouring cylinders were included in the analytical model and verified with simulated numerical model. It was concluded by the authors that increasing the channel density and decreasing gate height will increase device speed. Double-walled CNT is the simplest form of multi-walled CNTs and it was discussed and reported that it exhibits

4 55 enhanced electrical characteristics like high current and power handling capability. Jun Zh. Huang et al proposed (2011) a planar model of Double- Walled Carbon Nano tube field effect transistor (DWCNTFET) and proved that the current flow had been enhanced. The device was numerically modelled and partially verified using Non-equilibrium Green s function approach. The comparison of the electrical performance of proposed Double- Walled CNTFET with Single-Walled Carbon Nano tube field effect transistor (SWCNTFET) was also done. It was found that DWCNTFET has larger ON current, shorter delay and higher cut-off frequency than SWCNTFET. To drive larger current and larger capacitive loads, array of Carbon Nano tubes were needed (Xinlin Wang et al 2003). The three different configurations of the gate electrode a) bottom gate, b) top gate and c) wrap around gate CNTFET were studied and compared. It was concluded that the third category, wrap around gate configuration had the largest gate capacitance. The current drive capability of the CNTFET was improved by an array of channels between the electrodes in the transistor, reported Xinlin Wang et al (2003). In their work, three gate configurations were simulated and compared to prove that the largest gate capacitance was provided by gate wrap around transistor. Array of surrounding gate CNTFET for single wall device was capacitance modelled by Md Rakibul Karim Akanda et al (2013). The proposed finite element method model included the screening effects and imaging effects of neighbouring channels due to multiple channels. Three key capacitances gate channel capacitance, fringing capacitance and gate to gate capacitances are analytically modelled and verified with FEM model. The device had enhanced gate capacitance over the planar gate. The performance of SWCNT and DWCNT bundle interconnects were compared with Cu wire to study the cross talks effects using numerical characterization. Crosstalk induced time delay was reduced in DWCNTs

5 56 compared to SWCNTs. So, DWCNT is found suitable in the next generation technology due to its reduced time delay (Shao-Ning Pu et al 2009). Md Rakibul Karim Akanda et al (2013), proposed a capacitance model for Wrap around CNTFET with multi-cnts. This paper discussed the gate wrap around the device with single-walled channel. Jun Zh Huang et al (2011) proposed the Modelling and Performance Characterization of Double-Walled Carbon Nanotube Array Field-Effect Transistors. This research work details modelling of planar gate with double-walled channel CNTFET. Using the equations of the gate wrap around CNTFET from Md Rakibul Karim Akanda et.al (2013) and double-walled array from Jun Zh Huang et al (2011) relations for the new device are developed. The proposed GWA with double-walled channel array CNTFET is the combination of these two works. 3.2 STRUCTURE OF THE DEVICE Figure 3.1 Internal 3-D Views of DWAGWA CNTFET An analytical model of GWADWA is proposed, studied and compared with its deepened competence over GWASWA. The screening or imaging effects of neighbouring channels and adjacent walls are included.

6 57 In section 3.2, the structure of the device is explained with its geometric descriptions. The equivalent circuit is developed in section 3.3, the distribution of capacitance in section 3.4 and a set of equations is derived for calculating capacitance of each distributed component are detailed in section 3.5. Current equations are discussed in section 3.6. Results and discussions of DWGWA are presented in section 3.7. Conclusions are drawn and discussed in Section 3.8. (a) (b) Figure 3.2 (a) and (b) Cross-sectional views of Gate Wrap Around Double-Walled Carbon Nanotube Array FET The structure of GWADWA is shown in Figure 3.1. The device cross section is shown in the Figure 3.2 (a) and (b). The device is 80nm length and 48nm width. The device is grown on Si base of 5nm, the bulk dielectric

7 58 of 10 µm, Gate height (H gate ) of 12nm and connecting electrode of 2nm thickness. Drain and Source regions are heavily doped and connected to both the inner and outer walls of GWADWA CNTs whereas, the channel region is un-doped. The gate length (L g ), source/drain (L sd ) are 16nm and 32 nm respectively. The chiralities of outer and inner walls are (26,0), (17,0) with diameter of d O (outer wall) 2nm and d I (inner wall) 1.34nm.The inter space distance between the co-axial channel is 0.34nm.The pitch distance (s) and oxide thickness (T ox ) are taken as 20nm and 4nm. The gate controls the current flow in the channel region through high-κ dielectric material H f O 2 of value 16.The bulk dielectric κ 2 has the value of EQUIVALENT CIRCUIT High-κ material is taken for the insulator since, CNTFET provides high gate control with high-κ insulator material in 1-D channel. Equivalent circuit in Figure 3.3 drawn for DWAGWA is developed and the circuit is shown in circular cross section. The current contributions of both the walls are marked as I O for the outer wall and I I inner wall. Semiconductorsemiconductor combination is assumed since switching off FET for metalsemiconductor and metal-metal combination is not effective. The details of the various capacitances per unit length are: a. C gc,o is the electrostatic capacitance between the gate and the outer wall of the channel b. C gc,i is the electrostatic capacitance between the gate and the inner wall of the channel c. C oi is the electrostatic capacitance between outer and the inner wall of the channel due to coupling

8 59 d. C gs,c gd (C gtg ) is the fringing capacitance between gate and source/drain or gate-to-gate capacitance. e. C frg,g is the fringing capacitance between the gate and outer wall of the channel f. C frg,sub is the fringing capacitance between substrate and outer wall of the channel g. C sub,o is the electrostatic capacitance between substrate and the outer wall of the channel h. C sub,i is the electrostatic capacitance between substrate and the inner wall of the channel i. C gsub is the electrostatic capacitance between gate and substrate. j. C qs,o is the quantum capacitance between source and the outer wall of the channel k. C qs,i is the quantum capacitance between source and the inner wall of the channel l. C qd,o is the quantum capacitance between drain and the outer wall of the channel m. C qd,i is the quantum capacitance between drain and the inner wall of the channel

9 60 Figure 3.3 Equivalent circuit of capacitive model for DWAGWA CNTFET 3.4 CAPACITANCE DISTRIBUTION For simplicity, three channels are taken. Gate oxide is taken with high-κ dielectric material κ 1 dielectric value of substrate is κ 2. The distance between the centre of the adjacent channels (the pitch distance) is denoted as s. The diameter of the outer wall is d O and that of inner wall is d I.The outer and inner diameters of the channels are 2 and 1.34nm respectively. The device structure is supported on Si base. Figure 3.4 and 3.5 illustrates the distribution of gate to channel capacitances and fringe capacitances

10 61 respectively. Figure 3.5 includes both the inner and outer walls. h is the distance between the centre of the cylinder and the metal gate. The inner and outer wall radii are denoted as r I and r O respectively. Figure 3.4 Distribution of Gate to Channel Capacitances Figure 3.6. shows the real charge Q and its image charges Q 1 and Q 2 and Figure 3.7 depicts the charge profile of the channel. Let A and B are adjacent channels, Q 1 and Q 2 are the image line charges of Q, while Q O and Q I denote charge of outer wall, inner wall of the channel respectively. The neighbouring channels affect each other and the individual walls disturb each other to cause a parasitic capacitance called fringing capacitance due to screening and imaging effects. This parasitic capacitance reduces the total output capacitance which has to be considered carefully while designing nano devices.

11 62 Figure 3.5 Distribution of Fringe capacitances and Gate-to-gate Capacitance Figure 3.6 The real charge Q and its image charges Q 1 and Q 2

12 63 Figure 3.7 Charge profile of a cylinder 3.5 CAPACITANCE MODELLING Capacitance modelling is preferred to study the dynamic response of the device. Three main capacitances viz., gate to channel, fringe and gate to gate capacitances are modelled along with the calculation of substrate, coupling and quantum capacitances. Drive current of 1-D device greatly depends upon the gate to channel capacitance in ballistic or quasi ballistic regime. The fringe capacitance is the major parasitic capacitance due to interferences and it plays an important role in designing device geometry. The other capacitances though smaller in values, the impact is non-negligible for nano devices. The following section discuss such factors for the proposed device Gate to Channel Capacitance (C gc ) The Gate to channel capacitance plays an important role in defining the drive current of the device. Figure 3.8 shows the classifications of gate to channel capacitance. The screening effects of neighbouring parallel cylinders and imaging effects of individual walls are taken into consideration for modelling Cgc. Figure 3.5 indicates the real charge Q and its image

13 64 charges Q1 and Q2 Figure 3.6 depicts charge profile of a cylinder. Two real and image line charges, one due to mirroring effect of metal gate and the other image line charge λ 1 Q due to κ 1 κ 2 are taken. The potential difference caused by the individual cylinders and the voltage drop due to screening effects of neighbouring cylinders are taken. The affects due to inter walls are also included. Figure 3.8 Classifications of Gate to channel capacitance Gate to channel capacitance (C gc ) of DWCNT is categorized into two parts, i.e. Capacitance between Gate and outer wall of the channel (C gc,o ) and Gate and the inner wall of the channel (C gc,i ).

14 65 C gc,o is calculated as (3.1) where, - Gate channel capacitance of the outer wall and the screening effects of other DWCNT. wall. - Gate channel capacitance due to screening effects of the inner is further divided into and. The first case is for the channels at end of the array and the second is for the middle ones. effected by the neighbouring channel at one side alone whereas is is effected by channels at both the sides. They are calculated as (3.2) where, C gc,inf - is the gate channel (outer wall) capacitance without any screening effects. C gc,sr - the equivalent capacitance including the screening effects of the other channels in the array. C gc,inf is calculated for cylindrical GWA CNTFET as,

15 66 (3.3) where, λ 1 - is the pre-factor that accounts for the interface of dielectrics κ 1 and κ 2 with different values. (3.4) C gc,sr is estimated by taking a. The potential drop between gate and outer wall and b. The potential drop due to the screening effects of the double walls of the neighbouring DWCNT. (3.5) where, (3.6) (3.7) (3.8)

16 67 The capacitance between gate and the inner wall of the channel (C gc,i ) comprises the effects of inhomogeneous gate dielectric and the imaging effects of other neighbouring GWADWA CNT. The imaging effects of the outer wall. (3.9) (3.10) (3.11) where, d O and are d I diameters of the cylinder a is Lattice Constant( 2.49A ) Fringe Capacitance (C frg ) The device speed is a mandatory calculation because it is a dependent factor on parasitic capacitances. The fringing capacitance between gate and the outer wall of the channel (C frg,g ) and fringing capacitance between gate and source/ drain or gate to gate capacitance C gs,c gd (C gtg ) and capacitance between gate and substrate (C gsub ) are parasitic capacitances. There are no fringing effects due to inner wall on gate and substrate, as it is isolated well from gate and the substrate by outer wall of CNT.

17 68 Figure 3.9 Classifications of Fringing capacitance The capacitance between gate and source (C gs ), the capacitance between gate and drain (C gd ),the capacitance between gate and the channel(c frg,g ), capacitance between the substrate and channel (C frg,sub ) are classified as parasitic capacitance. Being a strong function of device geometry, importance of fringing capacitance lies in evaluating the device speed accurately. C of is assumed to be independent of H gate and divided into two categories. One at the ends C of,e and the other at the middle C of,m the same way as the method followed to do C gc. Figure 3.9 shows the classifications of Fringing Capacitance. For a wraparound gate FET, (3.12)

18 69 where, (3.13) (3.14) τ 1, τ 2 are fitting parameters describing the rate of decrement in electric flux of the neighbouring cylinders with increase in distance between them. τ 1, τ 2 are taken as 2.5 and 2.0 respectively The Gate to Gate (Or Gate to S/D) Coupling Capacitance (C gtg ) C gtg is one of the parasitic capacitance and it is separated into gate to gate fringe capacitance per unit length C gtg,fr and gate-to-gate plate capacitance per unit length C gtg,nr due to normal electric field between the two channels. C gtg is the summation of both Gate-to-gate fringe capacitance per unit length C gtg,fr and Gate-to-gate plate capacitance per unit length C gtg,nr. (3.15) α gtg is the factor due to screening effect of neighbouring conductors(gate/source/drain) (α gtg = 0.7 for H adj =H gate )

19 70 where, (3.16) The driven capacitance is calculated using the following relation, (3.17) where, f miller =1.5. (3.18) Substrate Capacitance Figure 3.10 Classifications of Substrate capacitance

20 71 The substrate capacitance is an electrostatic capacitance between substrate and the channel. Classifications of Substrate Capacitance are shown in Figure It is divided into capacitance due to screening effects of outer walls of adjacent channels and screening effects of the inner wall. (3.19) where, is the substrate capacitance of the outer wall due to the outer wall of neighbouring channels. the channel. is the substrate capacitance of the outer wall due to inner the wall of (3.20) (3.21) Similarly, is categorized and calculated by the following expressions (3.22) (3.23) (3.24)

21 72 where, the channel is the substrate capacitance of the inner wall due to outer the wall of is the substrate capacitance of the inner wall due to the inner wall of neighbouring channels Coupling Capacitance The electrostatic capacitance between the outer and inner wall of the channel due to coupling (C oi ) is the same as that of. (3.25) Quantum Capacitance Figure 3.11 Classifications of Quantum capacitance

22 73 Figure 3.11 depicts the Classifications of Quantum Capacitance. For large gate bias (Em,0>>ΔΦ B ), the surface potential is limited by quantum capacitance, whereas for small gate bias(em,0 << ΔΦ B ), channel acts as a linear voltage divider with less reliance on quantum capacitance. With larger gate bias, the equations (3.26) and (3.27) relate quantum capacitance with surface potential. The factor of 4 indicates spin and double degeneracies of the sub-band. (3.26) (3.27) where (3.28) 3.6 CURRENT MODELLING The currents through the outer and inner wall are calculated with the following equation.

23 74 (3.29) The inter wall tunnelling current is ignored. Here, m, l are the number of sub-bands and substates. T LR is the transmission probability of the carriers at the substate (m,l) in +k branch due to scattering effect of acoustic phonon and optical phonon at the channel region. Similarly, T RL is in k branch. It is assumed that the transmission probability to be unity for ballistic transport. V ds and V gs are the corresponding voltages across drain-source and gate-source at the channel end. The wave numbers and is along the circumferential and axial directions. is the surface potential of channel, the the superscript i stands for outer and inner wall. The relation for k l is calculated as in equation (3.30). Double degeneracy is reflected by the factor of 2 in the equation., (3.30) where l = 0,1,2 and i= O,I To calculate the outer wall surface potential (3.35) are solved iteratively., equations (3.31) through Similarly, for inner wall surface potential (3.40) are solved., equations (3.36) through (3.31)

24 75 (3.32) (3.33) (3.34) (3.35) (3.36) (3.37) (3.38) (3.39) (3.40) where, k - Boltzmann constant T - Kelvin temperature.

25 76 C c,o - Coupling capacitance of the outer wall due to the surface potential. C c,i - Coupling capacitance of the inner wall due to the surface potential. - Charge induced on the electrodes (outer wall) per unit length - Charge induced on the electrodes (inner wall) per unit length - Charge induced on the outer wall. - Charge induced on the inner wall. The surface potential responds to the drain voltage that is explained by the fitting parameter βc c (β=0.8, C c =C gc /15). It is due to lowering of the surface-potential by 1) electrostatic coupling between CNT and drain the electrode through fringing field and 2) drain induced barrier lowering (DIBL) which remains as the base for non-uniform surfacepotential profile. V FB is the flat band voltage and is assumed to be zero, V sub is the potential difference between source and substrate. The driven relations capacitance and drive current are calculated with following (3.41) Driven capacitance (3.42) where,

26 77 (3.43) (3.44) C g - Total gate capacitance - Total fringe capacitance - Gate capacitance of the inner wall of the end channels - Gate capacitance of the outer wall of the end channels - Gate capacitance of the inner wall of the middle channels - Gate capacitance of the outer wall of the middle channels N - Number of channels 3.7 RESULTS AND DISCUSSIONS The difference in capacitance calculation of double-walled CNTFET from that of single-walled lies in the capacitance due to inter wall interferences. The key capacitances a) Gate to channel capacitance, b) Fringe capacitance and c) Gate-to-gate capacitances are studied under various parametric values. The role of gate dielectric value (κ1), the perpendicular distance of the channel and the gate (h), source /drain length (L sd ), number of channels (N) and the pitch distance between the adjacent channels (s) are the primary variables taken into account. Similarly, the responses of fringe capacitance are checked for қ 1, s and h. Gate Wrap Around Single-

27 78 Walled Array CNTFET is analysed with the chiralities of (26, 0). Likewise, Gate Wrap Around Double-Walled array CNTFET is analysed with the chiralities of (26, 0) and (17, 0) for the outer and the inner walls of the channel respectively. The diameter of the single-walled channel is the same as that of the outer wall of double wall channelled device. For simplicity, GWADWA CNTFET and GWASWA CNTFET are called as GWADWA and GWASWA respectively. The other parametric values used for GWADWA calculations are same as that of GWASWA tabulated in Table 2.1. The gate to the channel capacitance is calculated for the end and middle element of the array of channels. Correspondingly, the fringe capacitances are also calculated for the end and middle channels of the array. The comparisons of GWADWA and GWASWA are plotted for studying the behaviour of the individual devices as well as to project the wellness of multi-wall channelled device. In addition, the surface potentials are calculated for individual walls by solving equations from (3.31) through (3.40). The corresponding currents are calculated by solving equation (3.41). Drive currents for both double and single-walled with and without screening effects are calculated, plotted and compared. Response of drain current is studied with respect to drain voltage, the gate voltage, number of channels and tube diameters. Drive capacitance ratio is plotted for various values of the gate dielectric and gate length. As gate wrap around device structure provides good channel control, double wall enhances the current flow, array of channels handles larger capacitance loads and drive larger current, GWADWA shows improved response compared to GWASWA under the same working conditions.

28 Capacitance (nf) GWADWA Cgce GWADWA Cgcm GWADWA Cgcinf GWADWA Cgc Gate oxide dielectric Figure 3.12 Variations of capacitance of GWADWA for different gate oxide dielectric values From the graph of Figure 3.12, the behaviour of the gate to channel capacitances for different dielectric values with and without screening effects of GWADWA are studied. The gate oxide dielectric is varied from 1 to 30. The curves responds linearly, and it is found that the value of C gc,m varies between 0.094nF to 2.179nF while C gce values lies between 0.436nF to 1.712nF. The capacitance without any screening effects C gcinf has the value between nf and 1.246nF. The gate to channel capacitance provides 0.236nF to 5.604nF. The curves provide a constant increment in values with increase in dielectric value of the gate oxide. This becomes a proof for merit of using high κ material for switching devices. It is noted that the values of capacitances for channels at the end has more values than that at the middle ones. It is evident that this behaviour is the result of the interference due to adjacent channels. Also, the values of

29 C (GWADWA) / C (GWASWA) 80 capacitances without screening effects are smaller amongst all the curves. So, it is inferred that the contribution of gate channel capacitance of adjacent channels are noticeable above the parasitic effects. The advantage of array of channel is being proved. 2 Cgc,e Cgc,m Cgc,inf Cgc Gate oxide dielectric Figure 3.13 Capacitance ratio variations for various values of gate oxide dielectric of GWADWA & GWASWA The graph in Figure 3.13 shows the capacitance ratio between GWADWA and GWASWA for different κ 1 values. The gate to channel capacitances of middle (C gc,m ), end (C gce ) channels of the array, the capacitances without any screening effects (C gc,inf ) for GWADWA and GWASWA with respect to gate dielectric values are compared. From all these linear curves, it is observed that the slope of GWADWA is greater than GWASWA. From the capacitance ratio graph, it is noticeable that (C gc,e ) values of GWADWA are about 1.67 times greater, than that of GWASWA. The end and the middle gate capacitances ((C gc,e ), (C gce,m )) shows 1.7, 1.63 times greater value for GWADWA compared with GWASWA, but in the case of the capacitance excluding the screening effects it is 1.83 times greater

30 Capacitance (nf) 81 for GWADWA than its counterpart. With the screening and the imaging effects on neighbouring walls and channels of the array, the gate to channel capacitances (C gc ) for GWACNT shows that GWADWA gives higher values than its counterpart. In essence, it is proved that GWADWA has more capacitance values than that of GWASWA and the ratio maintains the same value with the increase in gate oxide dielectric. 4 3 DW Cgcm DW Cgce DW Cgcinf DW Cgc Normal distance of gate from the channel distance (nm) Figure 3.14 Variation of Capacitance with respect to the normal distance of gate from the channel (h) distance Variations of the gate distance from the channel are one of the important parameters depending upon which the device capacitance value varies. In the Figure 3.14, the behaviour of different components of the gate to channel capacitance for various h distances is plotted. The curve shows a negative exponential pattern with increase in x- axis value. It is found that the C gc,m varies from 1.182nF to 0.396nF, C gc,e does from nF to nF, while C gc,inf does from nF to nF and C gc ranges from 3.041nF

31 C( DWGWA)/ (C SWGWA) 82 to 1.239nF for h=5nm to 15nm. All the component curves approximates same value at h=14nm (C gc,m = 0.468nF, C gc,e = nF and C gc,inf = 0.465nF). This is reflected in the comparative graph also Cgc,inf Cgc,m Cgc,e Cgc Normal distance of gate from the channel (h) distance (nm) Figure 3.15 The variation of capacitance ratio with respect to h distance. The Figure 3.15 depicts the ratio of various gate capacitance components with respect to the distance of the gate from the channel. From the capacitance ratio graph, the changes of (C gc,e ), (C gc,m ), (C gc,inf ) and (C gc ) are observed for GWACNTs. The value of capacitances is more than 1.6 times for the lesser h reaches about 1.9 times for 14 nm distance. While designing such 1-D devices, care should be taken to check for trade-offs if any, before selecting h distance, particularly when the curves meet at h=14nm. After that point, C gc,m increases and C gc,inf maintains the same value.

32 Capacitance (nf) DW Cgce DW Cgcm DW Cgcinf DW Cgc Pitch distance (nm) Figure 3.16 Variation of Capacitance with respect to the pitch distance The distance between adjacent channels disturbs the capacitance with its screening and imaging effects. For this reason, it becomes necessary to read the corresponding changes. Figure 3.16 depicts the variation of gate to channel capacitance with respect to the pitch distance. The value of C gc ranges from nF to 3.159nF, C gc,e does from nF to nF and C gc,m varies from 0.908nF to 1.241nF. C gc,inf has same value through the values of pitch distance taken. The positive exponentially graph reaches saturation and remains constant after s = 15nm. With this results, it is inferred that the influence of pitch distance on the capacitance can be easily handled because of its little rate of change. In case of capacitance without any screening effects (C gc,inf ), the constant value allows to fix the pitch distance comfortably.

33 C (GWADWA) / C (GWASWA) 84 2 Cgce Cgcm Cgc Cgcinf Pitch distance (nm) Figure 3.17 Variation of capacitance ratio with respect to pitch distance to pitch distance. Figure 3.17 depicts the variation of capacitance ratio with respect The curves in the Figure 3.17 compares the gate to channel capacitances of middle (C gc,m ), end (C gc,e ) channels of the array, the capacitances without any screening effects (C gc,inf ) and the capacitances with all screening effects (C gc ) for various values of pitch distances. The ratio of C gc ranges from 1.91 to 1.66 while that of C gc,inf remains constant. C gc varies from 1.89 to1.68 and that of C gc,m does from 1.91 to The curves shows a negative exponential pattern except C gc,inf. That is, the capacitance values of GWADWA are appreciable though it reduces with respect to increasing s distances.

34 Capacitance (nf) 85 Thus, even if the reduction of capacitance ratio between Double and Single-walled channel finds little difference as s distance grows up, the capacitance value for GWADWA is found to be more DW Cgce DW Cgcm DW Cgcinf DW Cgc Source/drain length (nm) Figure 3.18 Variation of Capacitance with respect to the source/drain length Furthermore, gate to channel capacitance of end and middle (C gc,e, C gc,m, ) channels, Gate to channel capacitance without any screening effects (C gc,inf ) and Gate-to-channel capacitance including all screening effects (C gc ) for various source/drain lengths of the device has been studied to learn its limitation (Figure 3.18). From the graph, it is found that the values of C gc,e and C gc,m varies from 0.72nF to 1.698nF and 0.095nF to 2.15nF respectively. C gc ranges from 0.239nF to nF and C gc,inf has the values from 0.049nF to 1.246nF. Thus, the curves varies linearly and infers that for more L sd values, the gate capacitances are more.

35 C(GWADWA) / C(GWASWA) Cgce Cgcm Cgcinf Cgc Source /drain length (nm) Figure 3.19 Variation of Capacitance ratio with respect to source/drain length for GWADWA and GWASWA From the responses as shown in the Figure 3.19, capacitances of GWADWA increase linearly at a rate greater than GWASWA. The rate of increment of the capacitances is greater for GWADWA than its counterpart. C gc, C gc,m, C gc,inf shows 1.68, 1.64 and 1.83 times greater value for GWADWA than GWASWA. Conversely, in case of C gc,e, the values of GWASWA dominate that of GWADWA. But, the intrinsic capacitance (C gc ) ratio of GWADWA becomes larger and about 1.6 to 1.8 times greater than that of GWASWA. Increasing L sd introduce the limitation for the device containing double-wall and it is observed that its performance is lesser than GWASWA.

36 Capacitance (nf) DWGWA Cgc Number of Channels Figure 3.20 Variation of Capacitance with respect to the channel density The number of channels plays an important role in determining the capacitance values of the device. Figure 3.20 shows the variation of gate capacitance with respect to the number of channels. The value of C gc varies from 5.41 nf to 71.61nF for N=3 to 61. From the graph, it is found that an increase in number of channels provides more gate capacitance.

37 C(GWADWA) / C(GWASWA) Cgc Number of Channels Figure 3.21 Variation of capacitance ratio for GWADWA and GWASWA with respect to number of channels The Figure 3.21 depicts the capacitance ratio of gate-to-channel capacitance(c gc ) of GWACNT with respect to the number of channels. The improvement of GWADWA (2.2fF) over GWASWA (1.4fF) is being proved in the graph. The curve decreases drastically between N=3 to N=13 after which the ratio is almost constant. Capacitance ratio reduces to 1.64 times from 1.68 as number of channels increases from 3 to 20 and maintains constant after N = 20, reaching the restriction for the number of channels. It is inferred that the number of channels should be lesser for more gate capacitance.

38 Fringe Capacitance (af) Cofe Cofm Cof Gate oxide dielectric Figure 3.22 Variation of Fringe Capacitance with resect to the gate oxide dielectric for GWADWA The fringe capacitance is a parasitic capacitance which is to be explored for designing device containing multi-wall as well as array of channels. It is evident from the Figure 3.22 that there is no variation in the values of fringe capacitances irrespective of the end, middle or the total. All the three capacitances got a single value and it is independent of the dielectric value of the gate oxide (κ1). The value of fringe capacitance of the middle channel is 4.21aF and that of end channel is 3.81aF through the values of κ 1

39 Fringe Capacitance (af) 90 taken. The total fringe is 11.9aF which is the summation of two times the fringe capacitances of the channel at the end of the array and single time that at middle for number of channels three Cofe (s) Cofm (s) Cof (s) Cofe (h) Cofm (h) Cof (h) Normal distance of gate from the channel and Pitch distance (nm) Figure 3.23 Variation of fringe capacitances of GWADWA with respect to normal distance of gate from the channel and Pitch distances Fringing capacitance is due to screening, imaging effects of neighbouring channels and the individual walls of the channels. The values are to be studied to attribute the device geometry. More the fringing effect, more will be the parasitic values, In turn, more will be the reduction of total output capacitance values. Figure 3.23 depicts the change of fringe capacitances (end, middle and cumulative) of GWADWA with respect to s and h distances. C of,e (s) varies between 1.547aF and 3.126aF while the variation of C of,e (h) is from 3.88aF to 2.866aF. C of,m for s shows its

40 Gate to gate capacitance (nf) 91 variation from 1.609aF to 3.462aF and that of (h) does from 4.356aF to 3.19aF. Both the curves varies exponentially but s varies positively while on the contrary h does negatively. That is, the fringing capacitance increases with s, and decreases with h distances. A trade-off has to be taken during the selection of the above two parameters. Since, both the curves meet at 15 nm that infers that this value can be considered to reduce the complexity during device design Hgate =12nm Hgate =32nm Hgate =64nm Source /drain length (nm) Figure 3.24 Variation of gate-to-gate capacitance with respect to source/drain length for GWADWA The summation of both gate to gate fringe capacitance per unit length C gtg,fr and gate to gate plate capacitance per unit length C gtg,nr

41 C (GWADWA) /C (GWASWA) 92 contributes the gate to gate capacitance. The variation is plotted for studying the difference in the behaviour of the parameter for GWADWA. Figure 3.24 shows that variation of gate-to-gate capacitance with respect to L sd GWADWA. for The variation of this fringe capacitance is checked for various H gate value. C gtg gives values from 0.672nF to 0.132nF for L sd 10nm to 70nm and for H gate 64nm. Correspondingly, C gtg varies from 0.363nF to 0.084nF and 0.17nF to 0.053nF for H gate =32nm and 12nm. The variation is negative exponential and reduces considerably for L sd above 20nm. It is also found that shorter the H gate, lesser the capacitance value. As this is one of the parasitic capacitance, these changes also effect the device performance, which has to be analysed while designing devices d=1.6 nm N=3 d=2.0 nm N=3 d=2.8 nm N=3 d=1.6 nm N=12 d=2.0 nm N=12 d=2.8 nm N=12 d=1.6 nm N=21 d=2.0 nm N=21 d=2.8 nm N= Gate Oxide Dielectric Figure 3.25 Variation of drive capacitance ratio with respect to gate oxide dielectric for various diameters and channel density

42 C (GWADWA)/ C (GWASWA) 93 The drive capacitance ratio is checked for verifying the role of gate dielectric value. Also, the behaviour of the capacitance ratio of various channel densities and tube diameters has to be added to know the electrostatic performance of the proposed device. Figure 3.25 is the graph between the drive capacitance ratio of GWADWA and GWASWA with respect to dielectric values for different diameters and channel densities d= 1.6 nm N=21 d= 1.6 nm N=12 d= 1.6 nm N=03 d= 2.0 nm N=21 d= 2.0 nm N=12 d= 2.0 nm N= Gate Length (nm) Figure 3.26 Variation of drive capacitance ratio with respect to gate length for various channel diameters and channel density The value of the drive capacitance increases when the channel density increases and the increment is greater in case of a double-walled gate wrap around transistor than that of a single-walled gate wrap around transistor. It gives 1.55, 1.6 and 1.7 increment before maintaining a constant ratio of d=1.6, 2.0 and 2.8 respectively for κ 1 16, N 12. For lesser N and κ 1 30 the increment approximates the same value. To summarize, high-κ dielectric value increases the capacitance ratio till κ So, increasing κ 1

43 Drain Current ( µa) 94 greater than 16 has very little or no significant enhancement in the capacitance value of GWADWA over GWASWA. Gate or channel length is the transient distance for the current to travel from the source side to the drain side. Although the transport is ballistic, the study of electrostatic variation with gate length for various tube diameters and channel density becomes specific. Figure 3.26 shows the drive capacitance ratio with respect to the gate length for different values of diameters and channel densities N=9 Vgs=1V Vgs=0.8V Vgs=0.6V Vgs=0.1V N= Drain Source Voltage ( V) Figure 3.27 Variation of drain current with respect to drain source voltage for N=3, 9 of DWAGWA The constant variation shows that the behaviour of capacitance curve for both single and double-walled device is similar, but the values of GWADWA is greater than GWASWA. The improvement graph shows a

44 95 constant behaviour and the ratio reduces with reducing density of channels. The values of DWSWA are around 1.5, 1.55, 1.6 times for diameters 1.6 nm, 2.8 nm and 2.0 nm respectively. The reason that d=2.8nm lies in between the other two is its outer wall chirality is same as that of d=1.6 nm (35,0). This complexity shuffles the graph. Otherwise, the ratio will increase with larger diameter. The output drain current is plotted against output drain voltage for various gate voltage. Figure 3.27 shows increasing drain current with increasing drain voltage and gate voltage. The drive current starts at V ds = 0.1V itself and reaches maximum. After that it maintains almost constant variation. Drive current for DWGWA ranges around 36µA for 1V V gs to 20 µa for 0.1V V gs. Increasing the number of channels per gate, increases the drain current profile. More the number of channels (Channel density) has two effects. i) Each individual channels contribute for increasing the drive capacitance and drive current. ii) In contrast, it leads to more screening and imaging effects that in turn increases the parasitic capacitance. This will reduce the drive capacitance and degrades drive current. There needs a trade off in designing such devices with array of channels. In this case, besides the second effect, first effect enhances the drive current compensating the parasitic effect of channel density.

45 Drain Current ( µa) N=9 Vds=0.1V Vds=0.6V Vds=1.0V N=3 Gate Source Voltage (V) Figure 3.28 Variation of drain current with respect to gate source voltage for N=3 and 9 The relation between drain current and gate source voltage is plotted in Figure The drain current is checked for V ds =0.1V, 0.6V, 1.V and found that to be 35µA utmost for N=3 and nears 100µA with N=9. Increasing the number of channels, increases the current flow. It has almost the same value with various values of drain voltage. It is evident that the transverse current values of the proposed device GWADWA (35µA) approximate to planar DWCNTFET (40 µa). The graph shows a linear relation between drain current and gate voltage which is a proof of good channel control. Though the screening effect of inner wall reduces the outer wall current, the channel density supports for the total current.

46 Drain Current (µa) GWADWA I1 I3 I6 I10 GWASWA Number of Channels Figure 3.29 Variation of GWADWA and GWASWA drain current with respect to channel density The number of channels is one of the key parameter to be addressed, variation of which effects the flow of current. The response of drain current response of both double-walled and single-walled gate wrap around CNTFET for different channel densities is shown in figure I1 through I10 corresponds to V gs and V ds = 0.1V through 1.0V. It is apparent that the DWGWA makes more current flow compared with its counterpart. DWGWA gives 273.6µA current for V gs =1.0V and N=21 whereas it is117.3µa in the case of SWGWA for the same V gs and N. The improvement of drive current is owing to more drive capacitance in DWGWA. The channel

47 (Id GWADWA) / (Id GWASWA) 98 density also supports for increase in drive current flow. So, more the number of channels and more the V gs value, larger is the current flow in the channels Vgs =0.1V Vgs =0.3V Vgs =0.6V Vgs =1.0V Number of Channels Figure 3.30 Variation of the drive current ratio for various channel density and gate voltage Comparison of drive current of GWADWA with that of GWASWA is studied to project the improved difference. It is done by varying the channel densities to show the performance significance of the device. The current ratio between GWADWA and GWASWA for number of channels is illustrated in Figure This ratio is derived for studying the improvement of GWADWA over GWASWA. It is seen that with an increase in number of channels, the current ratio shows almost constant difference. The curve shows lesser value for more V gs. That is, the ratio is almost constant since the curves in Figure 3.30 are linear, and the ratio decreases with an increase in

48 99 V gs. More the gate voltage, lesser the ratio value but almost constant for number of channels. In spite of the imaging and screening effects, the device shows enhanced performance. The ratio is not due to two paths, but both contribute individually to have more throughput. It may vary for three and more walled CNTs. Figure 3.31 Change of current ratio with respect to drain voltage for d=2.4nm,d=2.8nm The drive current ratio for various diameters (chiralities) of the channel is an important study, as it gives an idea about selecting the channel specifications for device design. Figure 3.31 shows the variation of drive current ratio and drain voltage for diameters d=1.6nm, 2.0nm,2.4nm,2.8nm (chiralities= [(35,0),(19,0)], [(26,0),(17,0)], [(31,0),(16,0)], [(35,0),(22,0)]). The ratio is almost constant and in order to see the variations closely the graphs are plotted separately and made as insets. The inset depicts the variation of diameters 2.4nm and 2.8nm. The drive current of GWADWA

49 100 maintains 1.7 and 2.26 times the drive current value of GWASWA. For d = 2.4 nm, the variation decreases at the starting point but with a linear increment till V ds =0.6V after which again there is a fall. In the next case, d=2.8nm the variation starts above 1.7 and oscillates around the same point and falls after V gs =0.6V. This variation is very small but for nano scale device these variations also have to be considered. Figure 3.32 Change of current ratio with respect to drain source voltage for d=1.6nm, d=2.0nm Figure 3.32 shows the variation of drive current ratio and drain voltage for diameters d=1.6nm, 2.0nm, 2.4nm, 2.8nm similar to Figure This graph shows the variation in diameters 1.6 nm and 2.0 nm as insets. The graph for d=1.6nm resembles the curve for d=2.8 nm. It is because of the similar chiralities of the outer wall of both the channels (35,0). But in overall appearance, it is concluded that the variations are 1.7 and For V gs > 0.6V, all the curves show a roll off even the variation is negligibly small. As

50 101 the device design is in nano scale, the above variation has to be followed closely. Otherwise, the curves are very similar and coincidental. 3.8 SUMMARY The simulation study reveals that GWADWA provides larger driven capacitance to drive large current. It is found that increasing the gate oxide dielectric, number of channels and source drain length increases the gate channel capacitance and drives current of the device. It is evident that the capacitance is decreasing with increase in h distance. The response for pitch distance is constant for s >15 for GWADWA. The capacitance ratio decreases for s >15 which means that the interferences due to more pitch distance decreases the gate channel capacitance of GWADWA. Regarding the fringe capacitances, the response is constant for different values of κ 1. While, it is found to be positive exponential for s and negative exponential for h distances. This means that fringe capacitance is not disturbed by variation of κ 1 value, it increases with the pitch distance and decreases with that of h. So, denser the channels produces more parasitic capacitance and shorter the device results in more fringe capacitance. The drain current increases with increase in drain voltage and number of channels for both devices. But, it is more in GWADWA compared to GWASWA. From the comparison study of both devices, it is found that the device containing double-wall excels in its performance over its single-walled counterpart. It is evident from the results that with the advantages of multiwalled channels, Gate Wrap Around Double-Walled Array Field Effect Transistor outperforms Gate Wrap Around Single-Walled Array Field Effect Transistor.