Reliability issues of current and emerging NVMs

Transcription

1 Reliability issues of current and emerging NVMs A. S. Spinelli, C. Monzio Compagnoni and D. Ielmini Dip. di Elettronica e Informazione Politecnico di Milano, Milano, Italy and IU.NET alessandro.spinelli@polimi.it

2 Purpose Discuss the operation and some reliability issues of NVMs, with emphasis on Floating-gate Phase-change Charge-trap Highlight the main problems and their current understanding, without going into many details 2

3 Acknowledgments A. L. Lacaita, C. Miccoli, A. Maconi, S. Amoroso, Politecnico di Milano A. Visconti, R. Bez and P. Tessariol, Micron, Agrate Brianza All authors whose works contributed to this tutorial 3

4 Outline Floating-gate technology Phase-change technology Charge-trap technology For each technology, the cell operation and reliability are discussed Only single-cell mechanisms no disturbs, interference, parameter spread, 4

5 Outline - FG Flash memory cell concept and operation Flash reliability Endurance Retention (Detrapping and SILC) Random telegraph noise Charge injection statistics 5

6 Flash memory cell concept C pp V CG MOS device with a floating gate (FG) C S C B V FG C D FG is electrically isolated by means of V S V B V D Tunnel oxide (bottom) Interpoly dielectric (top) A charge Q into the FG gives ΔV T = -Q/C pp Stored charge does not leak from the FG NVM 6

7 I D [µa] Program/erase operation (concept) 2,5 2 1,5 ΔV T 1 0, V CG [V] Electron charge is moved to/from the FG Verify levels PV and EV control the final V T 7

8 I D [µa] Read operation (concept) 2,5 2 1, ,5 0 R V CG A reference voltage R is applied and the cell current is sensed 8

9 V T distributions NAND Bit distribution NOR 1 N 0 DV EV R PV Voltage 9

10 Multi-level cells Bit Distribution NAND 11 N EV R1 PV1 R2 PV2 R3 PV3 OP PASS Voltage Bit distribution NOR 11 N DV EV R1 PV1 PV2 R2 PV3 R3 Voltage 10

11 Outline - FG Flash memory cell concept and cell operation Flash reliability Endurance Retention (Detrapping and SILC) Random telegraph noise Charge injection statistics 11

12 Flash reliability A charge flow through the oxide is required for cell operation Very high oxide field is routinely applied during Flash P/E operations Flash devices work almost constantly under stress Oxide reliability is the key to a successful Flash technology 12

13 Endurance From Lee et al., IRPS (2009) NOR cell From Lee et al., IRPS (2003) NAND cell The V T levels move with cycling Asymmetric behavior of programmed and erased levels 13

14 1 Oxide charge and FN tunneling FN tunneling generates traps in the oxide, mainly filled by electrons Electrons reduce the electric field and the tunneling current Less charge is transferred into the FG (even if CHE is used) From Mielke, IRPS tutorial (2007) 14

15 Effect V T From Shirota, IRPS tutorial (2005) - modified A narrowing of the V T window is expected 15

16 2 Oxide charge and V T V T From Shirota, IRPS tutorial (2005) - modified Trapped oxide charge shifts V T (ΔV T = Q/C) Asymmetric effect results 16

17 3 Interface states From Lee et al., IRPS (2003) cycles cycles Interface states are generated after FN stress Device gm and SS are degraded V T is further increased 17

18 Results FN field reduction Oxide charge Interface states V T V T V T All can be seen, depending on the leading mechanism 18

19 Scaling effect From Fayrushin et al., IEDM (2009) Non-uniform charge trapping at STI edges leads to different behavior for scaled cells 19

20 Retention Retention = ability to maintain the stored information over time Intrinsic retention is limited by tunneling through the oxide (plus thermionic emission over the 3.1 ev barrier) FG Sub 20

21 Retention time [s] Intrinsic retention V TP =V T0 +2V V Tfail =V T0 +1V 10years 120days 9.5hours 97years 30Kyears t ox [nm] From Ielmini et al., ME (2005) An oxide thickness around 4.5 nm is enough for the intrinsic case 21

22 Retention after cycling Detrapping SILC Main V T shift due to detrapping A small % of tail cells appear, losing charge much faster than the average 22

23 Detrapping Program/erase Retention 23

24 Detrapping in capacitors From Scott et al., TED (1996) From Spinelli et al., EDL (1999) A transient SILC is measured on capacitors after stress A t -1 dependence is usually shown V T ~ ln(t) 24

25 Detrapping features Dependence on cycling: Increases with cycle number Dependent on cycling pattern see Mielke et al., IRPS (2006) High activation energy (1.1 ev) for retention (Ghidini et al, IRPS (2002)) and cycling (Mielke et al., IRPS (2006)) Low field acceleration 25

26 Cycling pattern dependence damage creation Fast (test) damage recovery Distributed (real) damage creation damage recovery t t Charge detrapping and/or trap annihilation take place between cycles Fast cycling is a worst-case condition 26

27 Relations Assuming that Damage creation is not dependent on cycling pattern and temperature Then Distributed cycling (t c, T c ) is equivalent to fast cycling + bake time (t b, T b ): t b V T t 0 At ln c 1 exp t t b E A 1 k T B b UDM 1 k T B c 27

28 Comparison From Monzio Compagnoni et al., IRPS (2010) t b t 0 At c exp E A 1 k T B b 1 k T B c 28

29 Universal damage metric From Mielke et al., IRPS (2006) From Monzio Compagnoni et al., IRPS (2010) NOR NAND V T ln 1 t t b UDM 29

30 SILC in capacitors Steady-state current following detrapping (or transient SILC) Modeled via trap-assisted tunneling (TAT) of carriers through oxide traps (Ielmini et al., TED (2000)) 30

31 I FG (A) Current [A] SILC in tail cells 1 From Cappelletti et al., IEDM (2004) From Spinelli, IRPS tutorial (2005) Moving (SILC) Fast erasing V FG (V) Typical (FN) Tail cell Average SILC/cell FG Voltage [V] Tail cells show a much larger leakage current than average (at the same stress level) 31

32 SILC in tail cells 2 From Ielmini et al., ME (2001) A tunneling process assisted by two traps (2TAT) is held responsible for SILC in tail cells Successful models have been developed for SILC statistics (Ielmini et al., TED (2002) and Schuler et al., IRPS (2002)) 32

33 Array distribution Adapted from Ielmini et al., TED (2002) TAT 2TAT TAT E FS E 1 E 2 E FP Tail cells are those with an unlucky trap distribution, enhancing the leakage 33

34 SILC features Tail cells increase with cycle number Erratic behavior: Cells can suddendly stop/start leaking (trap annihilation/reactivation) Tail cells may be different from cycle to cycle Low activation energy ( ev) Trap annealing above 85 C Strong field acceleration 34

35 V T (V) I FG (A) Over-erase in NOR cells From Cappelletti et al., IEDM (2004) Fast erasing Time (s) Moving (SILC) Typical Moving (SILC) Fast erasing V FG (V) Typical Some cells show enhanced tunneling at high fields their V T is lower than typical ones during erase Read errors may arise if V T becomes < 0 35

36 Origin of fast-erasing cells From Chimenton et al., PIEEE (2003) Positive charges trapped in the oxide Three-charge cluster was assumed (Ong et al., VLSI (1993)) Generated by anode-hole injection (Chimenton et al., IRPS (2004)) FG morphology Barrier lowering/field enhancement (Muramatsu et al., IEDM (1994)) Field enhancement at polysi grain asperities (Nkansah et al., SSE (2000)) 36

37 Over-program in NAND cells Fast-program cells are expected in NAND arrays (opposite polarity with respect to NOR) Cells are programmed via ISPP it is the V T fluctuation within a single step that matters If V T is programmed above V pass, the cell will always remain OFF and the entire string can no longer be accessed (temporary failure) 37

38 Outline - FG Flash memory cell concept and cell operation Flash reliability Endurance Retention (Detrapping and SILC) Random telegraph noise Charge injection statistics 38

39 Random telegraph noise (RTN) G τ c S Sub D G SiO 2 τ e Sub Capture/emission of single electrons by oxide traps, with time constants τ c and τ e Fluctuations in the drain current (or threshold voltage) 39

40 RTN in FG NVMs ΔV T is the important parameter Due to the gate coupling coefficient α G, the RTN V T shift becomes (neglecting mobility fluctuations) q VT C WL For W = L = 45 nm, t ox = 7 nm, α G = 0.65 we have ΔV T 25 mv ox G 40

41 Anomalous RTN in FG NVMs From Kurata et al., VLSI (2006) From Fantini et al., EDL (2007) ΔI D / I D 15% (90 nm technology) ΔI D / I D 50% (65 nm technology) 41

42 Dynamic characterization of RTN ΔV T = 0 ΔV T > 0 ΔV T < 0 t 1 t 2 42

43 Results From Monzio Compagnoni et al., TED (2008) 43

44 Interpretation From Muller et al., JAP (1996) Large conductance modulation is interpreted via a trap closing a percolation path Nonuniform conduction determined by fixed charge (and interface traps) distribution 44

45 Random dopant fluctuation and RTN Atomistic doping induces percolation paths Additional contribution to RTN amplitude From Asenov et al., TED (2003) 45

46 Numerical simulation From Ghetti et al., IRPS (2008) Exponential distribution confirmed for the singletrap RTN Multi-trap model in Monzio Compagnoni et al., TED (2008) 46

47 The drift phenomenon From Monzio Compagnoni et al., TED (2008) From Kurata et al., JSSC (2007) From Fukuda et al., IEDM (2007) 47

48 Origin of drift From Spinelli et al., JJAP (2008) Slower and slower traps are observed as time elapses (RTN leading to 1/f noise) Increasingly large V T can be reached 48

49 Cycling dependence From Kurata et al., JSSC (2007) From Fukuda et al., IEDM (2007) 49

50 Effects on tail height and slope From Monzio Compagnoni et al., EDL (2008) 60 nm NAND 65 nm NOR 50

51 RTN scaling trends From Ghetti et al., TED (2009) Scaling rule for the slope K G tox W N L a 51

52 Impact of STI edges From Wang et al., TED (2009) From Ghetti et al., IEDM (2008) Traps near STI edges have large impact on RTN Sharper STI edges degrade RTN 52

53 Electron injection statistics (EIS) During programming, an average numbernnof electrons is injected into the FG at each step JA n t step q Fluctuations in n (shot noise of the gate current) generate fluctuations in V T J 53

54 ΔV T distribution From Monzio Compagnoni et al., TED (2010) Gaussian distribution of Independent of cycling and temperature (Monzio Compagnoni et al., TED (2008)) V T 54

55 Experimental data From Monzio Compagnoni et al., TED (2008) and TED (2010) σ ΔV T saturates at high ΔV T V V T T at low ΔV T 55

56 Low-ΔV T regime Since V T qn C pp, we have V T q C pp n For small n, injection events are rare, hence not correlated n is ruled by a Poisson statistics, having n V T q C pp n n q C pp V T 56

57 High-ΔV T regime Electron injection modifies the FG potential, reducing the oxide field The tunneling current is reduced a correlation arises between the injection events The final result is V T q C pp V FG (Monzio Compagnoni et al., TED (2008)) 57

58 Effect on program accuracy From Monzio Compagnoni et al., TED (2008) EIS controls the ultimate limit to the V T accuracy 58

59 Scaling trends From Monzio Compagnoni et al., TED (2008) C pp is the main parameter driving the increase in σ ΔV T 59

60 Outline Floating-gate technology Phase-change technology Charge-trap technology 60

61 Outline - PCM PCM cell concept and operation PCM reliability Cycling wearout Data retention Resistance drift 61

62 Bottom contact PCM cell concept Top contact c-gst Temperature a-gst T m Time 62

63 Bottom contact Bottom contact PCM logic states Top contact c-gst Reset state a-gst V T R=V/I Ge 2 Sb 2 Te 5 Set state 63

64 Set/reset in PCM devices I x I m Reset Set From Redaelli et al., EDL (2004) I < I x no change I x < I < I m crystallization I > I m melting + quenching 64

65 Outline - PCM PCM cell concept and operation PCM reliability Cycling wearout Data retention Resistance drift 65

66 Cycling endurance From Kim et al., IRPS (2005) Stuck set Stuck reset 66

67 Stuck-set mechanism From Rajendran et al., VLSI (2008) cycles Before After 67

68 Crystallization 68

69 Evidence for nucleation From Lee et al., NL (2008) 69

70 Evidence for growth From Shih et al., IEDM (2008) 70

71 Percolation dynamics T = 210 C r c = 5.6 nm T = 190 C r c = 3.3 nm T = 180 C r c = 2.2 nm From Redaelli et al., TED (2006) 71

72 G t X extrapolation From Russo et al., TED (2007) E X = x0e E x kt Reaction coordinate E x = 2.5 ev x0 = s 72

73 G R drift atomic relaxation From Ielmini et al., TED (2009) R = R 0 t t 0 0 E A = e kt E A Reaction coordinate 73

74 Energy Kinetic model for SR From Ielmini et al., IEDM (2007) Distributed E A : N T 0 E A E A = e kt Reaction coordinate E A Monomolecular dynamics: dn(e T A ) NT =- dt (E τ ) A 74

75 Why distributed E A? Single E A level N T R E A distribution N T E A Energy R time Energy time 75

76 Simulation results From Lavizzari et al., TED (2009) 76

77 Temperature dependence 77

78 Arrhenius plot R* From lelmini et al., APL (2009) 78

79 Intepretation: Meyer-Neldel rule Arrhenius law with distributed E A EA = exp kt SR 0 Crossing at T MN pre-exponential 0 is not constant, but is an exponential function of E A Meyer-Neldel (MN) rule (Yelon et al., PRB (1992)) = exp 0 00 E kt A MN N 79

80 Unified kinetic model E A = kt 0e From lelmini = e 0 00 E - kt A MN et al., APL (2009) SR and crystallization are described by the same Arrhenius + Meyer-Neldel rules 80

81 T-acceleration model From Ielmini et al., ME (2009) To normalize SR time to a given T: T2 T2 T 1 MN T1 T1 t1 00 t2 T MN T T

82 Outline Floating-gate technology Phase-change technology Charge-trap technology 82

83 Outline - CTM CTM cell concept and operation CTM reliability Endurance Retention (Detrapping and SILC) Random telegraph noise Charge injection statistics 83

84 CT memory cell concept V CG Still a charge-based approach same concept and operation as FG technology V S V B V D The polysilicon FG is replaced by a defective dielectric (usually silicon nitride) FN tunneling is used for P/E NAND technology 84

85 Erase saturation in SONOS cells Electron injection from CG limits the V T window 85

86 SONOS cell trade-off From De Salvo et al., TDMR (2004) Scaling of tunnel oxide leads to DT and holes injection, increasing ΔV T Retention is compromised 86

87 From SONOS to TANOS From Lee et al., IEDM (2003) 87

88 CTM reliability Same issues as FG memories (endurance, retention, RTN, ) Understanding complicated by nitride and blocking dielectric layers Contradictory results exist in the literature (dependence on technology, cell size, ) Only standard TANOS are discussed for brevity 88

89 Endurance capacitors From Van den Bosch, IMW (2009) In large-area capacitors, ΔV T is mainly controlled by interface states 89

90 Endurance cells From Lee et al., NVSMW (2006) In scaled cells, a behavior similar to FG ones is obtained same physical mechanisms are involved (i.e., edge effects) 90

91 Retention Intrinsic retention is still the issue Both oxide, nitride and alumina affect CT retention Thin oxide layer (4 5 nm) Trappy nitride layer ( ev from CB; actual values can vary) Trappy alumina layer 91

92 A few mechanisms 92

93 Lifetime [a.u.] Ea [ev] Activation energy 1 From Kim et al., DRC (2010) High activation energy (1 2 ev) Dependent on T range, but unusual (higher for low T) 93

94 Activation energy 2 From Bocquet et al., IMW (2009) Samples with 3.5/3, 5, 10/16 nm are investigated Low activation energy ( ev) 94

95 Role of nitride layer 2 hours at 150 C Different nitride thickness Different oxide thickness From Melde et al., NVSMW (2008) Thin nitride layer degrades retention faster leakage of charge at the nitride edge Small dependence on oxide layer thickness main leakage path is through alumina 95

96 Role of alumina layer From Amoroso et al., IRPS (2010) Main leakage path is through alumina 96

97 Tail cells From Lue et al., NVMTS (2009) Tail cells have been observed also in CTM Still interpreted as TAT through oxide traps 97

98 RTN From Gu et al., IEDM (2006) RTN is a reliability issue also in CTM 98

99 RTN and nitride charges From Chiu et al., IEDM (2009) Localized charge affect RTN amplitude, changing the percolation paths 99

100 RTN distribution (simulations) From Monzio Compagnoni et al., TED (2010) Random dopant fluctuations remains the main responsible for RTN in CTM 100

101 EIS From Lue et al., IMW (2010) A Poissonian behavior for charge injection is recovered in CTM 101

102 Conclusions 1 FG reliability is determined by different physical mechanisms, more and more connected in huge, scaled arrays Scaling brings on ever new phenomena, challenging our understanding of the basic issues and raising new ones Moreover 102

103 Conclusions 2 Emerging memories raise totally new issues, related to their unique operating characteristics A good comprehension of the reliability physics of NVMs is needed to understand the nature of the new failure mechanisms and learn how to live with them 103

104 References FG R. Shirota, IRPS tutorial (2005) W. H. Lee et al., Proc. IRPS, 907 (2009) J.-D. Lee et al., Proc. IRPS, 497 (2003) N. Mielke, IRPS tutorial (2007) A. Fayrushin et al., IEDM Tech. Dig., 823 (2009) D. Ielmini et al., Microel. Eng. 80, 321 (2005) R. S. Scott et al. IEEE Trans. Electron Devices 43, 130 (1996) A. S. Spinelli et al., IEEE Electron Dev. Lett. 20, 106 (1999) G. Ghidini et al., Proc. IRPS, 415 (2002) N. Mielke et al., Proc. IRPS, 29 (2006) C. Monzio Compagnoni et al., Proc. IRPS, 604 (2010) D. Ielmini et al., IEEE Trans. Electron Devices 47, 1258 (2000) D. Ielmini et al., IEEE Trans. Electron Devices 47, 1266 (2000) P. Cappelletti et al., IEDM Tech. Dig., 489 (2004) A. S. Spinelli et al., IRPS tutorial (2005) D. Ielmini et al., Microel. Eng. 59, 189 (2001) D. Ielmini et al., IEEE Trans. Electron Devices 49, 1955 (2002) F. Schuler et al., Proc. IRPS, 26 (2002) A. Chimenton et al., Proc. IEEE 91, 617 (2003) T. C. Ong et al., Symp. VLSI Tech. Dig., 83 (1993) A. Chimenton et al., Proc. IRPS, 216 (2004) S. Muramatsu et al., IEDM Tech. Dig., 847 (1994) F. Nkansah et al., Solid-State Electron. 44, 1887 (2000) H. Kurata et al., Symp. VLSI Circ. Dig., 140 (2006) P. Fantini et al., IEEE Electron Dev. Lett. 28, 1114 (2007) C. Monzio Compagnoni et al., IEEE Trans. Electron Devices 55, 388 (2008) H. H. Mueller et al., J. Appl. Phys. 79, 4178 (1996) A. Asenov et al., IEEE Trans. Electron Devices 50, 1837 (2003) A. Ghetti et al., Proc. IRPS, 610 (2008) H. Kurata et al., J. Solid-State Circ. 42, 1362 (2007) K. Fukuda et al., IEDM Tech. Dig., 169 (2007) A. S. Spinelli et al., Jap. J. Appl. Phys. 47, 2598 (2008) C. Monzio Compagnoni et al., IEEE Electron Dev. Lett. 29, 941 (2008) A. Ghetti et al., IEDM Tech. Dig., 835 (2008) R.-V. Wang et al., TED, 2107 (2009) A. Ghetti et al., TED, 1746 (2009) C. Monzio Compagnoni et al., IEEE Trans. Electron Devices 55, 2695 (2008) C. Monzio Compagnoni et al., IEEE Trans. Electron Devices 57, 1761 (2010) C. Monzio Compagnoni et al., IEEE Trans. Electron Devices 55, 3192 (2008) 104

105 References PCM and CTM A. Redaelli et al., IEEE Electron Dev. Lett. 25, (2004) K. Kim et al., Proc IRPS, 157 (2005) B. Rajendran et al., VLSI Tech. Dig., 96 (2008) S.-H. Lee et al., Nano Lett. 8, 3303 (2008) Y. H. Shih et al., IEDM Tech. Dig., 551 (2008) A. Redaelli et al., IEEE Trans. Electron Devices 53, 3040 (2006) U. Russo et al., IEEE Trans. Electron Devices 54, 2769 (2007) D. Ielmini et al., IEEE Trans. Electron Devices 56, 1070 (2009) D. Ielmini et al., IEDM Tech. Dig., 939 (2007) S. Lavizzari et al., IEEE Trans. Electron Devices 56, 1078 (2009) A. Yelon et al., Phys. Rev. B, 46, (1992) D. Ielmini et al., Appl. Phys. Lett. 94, (2009) D. Ielmini et al., Microelectron. Eng. 86, 1942 (2009) B. De Salvo et al., IEEE Trans. Dev. Mat. Reliab. 4, 377 (2004) C. H. Lee et al., IEDM Tech. Dig., 613 (2003) G. Van den Bosch, Proc. IMW (2009) C.-H. Lee et al., Proc. NVSMW, 54 (2006) J. Kim et al., Proc. DRC, 99 (2010) M. Bocquet at al., Proc. IMW, (2009) T. Melde et al., Proc. NVSMW, 130 (2008) S. Amoroso et al., Proc. IRPS, 966 (2010) H. T. Lue et al., Proc. NVMTS, 58 (2009) S. H. Gu et al., IEDM Tech. Dig., 487 (2006) J. P. Chiu et al., IEDM Tech. Dig., 843 (2009) C. Monzio Compagnoni et al., IEEE Trans. Electron Devices 57, 2124 (2010) H. T. Lue et al., Proc. IMW, 92 (2010) 105