Modeling of PMOS NBTI Effect Considering Temperature Variation

Transcription

1 Modeling of PMOS NBTI Effect Considering Temperature Variation Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang Circuits and Systems Division, Dept. of EE, Tsinghua Univ., Beijing, , P.R. China {luohong99, wangyuu99, {luorong, Yuan Xie CSE Department, Pennsylvania State University, University Park, PA, USA Abstract Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose a fast and accurate PMOS NBTI model, in which the temperature variation and the ratio of active to standby time are considered in both stress and relaxation phases. A PMOS V th degradation model and a digital circuits temporal performance degradation estimation method are developed based on our PMOS NBTI model. The simulation results show that: 1) our dynamic NBTI model without temperature variation is as accurate as previous models, the error is less than 2.3%; 2) the analysis error of PMOS V th degradation may reach up to 52.6% without considering temperature variation; 3) for ISCAS85 benchmark circuits, the error of worst case performance degradation analysis is about on average 52.0%; 4) the ratio of active to standby time has a considerable impact during the performance degradation analysis. 1 Introduction As semiconductor manufacturing migrates to more advanced technology nodes, negative bias temperature instability (NBTI) is becoming one of the major reliability concerns. NBTI significantly shifts the threshold voltage V th on the order of 20 50mV for devices operating at 1.2V or below [1]. Previous research showed that V th shifts due to NBTI is expressed as a power-law time dependence [2, 3], and this aging-induced parameter variation has a negative impact on circuit performance. After the aging time of 10 6 s arising from NBTI, the circuit performance degradation can reach up to 15% [4]. This work was supported by grants from 863 program of China (No. 2006AA01Z224), and NSFC (No , No ). Yuan Xie s work was supported in part by NSF , NSF CA- REER and MARCO/DRAPA-GSRC. The NBTI occurs when the PMOS transistor is negative biased, in particular at elevated temperature. This phenomenon can be classified as static NBTI and dynamic NBTI. Static NBTI (i.e. under constant voltage (DC) stress condition) leads to a severe V th shifts, while the mechanism was described in [5]. However, because of associated recovery phenomena the dynamic NBTI (i.e., under AC stress), a less severe parameters shifts over long time compared with that under DC stress condition were observed and described in [6 10]. Recently, NBTI models are developed to analysis the reliability and delay degradation problems in large-scale digital circuit [11 15]. Based on these circuit degradation models, NBTI-aware design techniques were investigated in [14, 15]. An analytical model for evaluating dynamic NBTI effect was proposed in [16], and the effect of various process and design parameters were described in [17]. In previous analytical NBTI models [16, 17], the circuit temperature was considered to be constant during the circuit operation. However, when the circuit switches between active and standby mode, the circuit temperature varies periodically between high temperature and low temperature. Therefore, we propose an analytical model for dynamic NBTI effect considering the temperature variation on account of the switch of circuit operation modes: active and standby mode. Our contribution in this paper distinguishes itself in the following aspects: We propose an analytical model to estimate PMOS NBTI effect under AC stress condition. Our model is faster than the model in [16], while remains the same accuracy. Furthermore, two factors, a) the temperature difference between circuit active and standby mode; b) the time ratio of circuit active and standby mode, are first considered in both stress and relaxation phases during our NBTI analysis. Based on our novel NBTI model, we propose a PMOS V th degradation model and study the impact of NBTI on the temporal performance degradation in combinational

2 circuits considering both the temperature variation and ratio of active to standby time. The rest of the paper is organized as follows. In Section 2, we first review previous NBTI models and present our improved analytical NBTI model. Then, in Section 3, we give out the V th degradation model, and the circuit delay estimation method. The simulation results of a single PMOS transistor and the ISCAS85 benchmark circuits are shown and analyzed in Section 4. Finally, Section 5 concludes the paper. 2 NBTI Model A shift in the threshold voltage ΔV th of the PMOS transistor is proportional to the interface trap generation due to NBTI, which can be expressed [15] as ΔV th =(1 + m) qn it(t) C ox (1) where m represents equivalent V th shifts due to mobility degradation, q is the electronic charge, C ox is the gate oxide capacitance, and N it (t) is the interface trap generation, which is the most important factor in evaluating performance degradation due to NBTI. 2.1 Previous NBTI Models The interface trap generation is often described by a reaction-diffusion (R-D) model [3], dn it = k f (N 0 N it ) N it C H (0,t) (2) dt dn it C H = D H dt x (3) x=0 C H t = D H 2 C H x 2 (4) where the mobile diffusing species are assumed to be neutral H atoms, and N 0 is the concentration of initial interface defects. The parameters k f and are constant dissociation rate and self-annealing rate, respectively. When the device is in recovery phase, k f becomes zero, and is unchanged. The parameter C H is the concentration of H atoms, and D H is the corresponding diffusion coefficient. In this model, the interface trap generation (ΔN it ) under DC stress condition is expressed as [3] kf N 0 N it (t)=1.16 (D H t) 1/4 = At 1/4. (5) Kumar et al. proposed an analytical NBTI model [16] to handle multi-cycle AC stress condition; and assuming the PMOS transistor is under AC stress with duty cycle of c and the period of τ, the interface trap generation after n + 1 cycles of AC stress can be evaluated by a recursion formula below, [ N it [(n + 1)τ]= βn ( ) ] it(nτ) 1 + β + N0 it Nit (nτ) 4 1/4 c β Nit 0 (6) and the initial condition is N it (τ)= c1/4 1 + β N0 it (7) where Nit 0 = Aτ1/4 1 c,andβ = Our improved dynamic NBTI Model without temperature variation Though the model proposed by Kumar [16] is accurate, the computing process may be slow because of the recursion process in Eq. (6). We use a different approach to derive the model under AC stress. If the period τ is small enough (i.e., at a frequency more than several KHz magnitude), the traps created at the stress and relaxation phases in one cycle can be expressed as ΔN it = k f (N 0 N it )(cτ) N it C H (0,t)(cτ) (8) ΔN it = N it C H (0,t)(1 c)τ (9) Thus, the above two equations can be averaged, giving [10] dn it = c k f (N 0 N it ) N it C H (0,t). (10) dt Contrasting with Eq. (2), the interface trap generation can be expressed as N it (t)=1.16c 0.5 kf N 0 (D H t) 1/4 (11) where c 0.5 describes the impact of AC stress on NBTI. In order to eliminate the error in Eq. (11), the exponent of c should be modified. We use a linear function to replace the exponent 0.5, and the function can be determined by fitting technology. Hence, the interface trap generation can be described as N it (t)=1.16 c c 0.23 kf N 0 (D H t) 1/4. (12) The comparison between Kumar s [16] and our model is shown in Figure 1. The multi-cycle NBTI model under AC stress condition proposed in this paper is as accurate as Kumar s model, the error is less than 2.3% ( cm 2 of our model, and cm 2 for Kumar s model in Figure 1). Since there is no recursion process in our model, our method is faster than Kumar s.

3 Interface traps ΔNit ( cm 2 ) DC stress (Kumar) AC, c=0.1 (Ours) AC, c=0.1 (Kumar) AC, c=0.4 (Ours) AC, c=0.4 (Kumar) AC, c=0.8 (Ours) AC, c= (Kumar) 3.70 (Ours) Operation time (s) Figure 1. Comparison between Kumar s and our model 2.3 NBTI analysis with temperature variation During circuit operations, the circuit switches between active and standby modes, so that the temperature changes relevantly. Previous NBTI models [16,17] only consider the situation that the temperature is a constant (which is around 400K). Actually the circuit temperature varies when the circuit switches between active and standby mode. Therefore the NBTI model should be modified to consider the temperature variation. Assuming the device operation temperature changes between T high and T low frequently, the interface trap generation due to NBTI is different from the case under a constant high operation temperature condition. First, we consider the impact of temperature variation in stress phases. The temperature variation has a significant impact on the diffusion coefficient of H atom (D H ) in Eq. (4). In this paper, a triangle diffusion profile [3] is used. The effect of H atom diffusion under T low lasting for a stress time of t low, equals to the effect under T high for a stress time of t high,if D high t high = D low t low (D high and D low denote diffusion coefficients under high and low temperature, respectively). Because the diffusion coefficient is proportional to exp( E a kt ), the ratio of D low to D high can be expressed as μ = D low D high = exp [ Ea kt high ( 1 T )] high T low (13) Therefore, the equivalent stress time can be expressed as t eq = t high + μt low (14) where the total stress time t can be divided into two parts: t high, the stress time at high temperature, and t low the stress time at low temperature. Figure 2 shows the numeric simulation result of this law. We take T high = 400K, T low = 340K as an example. The ratio μ is when E a is set to 0.48eV. Hence, the equivalent stress time t eq is Interface traps ΔNit ( cm 2 ) T low = 400K T low = 380K T low = 340K T high = 400K (1000, 2.34) (543, 1.70) (1000, 1.67) Stress time (s) Figure 2. Impact of temperature variation in stress phase Interface traps ΔNit ( cm 2 ) S:400K, R:400K S:400K, R:300K S:380K, R:380K S:380K, R:320K S:340K, R:340K S:340K, R:300K Operation time (s) Figure 3. Impact of temperature variation in relaxation phase 543s (Figure 2) when t high = t low = 500s. Figure 2 shows that the interface trap generation is cm 2, and the equivalent trap generatin at high temperature is cm 2, where the error is 1.8%. If the temperature is considered to be kept at high temperature constantly, the interface trap generation is cm 2, and the error is 40.1%. Second, a totally different phenomenon in relaxation phases is observed from numeric simulation. Under AC stress condition, if temperature variation only occurs in relaxation phases, the overall interface trap generation is not affected. This phenomenon is shown in Figure 3. Though the temperature variation indeed affects the trap generation in a single cycle, the overall trap generation remains the same as that at a constant temperature. 2.4 Our PMOS NBTI model during real circuit operations In previous section, we analyze the impact of temperature variation on the interface trap generation. In real circuits, the situation is much more complex. In this paper, we make an assumption that the circuit switches between

4 active and standby modes periodically, and the PMOS transistor in the circuit is under AC stress in active mode, while in standby mode, it is under constant DC stress or in relaxation. We denote the ratio of the active to standby time as R AS, the temperature of active mode is denoted as T act (corresponding to high temperature T high in previous section), and the temperature of standby mode as T stdby (corresponding to T low ). The interface trap generation is modeled as follows: a) If the PMOS transistor is in relaxation phase in standby mode, the interface trap generation is not affected by the temperature variation according to Section 2.3, which can be described as N it (t)=1.16 γ γ 0.23 kf N 0 (D act t) 1/4 γ = cr AS (15) R AS + 1 where D act is diffusion coefficient in active mode, and here c is duty cycle of stress in active mode. b) If the PMOS transistor is under DC stress in standby mode, the stress time in standby time should be transformed using Eq. (14). Therefore, the interface trap generation is described as N it (t)=1.16 γ γ 0.23 kf N 0 (D eff t) 1/4 where γ = cr ASD act + D stdby R AS D act + D stdby D eff = R ASD act + D stdby R AS + 1 μ = D stdby D act = cr AS + μ R AS + μ = R AS + μ R AS + 1 D act (16) [ ( Ea = exp 1 T )] act. (17) kt act T stdby 3 V th and circuit delay degradation model Previous section describes the analytical model of interface trap generation due to NBTI considering the temperature variation between active and standby mode in real circuits. In order to evaluate the temporal performance degradation due to NBTI, the threshold voltage degradation model and circuit delay model are described in the following subsections. 3.1 PMOS V th degradation model A predictive compact model for NBTI is developed in [17]. The dependence of NBTI on key process (such as L, V th,andt ox ) and design parameters (such as V dd ) are captured in this model. From Eq. (1), the model in [17], and our NBTI model Eq. (15)-(17) proposed in previous section, the degradation of threshold voltage is given by ΔV th = K V γ γ 0.23 λt 1/4 + δ V { cras R γ = AS +1, under relax in standby cr AS +μ R AS +μ, under stress in standby 1, under relax in standby λ = ( ) 1 RAS +μ 4 R AS +1, under stress in standby (18) where K V and δ V are the parameters extracted from [17], and μ is the ratio of D stdby to D act describing by Eq. (17). 3.2 Gate and circuit delay degradation analysis In this paper, the delay of a gate v can be approximately expressed as [15] d(v)= C LV dd K = I d (V gs V th ) α C L V dd K =. (19) μc ox W eff /L eff The shift in the transistor threshold voltage ΔV th can be derived using Eq. (18). Hence, the delay degradation Δd(v) for gate v can be derived as K Δd(v)= (V gs V th ΔV th ) α K (V gs V th ) α ( = (1 ΔV ) th ) α 1 d(v). V g V th (20) We use Taylor series expansion on the right side of Eq. (20), neglecting the higher order terms, giving that Δd(v)= αδv th V gs V th0 d(v) (21) where V th0 is the original transistor threshold voltage and d(v) is the original delay of gate v. 4 Simulation results In this section, we present the simulation results in order to validate the NBTI model. Firstly, a single PMOS transistor is used to evaluate the NBTI effect considering temperature variation. Secondly, ISCAS85 circuits are used as the benchmark. In this paper, the standard cell library is constructed using the PTM 90nm bulk CMOS model [18]. V dd = 1.0V, V th = 220mV are set for all the transistors in the circuits.

5 Vth degradation (mv) Var. temp. Const. temp. Temp. in standby = 340K R AS = 1: Operation time (s) Figure 4. NBTI effect under variable temperature vs. constant temperature Vth degradation (mv) R AS = 9:1 R AS = 3:1 R AS = 1:1 R AS = 1:3 R AS = 1:9 18 Time = s 16 Duty cycle in active = Temperature in standby (K) Figure 5. Impact of temperature in standby on V th degradation 4.1 Single PMOS device NBTI analysis The V th degradation of the PMOS transistor in the circuit is shown in Figure 4. The ratio of active to standby time is set to 1 : 9, and duty cycle in active mode is 0.5. We can see that after s (about 10 yr), the V th degradation is 17.3mV considering temperature variation. If the temperature is considered to be constant in the evaluation, the degradation can reach up to 26.4mV, and the error is 52.6%. The temperature in the standby mode and the ratio of active to standby time have considerable impact on the V th degradation, which is shown in Figure 5 and 6. Table 1 shows the threshold voltage degradation ΔV th with different ratios of active to standby time. From these figures and table, we can conclude that 1) a lower standby temperature leads to a smaller NBTI effect on the V th degradation; 2) if the ratio of active to standby time is smaller, which means a longer standby time during the circuit operation, the impact of the standby temperature variation on the V th degradation is larger. Vth degradation (mv) Duty cycle in active = 0.5 Time= s 18 T stdby = 400K T stdby = 380K 16 T stdby = 360K T stdby = 340K T stdby = 300K 14 9:1 3:1 1:1 1:3 1:9 Ratio of active to standby time R AS Figure 6. Impact of R AS on V th degradation Table 1. ΔV th under different R AS (mv) R AS 9:1 3:1 1:1 1:3 1:9 T stdby = 400K T stdby = 340K Performance degradation analysis in digital circuits Fig. 7 shows the performance degradation of ISCAS85 c432 benchmark with different ratios of active to standby time. The circuit delay degradation is much less than the V th degradation under a same standby mode temperature. And the standby mode temperature difference leads to considerable circuit delay difference. Table 2 shows the result of the circuit delay degradation analysis. In order to investigate the worst case circuit degradation (denoted as Max. Δdelay in Table 2), we set the internal inputs of all the PMOS transistors to logic 0 during the Vth and circuit delay degradation (%) :1 Duty cycle in active = 0.5 Time= s Δdelay, T stdby = 340K ΔV th, T stdby = 400K ΔV th, T stdby = 340K Δdelay, T stdby = 400K 3:1 1:1 1:3 Ratio of active to standby time R AS Figure 7. Impact of R AS on V th and circuit delay degradation 1:9

6 Table 2. Delay degradation of ISCAS95 benchmark circuits under NBTI ISCAS85 Nominal (400K) Max. Max. Min. Circuits delay (ns) Δdelay (%) Δdelay Δdelay c c c c c c c c c c Average N/A standby mode. The inputs are set to logic 1 to investigate the best case circuit degradation (denoted as Min. Δdelay in Table 2). The ratio of active to standby time is set to 1:9.TheMax.Δdelay is around 5.69% of the original circuit delay when T stdby = 340K, and Min. Δdelay is around 4.65%. If the temperature variation is not considered, the Max. Δdelay is around 8.65% (corresponding to the third column in Table 2), which leads to a error of 52.0%. 5 Conclusion In this paper, we propose an analytical model of temporal performance degradation due to PMOS NBTI effect under AC stress condition. The model is as accurate as previous models, while the speed is faster. We demonstrate that the temperature variation due to the change of circuit operation mode (active and standby mode) can have significant impact on PMOS NBTI effect: if the temperature variation is not considered, for single PMOS transistor analysis, 52.6% error can be reached, while for ISCAS85 circuits analysis, the error can be up to 52.0%. Therefore, we propose an analytical model that considers the temperature variation, such that a more accurate performance degradation estimation can be performed. We also study the impact of the ratio of active to standby time on PMOS and circuit performance degradation due to NBTI. References [1] L. Peters, NBTI: A Growing Threat to Device Reliability, Semiconductor International, vol. 27, no. 3, Mar [2] V.Huard,M.Denais,andC.Parthasarathy, NBTI degradation: From physical mechanisms to modelling, Microelectron. Reliab., vol. 46, no. 1, pp. 1 23, [3] J. Stathis and S. Zafar, The negative bias temperature instability in MOS devices: A review, Microelectron. Reliab., vol. 46, no. 2-4, pp , [4] K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, High-performance CMOS variability in the 65-nm regime and beyond, IBMJ.Res.&Dev., vol. 50, no. 4/5, pp , [5] S. Ogawa and N. Shiono, Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si- SiO 2 interface, Physical Review B, vol. 51, no. 7, pp , [6] S. Mahapatra, P. Bharath Kumar, T. Dalei, D. Sana, and M. Alam, Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen, in IEDM Tech. Dig., 2004, pp [7] M. Alam and S. Mahapatra, A comprehensive model of PMOS NBTI degradation, Microelectron. Reliab., vol. 45, no. 1, pp , [8] R. Wittmann, H. Puchner, L. Hinh, H. Ceric, A. Gehring, and S. Selberherr, Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-mosfet, in Proc. Intl. Integrated Reliab. Workshop Final Report, 2005, pp [9] S. Mahapatra, D. Saha, D. Varghese, and P. Kumar, On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress, IEEE Trans. Electron Device, vol. 53, no. 7, pp , [10] S. Zhu, A. Nakajima, T. Ohashi, and H. Miyake, Mechanism of dynamic bias temperature instability in p- and nmosfets: The effect of pulse waveform, IEEE Trans. Electron Device, vol. 53, no. 8, pp , [11] V. Reddy, A. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, Impact of negative bias temperature instability on digital circuit reliability, in Proc. IEEE IRPS, 2002, pp [12] V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, Impact of negative bias temperature instability on digital circuit reliability, Microelectron. Reliab., vol. 45, no. 1, pp , [13] B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, Impact of NBTI on the temporal performance degradation of digital circuits, IEEE Electron Device Lett., vol. 26, no. 8, pp , [14] S. Kumar, C. Kim, and S. Sapatnekar, Impact of NBTI on SRAM Read Stability and Design for Reliability, in Proc. ISQED, 2006, pp [15] B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits, in Proc. DATE, vol. 1, 2006, pp [16] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, An Analytical Model for Negative Bias Temperature Instability, in Proc. IEEE/ACM ICCAD, [17] R. Vattikonda, W. Wang, and Y. Cao, Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design, in Proc. DAC, 2006, pp [18] Nanoscale Integration and Modeling (NIMO) Group, ASU, Predictive Technology Model (PTM). [Online]. Available: ptm/