Impact of RDF and RTS on the performance of SRAM cells

Transcription

1 J Comput Electron (2010) 9: DOI /s Impact of RDF and RTS on the performance of SRAM cells Vinícius V.A. Camargo Nabil Ashraf Lucas Brusamarello Dragica Vasileska Gilson Wirth Published online: 2 November 2010 Springer Science+Business Media LLC 2010 Abstract This paper investigates electrical effects due to reliability phenomena associated with the downscaling of transistors in advanced technologies, particularly Random Telegraph Signal (RTS) and Random Dopant Fluctuations (RDF). RDF and RTS are becoming important issues in sub- 60 nm technologies, mainly in memories, where transistor sizes are smaller. This paper presents a comprehensive evaluation of the impact of the joint effect of RTS and RDF on 6T-SRAM cells. Based on 3-D atomistic simulation of the device structure, doping profile, and trap location, the random threshold voltage variation caused by the joint effect of RDF and RTS is evaluated. The derived threshold voltage variation is then used to statistically evaluate the performance variation at the circuit level. Finally, the impact of assuming a normal distribution for the threshold voltage variation caused by RDF and RTS is studied. The results obtained running Monte Carlo simulations raffling the value of the variation of the threshold voltage from a database obtained by 3-D atomistic simulation are compared to the results obtained running Monte Carlo simulations considering the variation of the threshold voltage as a Normal distribution. The results show that for a 6T-SRAM designed with 45 nm technology the read noise margin distributions are very similar between the two cases, making the Normal distribution a good approximation for the V th variations. Nevertheless, the performance variation induced at the circuit level does not necessarily follow a normal distribution. V.V.A. Camargo ( ) L. Brusamarello G. Wirth Universidade Federal do Rio Grande do Sul UFRGS, Porto Alegre, Brazil vvacamargo@inf.ufrgs.br N. Ashraf D. Vasileska Arizona State University ASU, Tempe, USA Keywords Random telegraph signal RTS Random dopant fluctuation RDF SRAM Reliability Variability 1 Introduction Random Telegraph Signal (RTS) is a statistical effect caused by traps at the Si/SiO 2 interface on MOS transistors operation. This effect, despite being detectable in older technologies, becomes more noticeable in sub-60 nm technologies. This happens due to the miniaturization of the transistors sizes which causes the electrical variations due to RTS to be up to 10% of the nominal electrical parameters, e.g. threshold voltage (V th ). This issue is aggravated in SRAM and flash memories because, in order to increase their integration density, these circuits are produced at the limit of the technology using sizing as small as possible [1]. RTS noise originates from the alternate capture and emission of charge carriers by traps (defects) at the Si/SiO 2 interface, causing discrete drain current fluctuations. This component is a random signal that oscillates between discrete levels with a random period, naming the effect. The traps can become filled with charge carriers which should be in the channel contributing to current conduction. Once the carrier is trapped it causes a change in channel current. On the other hand, Random Dopant Fluctuations (RDF) are the variations in the crystalline Si structure due to the variations in the number of dopant atoms in the channel, as well as its irregular distribution. This effect nowadays represents one of the greatest challenges for the industry. Recent works study different sources of variability, including Line Edge Roughness (LER) and polygate granularity (PGG) [2, 3], and concluded that random discrete dopants are still the dominant intrinsic source of statistical variability.

2 J Comput Electron (2010) 9: Fig. 1 Histogram of the Threshold Voltage variation The impact of RDF and RTS on SRAM memories can be divided in two parts, during the read process where the memory can change its state and during reading or writing where the memory can violate the time constraints. The main issue on memories can be considered the flip on the memory value during a read process. The analysis of this failure is made using the read noise margin (RNM). This paper will present the analysis of RNM of a SRAM cell and compare two models: (1) the reference (evaluations through 3D atomistic simulations) model and (2) the Normal approximation counterpart of method 1. Both methods consist on running Monte Carlo simulations raffling the variation of the threshold voltage for each transistor due to RTS and RDF. In the first method the variations are raffled from a database of variations on the threshold voltage that were generated by device simulations [4]. In the second method the Monte Carlo simulation is performed defining V th as a Normal distribution with the mean and the standard deviation calculated from the same database used in the first method. This comparison aims to evaluate the possibility of considering V th variations due to RDF and RTS as a Normal distribution. Although the variation on the threshold voltage is clearly not a normal distribution as we can see on Fig. 1, the advantages of considering it to be Normal during circuit level analysis and simulation are enormous, since most electronic design automation tools provide support to work with Normal distributions in a computationally efficient way. Detailed experimental work on RTS based instability in scaled flash memory arrays that discusses the evidence of exponential tail in the statistical spread in V th is given in [5]. In our simulation experiments the data statistics for EMC device simulation is based on 20 different fully random dopant distributions in the channel and bulk region of the MOSFET. From our extracted V th values from different Fig. 2 Threshold voltage distribution for the cases of 20 different fully randomized channel and bulk dopant distributions random dopants, the distribution do seem to show decreasing tail for higher V th separations (see following Fig. 2). This manuscript is organized as follows. First it presents RDF and RTS fluctuation which motivates the need for compact models to incorporate these effects and, thus, propagate their impact to circuit level modeling. Then it presents SRAM memory cell, the main metrics to evaluate SRAM cells and detailed description on Read Noise Margin of the SRAM cell. Then presents the results of the SRAM simulations and finally summarizes the main conclusions of this work. 2 Atomistic 3D simulations evaluating RDF and RTS RTS is caused by the capture and release of electrons by traps at the interface and bulk of the gate dielectrics. These captures and emissions cause oscillations in the transistor current. The induced current fluctuations may strongly vary between different devices on a same chip, and moreover even between different operation points of a single transistor. Atomistic three dimensional (3D) simulations were performed to study the impact of both RDF and RTS on the electrical performance of the device. Ensemble Monte Carlo (EMC) device simulations were conducted considering statistical fluctuations of the channel dopant number and position, known as RDF. In addition to RDF, the impact of interface traps lying close to the Si/SiO 2 interface was also simulated. In this context, EMC based device simulation is applied to evaluate the threshold voltage fluctuation due to both RDF and trap induced RTS noise. In contrast to 3D particle-based device simulations that accurately capture the electrostatics and the transport ef-

3 124 J Comput Electron (2010) 9: fects, 3D Drift-Diffusion (DD) simulations capture accurately only the electrostatic effects associated with random discrete dopant distributions (thus providing less accurate estimate for the variations in the threshold voltage and the drive current). DD simulations cannot capture the complex effects associated with the variation in carrier transport that significantly modulates the scattering cross section of a carrier in the vicinity of a trap altering the carrier s mobility [6]. Therefore the estimates for the variation in the drive current obtained from DD simulation will under estimate the real variation even in low to moderate gate voltage variations used to extract threshold voltage of the device. Using our EMC device simulator we have evaluated the total variation of the threshold voltage as a function of a double trap (that can capture two charge carriers simultaneously) position when the double trap is moved from the source end to the drain end of the channel (L direction). Along the channel width (W) direction, the double trap is positioned at the middle of the channel width. Because of the proximity of the traps and the fact of them being at the interface right in the vicinity of the channel the fluctuation cause by these double traps is increased and this will generate overly pessimistic results on the working of the cell. Details of these 3D atomistic simulations are presented in [4, 7, 8]. Here we briefly underscore our EMC device simulation scheme. A conventional EMC device simulator that utilizes non-parabolic band structure and was developed at ASU is supplemented by a novel molecular dynamics routine. In this approach, the mutual Coulomb interaction among electrons and impurities is treated in the drift part of the MC transport kernel. Indeed, the various aspects associated with the Coulomb interaction, such as dynamical screening and multiple scatterings, are automatically taken into account. Since a part of the Coulomb interaction is already taken into account by the solution of the Poisson equation, the MD treatment of the Coulomb interaction is restricted only to the limited area near the charged particles. It is claimed that the full incorporation of the Coulomb interaction is indispensable to reproduce the correct electron mobility in highly doped silicon samples [8]. Variations in drain current can then be modeled as momentary changes in threshold voltage. It is already well established that the variation in drain current due to RTS can be modeled as momentary changes in gate bias [9], induced by electron trapping and emission. This approach is adequate to model RTS as a dynamic source of variation. In circuit analysis, this source of variation may be included as one more parameter that can cause circuit performance variability, in addition to the other sources, as for instance the static, non time dependent, variations caused by RDF and also the variations caused by Negative Bias Temperature Instability (NBTI). A comprehensive model for RTS in time domain is presented in [10], deriving the relevant statistical Fig. 3 Percentage threshold voltage variation due to two traps located at the semiconductor/oxide interface and different positions along the middle section of the channel. 20 devices with different random dopant distributions have been averaged out. x = 0 denotes source end of the channel parameters. The model is suitable for analysis of digital circuits. The physical explanations regarding fluctuations of threshold voltage as determined by EMC simulation in presence of RDF and traps positioned from source end towards the drain end in close proximity to one another is discussed first. From the simulation results shown in Fig. 3 we see that the threshold voltage fluctuation increases from its average value when this trap is located at the source end of the channel. This is due to the fact that carriers see additional large potential barrier due to the presence of the charged double trap and are reflected back in the source contact. The threshold voltage fluctuation rapidly reduces when the double trap is moved away from the source injection barrier because when the electrons are injected in the channel, even though the electric field is small (due to small drain bias applied when measuring threshold voltage), they slowly drift towards the drain contact. Figure 4 schematically explains this effect. 3 Static Random Access Memory (SRAM) Yield analysis of SRAM memories using Monte Carlo and error propagation at electrical level for yield analysis considering variations on the V th has been studied in [11, 12] and [13]. Process variation induces shifts in different parameters, such as V th, critical dimensions W and L, Tox, mobility and other electrical parameters of the transistor. For modeling purposes, these components can be reduced to a compact model where only V th represents the variations in IV curves due to all sources. This approach is widely employed because of its simplicity and concordance with measured data [14]. In these works failures in SRAM cell are

4 J Comput Electron (2010) 9: Fig. 4 Schematic explanations of the results presented in Fig. 3. (Traps near the source end of the channel have the largest influence since they are major obstacles to the electrons because of the large input barrier depicted in case (a). Traps near the drain end of the channel have smaller influence since electrons are accelerated by the small electric field case (b) Fig. 5 6-transistors SRAM cell statistically modeled (access time failure, read failure, write failure and hold failure), and yield of SRAM memory is given as function of SRAM cell yield. The schematic of a typical 6-T SRAM cell is shown in Fig. 5. Statistical behavior of circuit response may be caused, for instance, by lithography and random dopant fluctuations. In this work it was considered the statistical variation on V th to be due to random dopant fluctuation and the traps (defects) at the Si/SiO 2 interface. The failure probability in a SRAM memory array is given as function of the number of columns, number of rows, number of redundant columns, and the probability of a SRAM cell to work properly in the presence of variability. Failures in SRAM cells can be due to: Access time violation when reading the value stored in a cell, bit line and negated bit line are set to V DD, and when the word line (wl) is set to V DD, one of them discharges (through M1 M3 or M5 M6). The access time (T AC ) is defined as the time required to discharge a secure margin of the bitline. As the maximum access time (T MAX ) is a design input related Fig. 6 Butterfly curves during read operation to chip frequency, violation occurs when T AC of the cell is greater than T MAX. The access time is a non-linear function of V th, but its inverse can be considered linear [15]. Read failure when reading the content of a cell, bit line or negated bit line discharges (through M1 M3 or M5 M6). This causes input of one of the inverters (M2 M3 or M5 M6) to be charged to voltage V READ. If maximum V READ is greater than V READ trip point V TRIP of the inverter, read operation will cause the stored bit to erroneously flip. Read failure can be modeled as a linear function of V th [15]. Write failure to write a value to the cell, bit line and negated bit line are set to the proper values, and then wl is set to V DD for a time T WL in order to the signals to be stored in the cell. Consider that signal takes T WRITE to be written to the cell, then it must apply T WRITE >T WL,otherwise the signal will not be successfully stored. Although write stability is not linear with V th, its inverse is so [15]. Hold voltage failure in order to diminish SRAM power consumption, voltage V DD is set to a value during sleep mode of the chip. But V HOLD must be secure enough to maintain the value stored in the cell, otherwise it will happen the value to be erroneously flipped or inconsistent during sleep mode. In this work we will only take into account the read failure. The method used to simulate the read failure is the Read Noise Margin (RNM). The read noise margin of the SRAM cell is the minimum noise (DC voltage) which flips the content of the cell during the reading process. One way of computing the Read Noise Margin (RNM) is from the analysis of the butterfly curve of the SRAM cell. Figure 6 presents the butterfly curve of the SRAM cell used in the simulations. In order to simulate the Read Noise Margin, the SRAM cell was divided in two parts, the left and the right side. The left side contains the transistors M1, M2 and M3 while the right side contains the transistors M4, M5 and M6. The

5 126 J Comput Electron (2010) 9: transfer functions for each side of the circuit are called f and g, respectively. According to [11] it is computed by: LoopGain(V L ) = f R gr (1) V L V R VR f R (V L ) The RNM is defined as the V L that causes the loop gain to be equal to 1, as defined by the following equation: RNM L = VL(flip) Rd grd( f Rd( VL(flip) Rd )) (2) The result of (2) is the Read Noise Margin of the left side of the cell. The RNM of the right side, RNM R, is computed similarly. The cell Read Noise Margin is then given by the weaker side of the cell as in RNM = min(rnm R, RNM L ). RNM either indicates that the cell has a stable reading process when its value is greater than zero or indicates a faulty cell otherwise. Such convenient and accurate approach for modeling Read Noise Margin was formulated by [11]. In order to simulate the RNM a DC simulation is run for each side of the SRAM cell obtaining the transfer function of f and g. A post-processing is performed by helper scripts, which automatically compute RNM from a Monte Carlo sample of DC simulations. 4 Results and discussion After the evaluation of the statistical parameters of the threshold voltage fluctuations at the device level, electrical (Spice) level simulations are conducted, aiming to evaluate the impact of both RDF and RTS at the circuit level, in this case a SRAM cell. All electrical simulations were performed using HSpice from Synopsys as the simulation tool. The model used for the transistors is the PTM of 45 nm [16 18], the temperature is 25 C and the V dd equal to 1 V. The database containing the variation on the threshold voltage was obtained using atomistic simulations mentioned before. Both Monte Carlo simulations consist of sample size of All the transistors have the minimum gate length which is equal to 45 nm. The sizing of the cells used in these simulation was made from a linear scaling from the 6T-SRAM presented in [19]. The values of the width obtained with this linear scale are 65 nm for M1, M2, M4 and M5 and 90 nm for M3 and M6. This leads to a β ratio of The nominal value of the Read Noise Margin of the SRAM cell is V. The fact that the SRAM cell used in this work may not be as optimized as the ones designed for commercial usage may have made his performance and reliability lower than the ones commercially available. However, it is good enough for the sake of comparing the techniques, since they should be independent of the cell scale. Fig. 7 Kernel density function obtained using both methods Figure 7 presents the simulated results obtained by running Monte Carlo simulations using the measured data and the Normal approximation, respectively called method 1 and method 2. Sample size used for both approaches is The percentage of failing cells obtained by the simulations is 31.73% when using the first method and 28.73% when using the second. The percentage of failing cell is very similar and in a first order, the PDFs obtained using both methods are similar. This confirms our hypothesis that, although RTS has a significant contribution to V th fluctuation, the combined effect of RTS and RDF can be assumed to follow a Normal Distribution for the purpose of propagating these device-level variations to circuit level. Since Gaussian distributions can be handled easier by standard EDA tools than arbitrary distributions, the circuit-level response is simpler to compute under assumption of Normality. Another relevant information is that the failure probability is too high. As said before, this happens due to two main reasons. The first one is that the SRAM cell used in this work is not as optimized as it can be in a commercial design, resulting in an intrinsic read noise margin of V. The second reason that leads to this unusual failure probability is the fact that the V th variation used were obtained considering that there are two traps in each transistor, the traps are close to each other and they are all occupied at the moment where the cell is being read. This is a very pessimistic case and the results show that even when this happens, 68.27% of the cells continue to work as they should. We also emphasize that despite of the general assumption that RNM is nearly linear for small variations in V th [11], such assumption does not hold for 45 nm technology node in the range of V th variations caused by RDF combined with RTS. Figure 8 illustrates RNM as being clearly non-linear in respect to V th s of the 3 transistors of the SRAM cell, varying independently. This happens partially because of the cell design (sizing).

6 J Comput Electron (2010) 9: Fig. 8 Read Noise Margin in function of the variation of the V th on M1, M2 and M3 5 Conclusions This work presents a comparison between two methods for simulating the combined effect of RDF and RTS on a SRAM. The first method is based on atomistic 3D simulations and is considered true by definition. The goal of the work was to validate the second method, which is based on the assumption of Normality of the combined effect of RTS and RDF, because it is computationally simpler than the first one. The results of the simulations with both methods are very similar which supports the assumption that it is a good approximation to model the V th as a Normal distribution. However, for large variations on the V th on small technologies the Read Noise Margin is not linear function of V th anymore. Due to this, the RNM is not expected to follow a Normal distribution on advanced deep-submicron technologies. References 1. Tega, N., et al.: Anomalously large threshold voltage fluctuation by complex random telegraph signal in floating gate flash memory. In: International Electron Devices Meeting, IEDM 06, Dec. 2006, pp. 1 4 (2006) 2. Cathignol, A., Cheng, B., Chanemougame, D., Brown, A.R., Rochereau, K., Ghibaudo, G., Asenov, A.: Quantitative evaluation of statistical variability sources in a 45-nm technological node LP N-MOSFET. IEEE Electron Device Lett. 29(6), (2008) 3. Ye, Y., Liu, F., Nassif, S., Yu, C.: Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. In: 45th ACM/IEEE Design Automation Conference, DAC, 8 13 June 2008, pp (2008) 4. Vasileska, D., Ahmed, S.S.: Narrow-width SOI devices: the role of quantum mechanical size quantization effect and the unintentional doping on the device operation. IEEE Trans. Electron Devices 52(2), (2005) 5. Spinelli, A.S., Compagnoni, C.M., Gusmeroli, R., Ghidotti, M., Visconti, A.: Investigation of the random telegraph noise instability in scaled flash memory arrays. Jpn. J. Appl. Phys. 47(4), (2008) 6. Alexander, C.L., Brown, A.R., Watling, J.R., Asenov, A.: Impact of single charge trapping in nano-mosfets-electrostatics versus transport effects. IEEE Trans. Nanotechnol. 4(3), (2005) 7. Gross, W.J., Vasileska, D., Ferry, D.K.: Ultrasmall MOSFETs: the importance of the full coulomb interaction on device characteristics. IEEE Trans. Electron Devices 47(10), (2000) 8. Gross, W.J., Vasileska, D., Ferry, D.K.: A novel approach for introducing the electron-electron and electron-impurity interactions in particle-based simulations. IEEE Electron Device Lett. 20(9), (1999) 9. Wirth, G.I., da Silva, R., Brederlow, R.: Statistical model for the circuit bandwidth dependence of low-frequency noise in deepsubmicrometer MOSFETs. IEEE Trans. Electron Devices 54, (2007) 10. Brusamarello, L., Wirth, G.I., da Silva, R., Brederlow, R.: Statistical model for the circuit bandwidth dependence of low-frequency noise in deep-submicrometer MOSFETs. IEEE Trans. Electron Devices 54, (2007) 11. Agarwal, A., et al.: Process variation in embedded memories: failure analysis and variation aware architecture. IEEE J. Solid-State Circuits 9, (2005) 12. Mukhopadhyay, S., Mahmoodi, H., Roy, K.: Statistical design and optimization of SRAM cell for yield enhancement. In: ICCAD- 2004, IEEE/ACM International Conference on Computer Aided Design, pp (2004) 13. Mukhopadhyay, S., Mahmoodi-Meimand, H., Roy, K.: Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMS for yield enhancement. In: Symposium on VLSI Circuits Digest of Technical Papers, pp (2004) 14. Nassif, S., Bernstein, K., Frank, D.J., Gattiker, A., Haensch, W., Ji, B.L., Nowak, E., Pearson, D., Rohrer, N.J.: High performance CMOS variability in the 65 nm regime and beyond. In: IEEE International Electron Devices Meeting, IEDM, Dec. 2007, pp (2007) 15. Agarwal, K., Nassif, S.: Statistical analysis of SRAM cell stability. In: Design Automation Conference, 43RD ACM/IEEE, pp (2006) 16. Balijepalli, A., Sinha, S., Cao, Y.: Compact modeling of carbon nanotube transistor for early stage process-design exploration. In: ISLPED 07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, Portland, OR, pp ACM, New York (2007) 17. Zhao, W., Cao, Y.: New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron Devices 53(11), (2006) 18. Cao, Y., Sato, T., Sylvester, D., Orshansky, M., Hu, C.: New paradigm of predictive MOSFET and interconnect modeling for early circuit design. In: CICC, pp (2000) 19. Ohbayashi, S., Yabuuchi, M., Nii, K., et al.: A 65 nm soc embedded 6t SRAM design for manufacturing with read and write cell stabilizing circuits. In: Symposium on VLSI Circuits. Digest of Technical Papers, pp (2006)