Improved V T Drift Characterization in Production Environments

Transcription

1 Improved V T Drift Characterization in Production Environments Daniel B. Habersat Aivars Lelis, Ronald Green

2 Threshold Drift, ΔV T [V] Drain Current, I D [arb] Challenges of V T Drift Assessment Objective: How to ensure that qualification tests are both useful AND practical? Challenge: The switching oxidetraps thought to be responsible for V T instability are highly sensitive to time and bias. Measurement itself allows a device to recover partially from stress. Approach: We utilized a fast (<1 µs) V T measurement system to increase sensitivity and investigate these issues consistent w/ qualification constraints Initial Delayed Immediate Gate-Source Bias, V GS [V] Fast (<1 µs) Intermediate (1 ms) Data from Vendor C COTS Stress Time, t S [s] Standard (1 s)

3 V T Drift [V] VGS [V] Experimental: Measurement Considerations V T drift results are highly dependent on the delay between stress and measurement! V GS = +15 V 2 μs measurement time Pre-stress Increasing t S Stress Time V GS = +2 V Recover Data from Vendor A COTS ΔV T as measured normally.1 2 s measurement time t S [s] t M [s] Recovery during delay appears to be the dominant reason for differences between measurements.

4 Industry requires large-scale test systems for qualification testing and screening Many SiC manufacturers qualify devices to Q11 automotive standard AEC-Q11- Rev D1 Sept. 6, 213 Difficulty with Existing HTGB Test Method for SiC MOSFETs Example of HTGB test procedure used by manufacturers for qualification: Devices stressed in parallel for 1 hours. Biased cool down to 25 C (1 min. bias interruption allowed per JESD22 - A18C for moving devices to test area). Bias interruption times generally >> 1 minute in practice. Devices can remain unbiased for up to 96 hrs. prior to electrical testing per JESD22 A18C without any requirement to reapply bias stress. JESD22-A18C does have an additional stress requirement when devices have remained unbiased for longer than 96 hrs. prior to electrical testing. Serial testing leads to variation in interrupt/delay times

5 V T Drift [V] Fractional V T Drift Gate-Source Bias V GS [V] Experimental Approach JESD22-A18D makes allowances for stress interruption and reapplication to accommodate practical-usage in production environments Section 5 Cool-down: The interruption of bias for up to one minute [ ] shall not be considered removal of bias. Delays are both necessary and accepted in qualification testing hence up to 96 hours allowed after bias removal. However, even very short bias interruptions lead to significant V T recovery. Devices are typically stressed in parallel but tested serially. Varying interrupt times between devices Need to re-apply stress in parallel OR for very short times serially. Stress time, t S t S Interrupt time, t I V T, V T,S V T,M t I Time [arb. scaling] t =1 s S % t R = s % 1 2 Interrupt Time, t I Immediate Delayed Reapplication time, t R t R 1% 75% 5% 25% Data from Vendor C COTS

6 Fractional V T Drift Reapplication of Stress Bias Can re-applying bias stress consistently and predictably counter the effects of a bias interruption? Ideally we want to measure the full drift while minimizing the time spent reapplying the bias. With a significant interruption (1% of the stress time): No reapplication results in neartotal loss of V T drift Full reapplication (t R = t S ) restores the drift highly impractical for 1,-hr HTGB! Log-time dependence leads to diminishing returns as t R t S Could shorter reapplication times be chosen which are feasible in testing while restoring most of the V T drift? (e.g., t R >1 s led to >75% of original V T drift) ts1e4 t S =1 4 s, t I =1 3 s ts1e3 t S =1 3 s, t I =1 2 s ts1e2 t S =1 2 s, t I =1 1 s Reapplication Time t R Data from Vendor C COTS

7 Fractional V Fractional T Drift T Drift Universal Drift Observed E+2 t'1e2 S =1 2 s 1.E+3 t'1e3 S =1 3 s 1.E+4 t'1e4 S =1 4 s 1.E+5 t'1e5 S =1 5 s otherwise To first-order, all fractional V T drift data taken at 25 C indicates: Constant when t R t I Independent of t S Data from Vendor A,B,C COTS t R2 t / R / t[s] I [s] t I This includes data for: Three SiC MOSFET vendors t R = [ ] s t I = [ ] s t S = [ ] s T = 25 C t R s = t I s 1 2 s consistently leads to ~75% recovery

8 Summary of Fast V T Measurement Results to date Important to understand this V T drift sensitivity w.r.t.: Longer stress times (1, hrs) Elevated temperatures (175 C) Manufacturing processes (vendor, vintage) Measurement speeds (parametric analyzer) Determine underlying mechanisms for observed empirical relationship Use results to inform improved test method Explore improved test equipment capability *Projected Initial results at room temperature indicate: Bias interruptions, while undesirable, can be better accommodated by re-applying bias t R s = t I s 1 2 s consistently leads to ~75% recovery of V T drift occurring during bias stress ~65% recovery of V T drift requires ~1 order of magnitude shorter reapplication time Even long interrupt times are likely manageable Variations in interrupt times due to serial testing not terribly important t I [hrs] t R,65% [s] t R,75% [s] t R,85% [s] * 6* 27*

9 HTGS Evaluations

10 V GS [V] Drain Current I D [ma] HTGS Measurement Overview Objective: Approach: High temperature gate switching (HTGS) using our fast I-V system Heat DUT to target temperature Apply a continuous, uninterrupted switching waveform Rise & fall time (-1%) of 4 μs dwell time (top & bottom) of 46 μs 1 μs period, 1 khz V GS from -1 V to +25 V V DS constant, ~1mV All pulses applied are identical, except that: I D is sampled during a portion of the rise & fall of selected pulses (bias output remains the same) Displacement current is measured in situ by recording V DS, I D during V GS ramp while V DS output is set to zero Time [μs] Gate-Source Bias V GS [V] Increasing stress time Data from Vendor A COTS

11 V GS [V] Threshold Voltage V T [V] Hysteresis ΔV T [V] V T at Room Temperature (25 C) Time [μs] Small negative drift in V T probably transient transitions of deeper SOTs to quasi-equilibrium with gate switching bias ΔV T remains stable (but somewhat large) No change in # of active switching traps Data from Vendor A COTS 25 C Switching Time [s] (1 4 cycles) C Switching Time [s] (1 4 cycles)

12 Hysteresis ΔV T [V] Threshold Voltage V T [V] V T at High Temperature (175 C) When switched at 175 C (outside of device s rating of 15 C) Initial hysteresis has decreased dramatically, to ~.1V from.9 V at 25 C Similar negative movement in V T at short stress times, but around s there is a strong, positive movement on each side. Consistent with activation of new acceptorlike interface traps An increase in the ΔV T width occurs at the same time, suggesting the activation of additional SOTs (which we did not observe at 25 C) Data from Vendor A COTS C Switching Time [s] (1 4 cycles) C Switching Time [s] (1 4 cycles)

13 Hysteresis ΔV T [V] Hysteresis ΔV T [V] Threshold Voltage V T [V] Threshold Voltage V T [V] COTS Comparison (25 C & 175 C) 25 C Vendor B: symbols 3.5 Vendor A: lines C Switching Time [s] (1 4 cycles) C Switching Time [s] (1 4 cycles) C C Switching Time [s] (1 4 cycles) C Switching Time [s] (1 4 cycles)

14 V GS [V] post-nbts Threshold Drift ΔV T [V] post-pbts Threshold Drift ΔV T + [V] V GS [V] All temperatures show a slight, initial decrease in V T Much like the 175 C shown above Above 1 C, a positive shift is observed after ~1 3 s Most of the shift is occurring after application of positive bias Temperature-activated drift gets worse as temperature increases! HTGS as a Function of Junction Temperature C 2 C 175 C 15 C 1 C 25 C Stress Time t S [s] Stress Time t S [s] Data from Vendor A COTS

15 V GS [V] Threshold Hysteresis Drift ΔΔV T [V] Threshold Hysteresis ΔVT [V] HTGS as a Function of Junction Temperature Monitoring the hysteresis provides additional clues ΔV T increases monotonically, rate increases with temperature Even at rated operating temperatures ( 15 C), Rated Max After 1 hr HTGS Initial Temperature [ C] C 2 C 175 C 15 C 1 C 25 C Stress Time t S [s] Data from Vendor A COTS

16 25 C Change in V T Hysteresis, post pre [V] Room Temperature Effects of HTGS Investigate the room.45 temperature hysteresis before and after 1 hr.4 HTGS Fast I-V data shows.35 significant and permanent degradation.3 DC I-V data barely registers any change (results are near.25 typical fluctuations in the data).2 Why can t a traditional test.15 measure this phenomenon? Ex situ evaluation.1 Slow measurements Unipolar stress of longer.5 duration than typical operating conditions Measured at 25 C fast I-V DC I-V HTGS Stress Temperature [ C]

17 Conclusions Stable operation at room temperature - no change observed in ΔV T Operation at high temperature Vendor A V T s moving positively likely activation of new acceptor-like interface traps ΔV T Moving positively - activation of additional SOTs Temperature-dependent activation process Suppression could be due to some combination of counteracting mechanisms and less-efficient trap charging processes Vendor B Slight negative drift in V T (as seen in 25 C) Negative ΔV T at 175 C - mobile-ion/polarization charge in the oxide Fast, in-situ measurements allow V T characterization without significant relaxation effects Slow (DC) measurements fail to observe the same results Better realization of the true shifts an operating device would experience