COTS BTS Testing and Improved Reliability Test Methods

Transcription

1 2015 August 2015 SiC MOS Program Review COTS BTS Testing and Improved Reliability Test Methods Aivars Lelis, Ron Green, Dan Habersat, and Mooro El

2 Outline Lelis (and Green) : COTS BTS results Standard measurements Habersat : COTS BTS results Fast V T measurements Test Method Comparisons Lelis (and Green) : Improved Reliability Test Methods

3 Outline I. COTS BTS results dramatic improvements in past year II. Improved Reliability Test Methods

4 Gate Voltage ARL BTI Test Procedure Stress-and-measure test sequence used to investigate BTI and underlying physical mechanisms NBTS Test Sequence NBTS and PBTS effects are studied independently on separate devices A sweep technique was used to characterize V T and V T-sub. Electrical Measurement Conditions: V ds = 50.0 mv; For V GS stress < 0 V: V GS : linear sweep from -10 V to +15 V For V GS stress > 0 V: V GS : linear sweep from +15 V to -10 V HT +V GS (DC) pre Unipolar stress: V T shift PBTS Test Sequence +V GS +V GS 100 s +V GS 1 neg V GS 1 pos Time 2 pos RT 100 s 2 neg 3 pos V GS 3 neg Back-and-forth: Oxide-trap activation 4

5 I D (A) V T (V) Time Dependent V T Degradation NBTS: 175 C, 15 V 3.5E E E E E E E E V GS (V) 175 C 175 C 1.0 V T drift is a measure of gate-oxide charging that occurs during stress 5

6 V T-sub Shift (V) V T Shift (V) Experimental Results V T Drift NBTS: 175 C, 15 V Subthreshold V T Linear V T C Vendor A ( ) Vendor A ( ) Vendor A ( ) Vendor A ( ) 175 C -8.0 The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. 6

7 V T-sub Shift (V) V T-sub Shift (V) Experimental Results V T Drift NBTS: 175 C, 15 V Vendor A vs time Vendor A vs Vendor B Vendor A ( ) Vendor A ( ) 175 C C Vendor B ( ) The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. 7

8 Experimental Results V T Drift Previous Results NBTS: 10, 15 V Vendor A ( ) vs Vendor B ( ) 200 C, 15 V 150 C, 10 V The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. Ronald Green, A. Lelis, M. El, and D. Habersat, Bias-Temperature-Stress Response of Commercially- Available SiC Power MOSFETs, Mater. Sci. Forum Vols , p. 677 (2015). 8

9 Gate Voltage ARL BTI Test Procedure Stress-and-measure test sequence used to investigate BTI and underlying physical mechanisms NBTS Test Sequence NBTS and PBTS effects are studied independently on separate devices A sweep technique was used to characterize V T and V T-sub. Electrical Measurement Conditions: V ds = 50.0 mv; For V GS stress < 0 V: V GS : linear sweep from -10 V to +15 V For V GS stress > 0 V: V GS : linear sweep from +15 V to -10 V HT +V GS (DC) pre Unipolar stress: V T shift PBTS Test Sequence +V GS +V GS 100 s +V GS 1 neg V GS 1 pos Time 2 pos RT 100 s 2 neg 3 pos V GS 3 neg Back-and-forth: Oxide-trap activation 9

10 I D (A) ΔV T-sub (V) Measured V T Hysteresis NBTS: 175 C, 15 V 1.E-01 1.E-02 1.E C C 1.E E-05 1.E-06 ΔV T-sub E E-08 1.E V GS (V) 0.5 Stress Time (s) ΔV T provides a measure of trap activation that occurs at HT 10

11 ΔV T-sub (V) ΔV T-sub (V) Experimental Results V T Hysteresis NBTS: 175 C, 15 V Vendor A vs time Vendor A vs Vendor B Vendor A ( ) T meas. = 25 C 0.2 T meas. = 25 C Vendor B ( ) 0.0 V T hysteresis is a measure of the voltage shift that occurs in response to a short-duration bipolar gate-stress. 11

12 Gate Voltage ARL BTI Test Procedure Stress-and-measure test sequence used to investigate BTI and underlying physical mechanisms NBTS Test Sequence NBTS and PBTS effects are studied independently on separate devices A sweep technique was used to characterize V T and V T-sub. Electrical Measurement Conditions: V ds = 50.0 mv; For V GS stress < 0 V: V GS : linear sweep from -10 V to +15 V For V GS stress > 0 V: V GS : linear sweep from +15 V to -10 V HT +V GS (DC) pre Unipolar stress: V T shift PBTS Test Sequence +V GS +V GS 100 s +V GS 1 neg V GS 1 pos Time 2 pos RT 100 s 2 neg 3 pos V GS 3 neg Back-and-forth: Oxide-trap activation 12

13 V T-sub Shift (V) V T Shift (V) Experimental Results V T Drift PBTS: 175 C, +25 V Subthreshold V T Linear V T Vendor A ( ) Vendor A ( ) 175 C Vendor A ( ) C The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. 13

14 V T Shift (V) V T Shift (V) Experimental Results V T Drift PBTS: 175 C, +25 V Vendor A vs time Vendor A vs Vendor B Vendor A ( ) C C Vendor B ( ) The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. 14

15 Experimental Results V T Drift Previous Results PBTS: +15 V Vendor A ( ) vs Vendor B ( ) 150 C 200 C The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. Ronald Green, A. Lelis, M. El, and D. Habersat, Bias-Temperature-Stress Response of Commercially- Available SiC Power MOSFETs, Mater. Sci. Forum Vols , p. 677 (2015). 15

16 Gate Voltage ARL BTI Test Procedure Stress-and-measure test sequence used to investigate BTI and underlying physical mechanisms NBTS Test Sequence NBTS and PBTS effects are studied independently on separate devices A sweep technique was used to characterize V T and V T-sub. Electrical Measurement Conditions: V ds = 50.0 mv; For V GS stress < 0 V: V GS : linear sweep from -10 V to +15 V For V GS stress > 0 V: V GS : linear sweep from +15 V to -10 V HT +V GS (DC) pre Unipolar stress: V T shift PBTS Test Sequence +V GS +V GS 100 s +V GS 1 neg V GS 1 pos Time 2 pos RT 100 s 2 neg 3 pos V GS 3 neg Back-and-forth: Oxide-trap activation 16

17 ΔV T-sub (V) ΔV T-sub (V) Experimental Results V T Hysteresis PBTS: 175 C, +25 V Vendor A vs time Vendor A vs Vendor B Vendor A ( ) T meas. = 25 C 2.0 T meas. = 25 C Vendor B ( ) V T hysteresis is a measure of the voltage shift that occurs in response to a short-duration bipolar gate-stress. 17

18 Outline I. COTS BTS results dramatic improvements in past year II. Improved Reliability Test Methods

19 Reliability Qualification Specifications AEC Q101 Stress Test Qualification for Automotive Grade Discrete Semiconductors JEDEC JESD-22 A108C Reliability Test Methods for Packaged Devices MIL-STD-750 Test Methods for Semiconductors AEC Q101 Rev C JESD-22 A108C Electrical testing shall be completed as soon as possible and no longer than 96 hours after removal of bias from devices.

20 Collaborators JC-13.1: Provides technical support and recommendations to DoD concerning environmental and electrical test methods and procedures for discrete electronic components. DLA: Controlling agency of military performance specifications and test methods for semiconductor devices: MIL-PRF and MIL-STD-750 Development of Improved Reliability Test Methods for SiC (and GaN) Objectives: Identify potential issues in existing performance and reliability verification test methods in MIL-PRF Propose improved test method ( Burn-in and life test for power MOSFETs) in MIL-STD- 750

21 SiC MOSFET Key Test Issues Measurement delay time Most important factor to properly assess V T stability Short delay times are recommended (< 1 ms is ideal) Long delay times relax the applied dc gate-stress and can lead to significant recovery in V T Bias removal (when measuring) Requires re-application of the gate-bias stress for at least as long as the unbiased period fast sample fast sweep 1E-6 1E-3 1E+0 1E+3 1E+6 Delay Time [s] 96-hour delay JESD-22 A108C slow sample slow sweep 1 hr delay 05/12/2015

22 Gate Voltage (V) Summary of Improved Test Method Improved Reliability Test Method for V T Stability in SiC MOSFETs Delay Time Minimize Re-apply bias if interrupted Measurement Speed and Method Standard SMU, sweeping I D -V GS Use PMU, sampled at V GS = V T for high-sensitivity application Stress-and-Measurement Sequence immediate measurement following uni-polar bias-temperature stress followed at end by: back-and-forth bipolar stress-and-measure sequence (100-s +V GS, 100-s V GS ) Measurement Temperature measure at the stress temperature re-measure at room temperature as well for high-sensitivity application fast sample fast sweep 1E-6 1E-3 1E+0 1E+3 1E+6 Delay Time [s] Schematic for improved test method -V GS (t) 96-hour delay JESD-22 A108C slow sample slow sweep HT +V GS Stress Time (s) 1 hr delay -V GS

23 V T-sub Shift (V) V T Shift (V) Summary of Commercial Results Vendor A vs Vendor B: V T Shift NBTS: 175 C, 15 V PBTS: 175 C, +25 V C Vendor B ( ) Vendor B ( ) C The observed V T shift is due to unipolar gate-stressing and charging of oxide defects. 23

24 Summary of Basic Mechanisms Oxide-Trap Activation During device processing High-Temperature stress under bias (DC and AC) activation energy of 1.1 ev evidence of interface-trap generation as well Possible HT electron trap Si Si Oxide-Trap Charging Occurs via direct tunneling mechanism Strong dependence on measurement conditions speed, direction, delay time, temperature Significant effect only under DC stress Interface traps may play intermediary role HDL (ARL) Oxide Hole-Trap Model: (Developed to explain V T instability in irradiated Si MOS.) Si Si Oxide-Trap Reduction Improved oxidation technique Reduce process-induced damage Permanently passivate oxide traps Reduce O vacancies Tie up dangling bonds

25 New Publication A.J. Lelis, R. Green, D.B. Habersat, and M. El, Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs, IEEE Trans. Elec. Dev., vol. 62:2, p 316 (February 2015).

26 End of Talk