POWER MOSFET, N-CHANNEL, RADIATION HARDENED, HIGH RELIABILITY, SPACE USE, DETAIL SPECIFICATION FOR

Size: px
Start display at page:

Download "POWER MOSFET, N-CHANNEL, RADIATION HARDENED, HIGH RELIABILITY, SPACE USE, DETAIL SPECIFICATION FOR"

Transcription

1 Registration No.98 JAXA-QTS-23/A Superseding JAXA-QTS-23/ Cancelled POWER MOSFET, N-CHANNEL, RADIATION HARDENED, HIGH RELIABILITY, SPACE USE, DETAIL SPECIFICATION FOR 448, 449, 45 45, 452, , 455, , 425, 426 Prepared and Established by Fuji Electric Device Technology Co., Ltd. Issued by Japan Aerospace Exploration Agency

2 This specification was originally written and established in the Japanese language. This specification has been translated into English for international users. Note that this document is a working document for international users. Any discrepancies found in this document should be verified against the latest Japanese document before any significant decisions are made.

3 Page i Rev. Date Description ---- A 2 December Feb. 28 Original Revision Log Added the family type part number Added Part No.: 424, 425 and 426 (V DS 3V Class Revised to reflect the changes made to JAXA-QTS-23C. Revised screening test in compliance with JAXA-QTS-23C. Revised qualification test and quality conformance inspection in compliance with JAXA-QTS-23C.

4 Page ii Contents GENERAL.... Part Number....2 Absolute Maximum Ratings Primary Electrical Characteristics Radiation Hardness APPLICABLE DOCUMENTS REQUIREMENTS Design and Construction Package Configuration and Lead Connection Lead Materials and Finish Electrical Characteristics Marking Certification QUALITY ASSURANCE PROVISIONS General Requirements Materials Control Manufacturing Process Control In-process Inspection Screening Electrical Characteristics to be Measured Test Conditions Delta Limits Qualification Test and Quality Conformance Inspection Electrostatic Discharge Sensitivity Test Radiation Hardness Test Change of Tests and Inspections Long-term Storage... 5 PREPARATION FOR DELIVERY... 6 NOTES Terms and Definitions Notice for Acquisition Officers Handling Instructions Beryllium Warning...

5 Page POWER MOSFET, N-CHANNEL, RADIATION HARDENED, HIGH RELIABILITY, SPACE USE, DETAIL SPECIFICATION FOR 448, 449, 45 45, 452, , 455, , 425, 426 GENERAL This specification establishes the detailed requirements for space use, high reliability, N channel power MOSFET (, 3, 2 and 25V for TO-254 types used for electronic equipment installed on spacecrafts. The products specified in this specification are as follows.. Part Number The part numbers for the products covered by this specification are as follows: JAXA ( R (2 448 JAXA ( R (2 449 JAXA ( R (2 45 JAXA ( R (2 45 JAXA ( R (2 452 JAXA ( R (2 453 JAXA ( R (2 454 JAXA ( R (2 455 JAXA ( R (2 456 JAXA ( R (2 424 JAXA ( R (2 425 JAXA ( R (2 426 Notes ( "JAXA" indicates that the parts are for space applications. (2 "R" indicates that the parts are radiation hardened for space applications.

6 Page 2.2 Absolute Maximum Ratings The absolute maximum ratings of the products specified in this specification are as follows. Unless otherwise specified, T A is +25 C. Part No. V DS (V (A (pulse (A V GS (V T C =25 o C (W T A =25 o C (W h ( ( o C T stg ( o C R th(ch-c ( o C/W R th(ch-a ( o C/W Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig.22 ±2 5 to Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig.37 SOA Fig Fig.39 Note( The channel temperature h is given by the following equations: Fig.4 h =T C + R th(ch-c x h =T A + R th(ch-a x Where T C : Case temperature ( C T A : Ambient temperature ( C R th(ch-c : Thermal resistance between junction and case ( C/W R th(ch-a : Thermal resistance between channel and ambient ( C/W : Power dissipation (W

7 Page 3.3 Primary Electrical Characteristics The primary electrical characteristics of the products specified in this specification are as follows. Unless otherwise specified, T A is +25 C. Part No. V (BRDSS (V =ma V GS =V Electrical Characteristics (/3 SS (μa V DS =8% of rated V DS V GS =V I GSS (na V GS =±2V V DS =V V GS(th (V =ma V DS =V GS R DS(on ( (mω =5% of rated V GS =2V gfs( (S =5% of rated V DS =25V E AS (mj Rated V DD =48V, V GS =2V Min Max Max Min-Max Max Min Max ± Note( Pulse test: Pulse width ms, Duty cycle 2%

8 Page 4 Electrical Characteristics (2/3 Part No Q GS (nc Q GD (nc Q G (nc t d(on (ns t r (ns t d(off (ns t f (ns V DS =5% of rated V DS, = rated, V GS =2V V DD =5% of rated V DS, = rated, V GS =2V, R G =Ω Max Max Max Max Max Max Max

9 Page 5 Electrical Characteristics (3/3 (Body Diode Characteristics Part No V SD ( (V I F = rated V GS =V t rr (ns Q rr (C I F = rated, V GS =V, -di/dt=a/s, h =25 o C Max Typ Typ Note( Pulse test: Pulse width ms, Duty cycle 2%

10 Page 6.4 Radiation Hardness The radiation hardness of the products specified in this specification is as follows. Symbol R Radiation hardness assurance level Gy(Si { 5 rad(si} (Dose Rate 36Gy(Si/ h to 36Gy(Si/ h 2 APPLICABLE DOCUMENTS The latest issues of documents listed below at the time of contract award or application form a part of this specification the extent specified herein. JAXA-QTS-23 Semiconductor Devices, High Reliability, Space Use, General Specification for MIL-STD-75 Test Methods Standard for Semiconductor Devices

11 Page 7 3 REQUIREMENTS 3. Design and Construction The design and construction of the products shall meet the requirements specified in this paragraph and paragraph 3.3 of JAXA-QTS Package Configuration and Lead Connection The package configuration and lead connection shall meet the requirements specified in Figure Lead Materials and Finish The leads shall be made of Fe-Ni (Ni-Au plating covered OCF (Oxygen-Free Copper and plated with Au as specified in the paragraph c or with Pb-Sn solder immersion as specified in paragraph c 2 2. of JAXA-QTS-23. In the case of Pb-Sn solder immersion, unplated lead length shall be less than 2mm from the lead egress on the product s body Electrical Characteristics The electrical characteristics shall meet the requirements specified in Tables a and b. 3.2 Marking Marking shall be in accordance with the paragraph 3.4 of JAXA-QTS-23, and Figure Certification Manufacturers who wish to supply the products specified herein shall be certified by JAXA as specified in paragraph 3. of JAXA-QTS QUALITY ASSURANCE PROVISIONS 4. General Requirements The general requirements shall be in accordance with the paragraph 4. of JAXA-QTS Materials Control The materials control shall be in accordance with the paragraph 4.2 of JAXA-QTS Manufacturing Process Control The manufacturing process control shall be in accordance with the paragraph 4.3 of JAXA-QTS In-process Inspection The in-process inspection shall be in accordance with the paragraph 4.5 of JAXA-QTS-23.

12 Page Screening The screening shall be in accordance with paragraph 4.7 of JAXA-QTS-23. The electrical characteristics to be measured, test conditions and delta limits shall be as follows Electrical Characteristics to be Measured The following parameters shall be measured during the interim and final electrical characteristics tests for screening. ( Interim electrical characteristic tests T A =+25 o C Measuring item MIL-STD-75 Test Method No. Test conditions V (BRDSS (V SS (μa I GSS (na V GS(th (V R DS(on ( (mω gfs( (S Bias Condition C =ma V GS =V Bias Condition C V DS =8% of rated V DS V GS =V Bias Condition C V GS =±2V V DS =V =ma V DS =V GS =5% of rated V GS =2V =5% of rated V DS =25V V SD ( (V I F = rated V GS =V Min Max Max Min-Max Max Min Max ± Note( Pulse test: Pulse width ms, Duty cycle 2% (2 Final electrical characteristics test: As specified in the subgroups, 2 and 3 of Tables a and b.

13 Page Test Conditions The conditions of gate stress test, avalanche energy test, temperature cycling test, reverse bias burn-in test and burn-in test for screening test shall be as follows. (Gate stress test is performed as part of In-process inspection. Gate stress test: V GS =35V, t=ms, T A =25 o C Single pulse avalanche energy (E AS test: (pulse = rated, V DD =48V, V GS =2V 5 Initial T C = + 25 o + C 2E AS BVDSS VDD L(mH = 2 Equation ( (ID BVDSS Temperature cycling test: Condition G, 2 cycles Reverse bias burn-in test (GS: T A =5 C, V GS =6V V DS =V, 48hr Burn-in test (DS: T A =5 C, V DS =8% of rated V DS V GS =V, 24hr Delta Limits The delta limits for reverse bias burn-in test and burn-in test shall be as follows. ΔI GSS 2nA ΔSS μa ΔR DS(on 2% ΔV GS(th 2% 4.6 Qualification Test and Quality Conformance Inspection The qualification test and the quality conformance inspection shall be in accordance with paragraphs 4.6 and 4.8 of JAXA-QTS-23. External dimensions, electrical characteristics, test conditions and limits shall be as specified in Figure, and Tables, 2, 3, and 4. Group C tests and Group D tests may be exempted when the qualification test or quality conformance inspection for the Groups C and D tests was performed and the device passed the test within a year. Detailed requirements are specified in Table 6. Group E tests may be exempted in spite of chip size, when the semiconductor devices manufactured from the die of the same wafer lot have passed the Group E tests in the qualification test or the quality conformance inspection Electrostatic Discharge Sensitivity Test Electrostatic discharge sensitivity test in the qualification test shall be performed with the following lead combination: Gate and Source

14 Page Radiation Hardness Test Radiation test (TID: Total Dose Irradiation level, electrical characteristics, test conditions and limits in the qualification tests and the quality conformance inspections shall be as specified in Table 5. The bias shall be maintained during the irradiation and post-irradiation electrical characteristics test. The post-irradiation electrical characteristics test shall be performed within 24 hours after the completion of irradiation. 4.7 Change of Tests and Inspections No change has been made to any test or inspection specified in appendixes A, B or C of JAXA-QTS Long-term Storage Delivery of the products stored at the manufacturer s site for 24 months or longer shall be in accordance with paragraph 4.9. of JAXA-QTS PREPARATION FOR DELIVERY Preparation for delivery shall be in accordance with Section 5 of JAXA-QTS NOTES 6. Terms and Definitions The terms and definitions used herein shall be in accordance with paragraph.2 of JAXA-QTS-23 and as follows. ( SEB (Single Event Burnout; Burnout of the device caused by the incidence of a proton or a heavy ion, when the device is applied to an off-state voltage between drain and source. (2 SEGR (Single Event Gate Rupture; Breakdown of MOSFET Gate Oxide film caused by the incidence of a proton or a heavy ion, when the device is applied to a gate bias voltage between gate and source. 6.2 Notice for Acquisition Officers The precautions to be taken by the purchaser shall be in accordance with paragraph 6.2 of JAXA-QTS-23 and as follows Handling Instructions The products specified in this specification contain thin oxide films and can be damaged due to electrostatic discharge (ESD. ESD protection measures shall be implemented to avoid ESD between the gate and source and between the gate and drain during transportation and other handling environments.

15 Page Beryllium Warning The products of TO-254 package contain beryllium. Disintegration or chemical processing of the products that may produce dusts or fumes shall be prohibited. Disposition of the products shall be performed in accordance with applicable regulations.

16 Page 2 Table -a. Group A Inspection ( Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method A - Static Characteristics Sample (T A =25 C Size LTPD 3 -a Breakdown Voltage 347 Conditions Bias Condition C Drain to Source =ma, V GS =V V DSS min min min min Limits V DC 3V DC 2V DC 25V DC -b Gate Current 34 Conditions Bias Condition C I GSS V GS =±2V, V DS =V max Limits ±na DC -c Drain Current 343 Conditions Bias Condition C Bias Condition C Bias Condition C Bias Condition C SS V DS =8V, V GS =V V DS =4V, V GS =V V DS =6V, V GS =V V DS =2V, V GS =V Limits μa DC -d Gate to Source 344 Conditions Bias Condition C Voltage (Threshold V GS =V DS, =ma V GS(th Limits max V DC -e Static Drain to Source 342 Conditions Pulse Test( 2, V GS =2V On-State Resistance R DS(on 2A 2A 7.5A 2A 7.5A 7.5A 2A 6.5A 7A 2A 3.5A 6A max [mω] max [mω] max [mω] max [mω] Limits f Forward 3475 Conditions Pulse Test( 2, V GS =25V Transconductance gfs 2A 2A 7.5A 2A 7.5A 7.5A 2A 6.5A 7A 2A 3.5A 6A min min min min Limits 8S 8S 4S 8S 8S 4S 8S 8S 4S 8S 8S 4S -g Forward Voltage --- Conditions Pulse Test( 2, V GS =V V SD 42A 42A 5A 42A 35A 5A 42A 33A 4A 42A 27A 2A max Limits.6V A -2 Static Characteristics Sample (T A =25 C Size LTPD 5-2a Gate Current 34 Conditions Bias Condition C I GSS V GS =±2V, V DS =V (25 C max Limits ±na DC -2b Drain Current 343 Conditions Bias Condition C Bias Condition C Bias Condition C Bias Condition C ISS V DS =8V, V GS =V V DS =4V, V GS =V V DS =6V, V GS =V V DS =2V, V GS =V (25 C max Limits 25μA DC -2c Gate to Source 344 Conditions Bias Condition C Voltage (Threshold V GS =V DS, =ma V GS(th min (25 C Limits.5V DC -2d Static Drain to Source 342 Conditions Pulse Test( 2, V GS =2V On-State Resistance R DS(on 2A 2A 7.5A 2A 7.5A 7.5A 2A 6.5A 7A 2A 3.5A 6A (25 C max [mω] max [mω] max [mω] max [mω] Limits Notes( The same sample may be used for all subgroups. ( 2 Pulse test: Pulse width ms, Duty cycle 2%

17 Page 3 Table -b. Group A Inspection ( Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method A -3 Static Characteristics Sample (T A =-55 C Size LTPD 5-3a Gate to Source 344 Conditions Bias Condition C Voltage (Threshold V GS =V DS, =ma V GS(th max (-55 C Limits 5.V DC -3b Forward 3475 Conditions Pulse Test ( 2, V GS =25V Transconductance gfs 2A 2A 7.5A 2A 7.5A 7.5A 2A 6.5A 7A 2A 3.5A 6A (-55 C min min min min Limits 8.5S 8.5S 4.5S 8.5S 8.5S 4.5S 8.5S 8.5S 4.5S 8.5S 8.5S 4.5S A -4 Dynamic Characteristics Sample (T A =25 C Size LTPD 3 Switching Time Test 3472 Conditions V DD =5V V DD =65V V DD =V V DD =25V ( Turn-on delay time: V GS =2V, R g =Ω V GS =2V, R g =Ω V GS =2V, R g =Ω V GS =2V, R g =Ω t d(on Rise time: t r 42A 42A 5A 42A 35A 5A 42A 33A 4A 42A 27A 2A (2 Turn-off delay time: Limits max max max max t d(off t d(on 65ns 4ns 3ns 65ns 4ns 3ns 65ns 4ns 3ns 65ns 4ns 3ns Fall time: t f t r 3ns 2ns 2ns 3ns 2ns 2ns 3ns 2ns 2ns 3ns 2ns 2ns t d(off 9ns ns 65ns 9ns ns 65ns 9ns ns 65ns 9ns ns 65ns t f 65ns 3ns 5ns 65ns 3ns 5ns 35ns 2ns 5ns 3ns 5ns ns A -6a Safe Operating Area Sample Test( 3 Size LTPD Conditions b End-Point Electrical --- Same as Gr.A- A -7 Other Characteristics Sample (T A =25 C ( 4 Size LTPD -7a Gate Charge 347 V GS =2V V GS =2V V GS =2V V GS =2V ( Gate Charge: Q g Conditions V DS =5V V DS =65V V DS =V V DS =25V (2 Gate to Drain Charge: Q gd 42A 42A 5A 42A 35A 5A 42A 33A 4A 42A 27A 2A (3 Gate to Source Limits max max max max Charge: Q gs Q g 22nC nc 5nC 22nC nc 5nC 22nC nc 5nC 22nC nc 5nC Q gd 7nC 3nC nc 7nC 3nC nc 7nC 3nC nc 7nC 3nC nc Q gs 6nC 3nC 3nC 6nC 3nC 3nC 6nC 3nC 3nC 6nC 3nC 3nC -7b Reverse Recovery 3473 Conditions IF = I F = I F = I F = Characteristics 42A 42A 5A 42A 35A 5A 42A 33A 4A 42A 27A 2A ( T rr V GS =V (2 Q rr -di/dt=a/μs Notes( The same sample may be used for all subgroups. ( 2 Pulse test: Pulse width ms, Duty cycle 2% Limits max max max max T rr 765ns 75ns 525ns 765ns 75ns 525ns 5ns2ns 95ns 5ns 35ns 95ns Q rr.5μc.μc 5.5μC 3.μC 2.μC 6.5μC 2.μC 8.μC 9.μC 29.μC 8.μC.μC ( 3 The samples used for subgroups A-, A-2, and A-3 tests shall be used. ( 4 The samples used for subgroups A-6 tests shall be used.

18 Page 4 Table 2-a. Group B Inspection Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method B - Dimensions( Sample Level I ( 2 3p Size Level II ( 2 3p 266 Conditions See Fig. B -2 Resistance to Sample Level I 3p Solvents( 3 ( 4 Size Level II 3p 22 Conditions Solvent a, b, c B -3b Temperature Cycling Sample Level I 6p (Air to Air Size Level II 6p 5 Conditions C C C cycles -3c Surge Test 466 Conditions ( Gate Shock V GS =35V (2 Avalanche 466 V DS =48V, L= See paragraph 4.5.2, Equation (, R g =Ω Conditions (pulse 42A 42A 5A 42A 35A 5A 42A 33A 4A 42A 27A 2A -3d Hermetic Seal 7 Conditions ( Fine Condition H max Limits -3 Pa-cm 3 /s (2 Gross 7 Conditions --- Condition C -3e End-Point Electrical --- Conditions Same as Gr.A- -3f Decap-Internal 275 Conditions Visual g Bond Strength 237 Conditions Condition A Limits Gate Wire >9gf Source Wire >3gf >3gf >9gf >3gf >3gf >9gf >3gf >3gf >9gf >3gf >3gf >9gf -3h SEM( 277 Conditions i Die Shear Sample Level I 3p Size Level II 3p 27 Conditions --- Limits min 2.5kgf B -4 Solderability( 3 ( 4 Sample Level I 6 leads( 5 Size Level II 6 leads( Conditions --- Notes( The test may be performed using the samples prior to inspection lot formation. ( 2 Level I and Level II shall be applicable to the qualification test or the quality conformance inspection, respectively. (See paragraphs C.3.2 and C.3.3 of JAXA-QTS-23 ( 3 Electrically defective products from the same inspection lot may be used. ( 4 When electrically defective products are used, the samples shall be exposed to the same thermal environments as the certified samples experience in all thermal tests required as part of the screening test. ( 5 This test shall be performed for each 3 lead from 2 devices.

19 Page 5 Table 2-b. Group B Inspection Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method B -5a Intermittent Sample Level I LTPD Operation Life Size Level II 2p 42 Conditions Condition D, 2 cycles( -5b End-Point Electrical --- Same as Gr.A- B -6c Accelerated Sample Level I LTPD Steady-state Size Level II 2p Gate Stress (High 42 Conditions V GS =2V, T A =5 C, 48hr Temp. GS or V GS =2V, T A =75 C, 24hr -6d End-Point Electrical --- Same as Gr.A- -6e Accelerated 42 Conditions V DS =V V DS =3V V DS =2V V DS =25V Steady-state T A =5 C, 24hr Reverse Bias (DS or T A =75 C, 2hr -6f End-Point Electrical --- Conditions Same as Gr.A- -6g Bond Strength Sample 2 wires Size 237 Conditions Condition A Limits Gate Wire >9gf Source Wire >3gf >3gf >9gf >3gf >3gf >9gf >3gf >3gf >9gf >3gf >3gf >9gf B -7 Thermal Resistance Sample Level I LTPD R th(ch-c (ΔV SD Size Level II 8p 36 Conditions TA =25 C max ( C/W max ( C/W max ( C/W max ( C/W Limits Note( If the samples are also used for Intermittent operating life test of C- in the Group C test, the test shall be performed up to 6 cycles.

20 Page 6 Table 3. Group C Inspection Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method C -a Intermittent Sample Level I LTPD Operation Life Size Level II LTPD 42 Conditions Condition D, 6 cycles ( -b End-Point Electrical --- Conditions Same as Gr.A- C -2a Steady-state Bias Sample Level I LTPD 5 Life test (high Size Level II NA temperature 42 Conditions V GS =6V GS applied ( 2 T A =5 C, hr -2b End-Point Electrical --- Conditions Same as Gr.A- -2c Steady-state Bias 42 Conditions V DS =8V V DS =4V V DS =6V V DS =2V Life test (high temperature DS applied ( 2 T A =5 C, hr -2d End-Point Electrical --- Conditions Same as Gr.A- C -2a Thermal Shock Sample Level I 2p Temperature Cycling Size Level II NA 5 Conditions C C C cycles -2b Hermetic Seal 7 Conditions Condition H ( Fine max Limits -3 Pa-cm 3 /s (2 Gross 7 Conditions Condition C -2c End-Point Electrical --- Conditions Same as Gr.A- ( 3 C -3 Thermal Resistance Sample Level I LTPD ( 4 Size Level II 8p R th(ch-c (ΔV SD 36 Conditions T A =25 C max ( C/W max ( C/W max ( C/W max ( C/W Limits C -4a Safe Operating Sample Level I LTPD Area Test( 5 Size Level II LTPD 3474 Conditions b End-Point Electrical --- Conditions Same as Gr.A- ( 5 C -6a Electric Discharge Sample Level I 3p Sensitivity Size Level II NA Classification 2 Conditions V GS ±275V ±V ±5V ±275V ±V ±5V ±275V ±V ±5V ±275V ±V ±5V V DS =V -6b End-Point Electrical --- Conditions Same as Gr.A- Notes( For the quality conformance inspection, the cycles may be reduced to 2 cycles as a minimum. ( 2 The legibility of the marking shall not apply. ( 3 This test may be conducted prior to the hermetic seal. ( 4 Thermal impedance curve shall be obtained during the qualification test. ( 5 This test may be exempted if performed in the Group A test.

21 Page 7 Table 4-a. Group D Inspection Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method D -a Thermal Shock Sample Level I LTPD 5 (Glass Strain Size Level II LTPD 5 56 Conditions Condition B, 5 cycles -b Thermal Shock 5 Conditions C C C (Temperature Cycling 45 cycles -c Terminal Strength 236 Conditions Condition A.5kg, 3s -d Moisture Resistance 2 Conditions (MIL-STD-22, Method 6 -e Hermetic Seal 7 Conditions Condition H ( Fine (2 Gross 7 Conditions max Limits -3 Pa-cm 3 /s Condition C -f Visual Inspection 5 Conditions g End-Point Electrical --- Conditions Same as Gr.A- D -2a Shock( Sample Level I LTPD 5 Size Level II LTPD 5 26 Conditions No Operating, 47m/s 2 (5G 5 blows in each orientation, X, Y, Y 2 and Z -2b Vibration, Variable 256 Conditions to 2 Hz, 4min Frequency( 96. m/s 2 (2G -2c Constant 26 Conditions m/s 2 (G Acceleration( X, Y, Y 2 and Z orientation -2d Hermetic Seal( 7 Conditions Condition H ( Fine (2 Gross 7 Conditions max Limits -3 Pa-cm 3 /s Condition C -2e End-Point Electrical --- Conditions Same as Gr.A- ( D -3a Salt Atmosphere( 2 Sample Level I LTPD 5 Size Level II LTPD 5 4 Conditions 35 C, 24hr Rate of salt deposit= to 5g/m 2 /24hr Notes( Samples used for subgroup may be used. ( 2 Electrically defective products from the same inspection lot may be used.

22 Page 8 Table 4-b. Group D Inspection Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method D -4 Barometric Pressure Sample Level I 3p (reduced Size Level II NA Conditions 8mmHg Not applicable for devices with rated voltage 2V. D -5 Internal Water Vapor Sample Level I 3p ( Size Level II 3p 8 Conditions --- 6sec (minimum V DS =25V, V GS =V D -6a Resistance to Sample Level I 3p Soldering Heat Size Level II NA 23 Conditions 25 C, s -6b Visual Inspection --- Conditions c Hermetic Seal 7 Conditions Condition H ( Fine (2 Gross 7 Conditions max Limits -3 Pa-cm 3 /s Condition C -6d End-Point Electrical --- Conditions Same as Gr.A- Note( Electrically defective products from the same inspection lot may be used.

23 Page 9 Table 5. Group E Inspection Gr.No MIL-STD-75 V Class 3V Class 2V Class 25V Class Sub Test Item Method E -a Total Dose Sample Level I 4p( Irradiation Size Level II 4p( (TID 9 Conditions Total Dose 3 Gy(Si Dose Rate 36Gy(Si/h to 36Gy(Si/h Bias Condition (during irradiation, after irradiation (a V DS =V, V GS =2V (b V DS =V, V GS =-2V (c V DS =8V, (c V DS =4V, (c V DS =6V, (c V DS =2V, V GS =V V GS =V V GS =V V GS =V -b End-Point Electrical Within 24hr after irradiation ( Breakdown Voltage 347 Conditions Bias Condition C Drain to Source =ma, V GS =V V DSS min min min min Limits V DC 3V DC 2V DC 25V DC (2 Gate Current 34 Conditions Bias Condition C I GSS V GS =±2V, V DS =V Limits max ±na DC (3 Drain Current 343 Conditions Bias Condition C Bias Condition C Bias Condition C Bias Condition C SS V DS =8V, V GS =V V DS =4V, V GS =V V DS =6V, V GS =V V DS =2V, V GS =V Limits max μa DC (4 Gate to Source 344 Conditions Bias Condition C Voltage (Threshold V GS =V DS, =ma V GS(th min.5v DC Limits ΔV GS(th max 2.V (5 Static Drain to Source 342 Conditions Pulse Test( 2, V GS =2V On-State Resistance R DS(on 2A 2A 7.5A 2A 7.5A 7.5A 2A 6.5A 7A 2A 3.5A 6A max [mω] max [mω] max [mω] max [mω] Limits Notes( This test shall be performed for each single wafer lot. When an inspection lot consists of multiple inspection sublots, one inspection sublot may be performed this test. ( 2 Pulse test: Pulse width ms, Duty cycle 2%

24 Page 2 Table 6. Exemption of Quality Conformance Inspection When the qualification test or the quality conformance inspection for products specified as following table was initiated within a year from the completion date of the screening test for the inspection lot, and the device passed the test or inspection, the corresponding tests may be exempted. Gr.No V Class 3V Class 2V Class 25V Class Sub JAXA-QTS-23 Appendix C Die Size Die Size Die Size Die Size Test Item / /2 /4 / /2 /4 / /2 /4 / /2 /4 C -a Intermittent Operation Life -b End-Point Electrical These tests may be exempted when the following two conditions are satisfied. When the devices having the same die size or larger die size passed. -2a Temperature Cycling When the devices passed using the value of V DS defined in paragraph.2 or -2b Hermetic Seal larger value of the V DS. -2c End-Point Electrical -3 Thermal Resistance This test may be exempted when the device passed in the Group B-7 test. -4a Safe Operating Area Test -4b End-Point Electrical This test may be exempted when the device passed in the Group A-6 test. D -a Thermal Shock (Glass Strain -b Thermal Shock (Temperature Cycling -c Terminal Strength -d Moisture Resistance -e Hermetic Seal -f Visual Inspection This test may be exempted when any one of the products passed in the Group D- -g End-Point Electrical test. -2a Shock -2b Vibration, Variable Frequency -2c Constant Acceleration -2d Hermetic Seal -2e End-Point Electrical -3a This test may be exempted when any one of the products passed in the Group D-3 Salt Atmosphere test. This test may be -4 Barometric Pressure -5 Internal Water Vapor This test shall not be performed in the quality conformance inspection. exempted when the device having same package passed in this test. This test may be exempted when any one of the products passed in the Group D-5 test.

25 Page 2 Note: All leads are isolated from the case. Figure. Package Configuration and Lead Connection of TO-254 type package

26 Page 22 BeO is used Figure 2. Marking

27 Page 23 V DD=5% of rated V DS R L V DS V GS=2V R G=Ω 9% % V GS t d(on t r t d(off t f V DS 9% 9% % % Figure 3. Switching time test circuit and waveforms Z Y 2 X 2 D S G X Y Z 2 Figure 4. Orientation

28 448 Page Fig. 5 =f( Fig. 6 T a =f(t a Operation in this area Limited by R DS(on 5 [A] PW=ms =25 T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS PW=5ms PW=ms Fig. 7 Fig =f( Operation in this area Limited by R DS(on 3 2 [A] T a =f(t a =25 T j =5 Single Pulse Fig. 9 Fig.. V DS [V] Maximum Safe Operating Area =f(v DS PW=ms PW=5ms PW=ms

29 45 Page =f( Fig. Fig T a =f(t a Operation in this area Limited by R DS(on 3 2 [A] PW=ms PW=5ms PW=ms =25 T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS Fig. 3 Fig =f( Operation in this area Limited by R DS(on 3 2 [A] T a =f(t a Fig. 5 Fig. 6 PW=ms T PW=5ms c =25 PW=ms T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS

30 452 Page Fig. 7 =f( Fig. 8 T a =f(t a Operation in this area Limited by R DS(on [A] PW=ms PW=5ms PW=ms. =25 T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS Fig. 9 Fig =f( Operation in this area Limited by R DS(on 3 2 [A] T a =f(t a =25 T j =5 Single Pulse Fig. 2 Fig. 22. V DS [V] Maximum Safe Operating Area =f(v DS PW=ms PW=5ms PW=ms

31 Page =f( Fig. 23 Fig T a =f(t a Operation in this area Limited by R DS(on 2 5 [A] PW=ms =25 T PW=5ms j =5 PW=ms Single Pulse. V DS [V] Fig. 25 Fig. 26 Maximum Safe Operating Area =f(v DS =f( Operation in this area Limited by R DS(on 3 2 [A] T a =f(t a. =25 T j =5 Single Pulse Fig. 27 Fig. 28. V DS [V] Maximum Safe Operating Area =f(v DS PW=ms PW=5ms PW=ms

32 456 Page =f( Fig. 29 Fig T a =f(t a Operation in this area Limited by R DS(on 3 2 [A] PW=ms =25 PW=5ms T j =5 PW=ms Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS Fig. 3 Fig =f( Operation in this area Limited by R DS(on T a =f(t a Fig. 33 Fig. 34 [A] =25 T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS PW=ms PW=5ms PW=ms

33 Page =f( Fig. 35 Fig T a =f(t a Operation in this area Limited by R DS(on [A] 5 =25 T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS PW=ms PW=5ms PW=ms Fig. 37 Fig =f( Operation in this area Limited by R DS(on [A] PW=ms PW=5ms PW=ms T a =f(t a Fig. 39 Fig. 4 =25 T j =5 Single Pulse. V DS [V] Maximum Safe Operating Area =f(v DS

Features. Symbol Parameter Rating Units V DS Drain-Source Voltage 30 V V GS Gate-Source Voltage ±20 V

Features. Symbol Parameter Rating Units V DS Drain-Source Voltage 30 V V GS Gate-Source Voltage ±20 V General Description These N-Channel enhancement mode power field effect transistors are using trench DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance,

More information

AO3411 P-Channel Enhancement Mode Field Effect Transistor

AO3411 P-Channel Enhancement Mode Field Effect Transistor January 23 AO3411 P-Channel Enhancement Mode Field Effect Transistor General Description The AO3411 uses advanced trench technology to provide excellent R DS(ON), low gate charge and operation with gate

More information

AOT404 N-Channel Enhancement Mode Field Effect Transistor

AOT404 N-Channel Enhancement Mode Field Effect Transistor AOT44 N-Channel Enhancement Mode Field Effect Transistor General Description The AOT44 uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. This device is suitable

More information

N- & P-Channel Enhancement Mode Field Effect Transistor

N- & P-Channel Enhancement Mode Field Effect Transistor PRODUCT SUMMARY V (BR)DSS R DS(ON) I D annel 30 27.5m 7A annel -30 34m -6A G : GATE D : DRAIN S : SOURCE ABSOLUTE MAXIMUM RATINGS (T C = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL annel

More information

AO7401 P-Channel Enhancement Mode Field Effect Transistor

AO7401 P-Channel Enhancement Mode Field Effect Transistor Nov P-Channel Enhancement Mode Field Effect Transistor General Description The uses advanced trench technology to provide excellent R DS(ON), low gate charge, and operation with gate voltages as low as.5v,

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor CoolMOS TM Power Transistor Features New revolutionary high voltage technology Extreme dv/dt rated High peak current capability Qualified according to JEDEC 1) for target applications Pb-free lead plating;

More information

OptiMOS 3 M-Series Power-MOSFET

OptiMOS 3 M-Series Power-MOSFET BSO15N3MD G OptiMOS 3 M-Series Power-MOSFET Features Dual N-channel Optimized for 5V driver application (Notebook, VGA, POL) Low FOM SW for High Frequency SMPS 1% Avalanche tested Product Summary V DS

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor BSO9N3S OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for notebook DC/DC converters Qualified according to JEDEC ) for target applications Product Summary V DS

More information

OptiMOS 3 M-Series Power-MOSFET

OptiMOS 3 M-Series Power-MOSFET BSO33N3MS G OptiMOS 3 M-Series Power-MOSFET Features Optimized for 5V driver application (Notebook, VGA, POL) Low FOM SW for High Frequency SMPS % Avalanche tested N-channel Product Summary V DS 3 V R

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor CoolMOS TM Power Transistor Features New revolutionary high voltage technology Extreme dv/dt rated High peak current capability Product Summary V DS 8 V R DS(on)max @ T j = 5 C.7 Ω Q g,typ 1 nc Qualified

More information

500V N-Channel MOSFET

500V N-Channel MOSFET 830 / 830 500V N-Channel MOSFET General Description This Power MOSFET is produced using SL semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize

More information

AON4605 Complementary Enhancement Mode Field Effect Transistor

AON4605 Complementary Enhancement Mode Field Effect Transistor AON5 Complementary Enhancement Mode Field Effect Transistor General Description The AON5 uses advanced trench technology to provide excellent R DS(ON) and low gate charge. The complementary MOSFETs form

More information

AOP606 Complementary Enhancement Mode Field Effect Transistor

AOP606 Complementary Enhancement Mode Field Effect Transistor AOP66 Complementary Enhancement Mode Field Effect Transistor General Description The AOP66 uses advanced trench technology MOSFETs to provide excellent and low gate charge. The complementary MOSFETs may

More information

OptiMOS 3 Power-Transistor

OptiMOS 3 Power-Transistor OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 1 V R DS(on),max 7.2 mω I D 8 A Very low on-resistance R DS(on) 175 C operating

More information

OptiMOS 3 Power-Transistor

OptiMOS 3 Power-Transistor OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 8 V R DS(on),max 2.8 mω I D 1 A Very low on-resistance R DS(on) 175 C operating

More information

OptiMOS -P Small-Signal-Transistor

OptiMOS -P Small-Signal-Transistor SPD5P3L OptiMOS -P Small-Signal-Transistor Features P-Channel Enhancement mode Logic level Product Summary V DS -3 V R DS(on),max 7 mω I D -5 A 175 C operating temperature Avalanche rated dv /dt rated

More information

OptiMOS TM P3 Power-Transistor

OptiMOS TM P3 Power-Transistor BSZ86P3NS3E G OptiMOS TM P3 Power-Transistor Features single P-Channel in S3O8 Qualified according JEDEC ) for target applications 5 C operating temperature V GS =25 V, specially suited for notebook applications

More information

SIPMOS Power-Transistor

SIPMOS Power-Transistor SPP18P6P G SIPMOS Power-Transistor Features P-Channel Enhancement mode Avalanche rated dv /dt rated 175 C operating temperature Product Summary V DS -6 V R DS(on),max.13 Ω I D -18.6 A PG-TO22-3 Type Package

More information

OptiMOS (TM) 3 Power-Transistor

OptiMOS (TM) 3 Power-Transistor Type BSZ123N8NS3 G OptiMOS (TM) 3 Power-Transistor Package Optimized technology for DC/DC converters Excellent gate charge x R DS(on) product (FOM) Superior thermal resistance Product Summary V DS 8 V

More information

OptiMOS 3 Power-MOSFET

OptiMOS 3 Power-MOSFET OptiMOS 3 Power-MOSFET Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC 1) for target applications N-channel Product Summary V DS 3 V R DS(on),max

More information

CoolMOS Power Transistor

CoolMOS Power Transistor CoolMOS Power Transistor Features Lowest figure-of-merit R ON xq g Ultra low gate charge Extreme dv/dt rated Product Summary V DS @ T j,max 65 V R DS(on),max.199 Ω Q g,typ 32 nc High peak current capability

More information

SSF7NS65UF 650V N-Channel MOSFET

SSF7NS65UF 650V N-Channel MOSFET Main Product Characteristics V DSS R DS(on) 650V 0.6Ω (typ.) I D 7A 1 Features and Benefits TO-220F Marking and Pin Assignment S c h e m a ti c Dia g r a m High dv/dt and avalanche capabilities 100% avalanche

More information

N-Channel 30-V (D-S) MOSFET With Sense Terminal

N-Channel 30-V (D-S) MOSFET With Sense Terminal SUM5N3-3LC N-Channel 3-V (D-S) MOSFET With Sense Terminal PRODUCT SUMMARY V (BR)DSS (V) r DS(on) ( ) (A).3 @ V S = V 5 a 3.7 @ V S =.5 V a FEATURES TrenchFET Power MOSFET Plus Current Sensing Diode New

More information

Max Q1. Symbol V GS I DM 15 I DSM 7.8 I AS E AS V SPIKE P D 2.5 P DSM. Junction and Storage Temperature Range T J, T STG

Max Q1. Symbol V GS I DM 15 I DSM 7.8 I AS E AS V SPIKE P D 2.5 P DSM. Junction and Storage Temperature Range T J, T STG 3V Dual Asymmetric N-Channel AlphaMOS General Description Latest Trench Power AlphaMOS (αmos LV) technology Very Low RDS(on) at 4.V GS Low Gate Charge High Current Capability RoHS and Halogen-Free Compliant

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor IPI3N3LA, IPP3N3LA OptiMOS 2 Power-Transistor Features Ideal for high-frequency dc/dc converters Qualified according to JEDEC ) for target applications N-channel - Logic level Product Summary V DS 25 V

More information

AO4802 Dual N-Channel Enhancement Mode Field Effect Transistor

AO4802 Dual N-Channel Enhancement Mode Field Effect Transistor July 2 AO482 Dual N-Channel Enhancement Mode Field Effect Transistor General Description The AO482 uses advanced trench technology to provide excellent R DS(ON) and low gate charge. They offer operation

More information

AO4620 Complementary Enhancement Mode Field Effect Transistor

AO4620 Complementary Enhancement Mode Field Effect Transistor AO46 Complementary Enhancement Mode Field Effect Transistor General Description The AO46 uses advanced trench technology MOSFETs to provide excellent and low gate charge. The complementary MOSFETs may

More information

OptiMOS 3 Power-MOSFET

OptiMOS 3 Power-MOSFET BSC886N3LS G OptiMOS 3 Power-MOSFET Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC 1) for target applications N-channel Logic level Product

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor IPW6R125CP CoolMOS TM Power Transistor Features Lowest figure-of-merit R ON xq g Ultra low gate charge Extreme dv/dt rated Product Summary V DS @ T j,max 65 V R DS(on),max.125 Ω Q g,typ 53 nc High peak

More information

OptiMOS (TM) 3 Power-Transistor

OptiMOS (TM) 3 Power-Transistor BSZ67N6LS3 G OptiMOS (TM) 3 Power-Transistor Features Ideal for high frequency switching and sync. rec. Optimized technology for DC/DC converters Excellent gate charge x R DS(on) product (FOM) Product

More information

CoolMOS Power Transistor

CoolMOS Power Transistor CoolMOS Power Transistor Features new revolutionary high voltage technology Extreme dv/dt rated High peak current capability Qualified according to JEDEC 1) for target applications Pb-free lead plating;

More information

OptiMOS 3 Power-Transistor

OptiMOS 3 Power-Transistor BSZ4N4LS G OptiMOS 3 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC 1) for target applications Product Summary V DS 4 V

More information

OptiMOS (TM) 3 Power-Transistor

OptiMOS (TM) 3 Power-Transistor IPD96N8N3 G OptiMOS (TM) 3 Power-Transistor Features Ideal for high frequency switching Optimized technology for DC/DC converters Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 8 V

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor OptiMOS 2 Power-Transistor Features Ideal for high-frequency dc/dc converters Qualified according to JEDEC 1) for target application N-channel, logic level Product Summary V DS 25 V R DS(on),max (SMD version)

More information

AO4607, AO4607L(Lead-Free) Complementary Enhancement Mode Field Effect Transistor

AO4607, AO4607L(Lead-Free) Complementary Enhancement Mode Field Effect Transistor Rev : Feb 3 Rev : Jan 4 AO467, AO467L(Lead-Free) Complementary Enhancement Mode Field Effect Transistor General Description The AO467 uses advanced trench technology MOSFETs to provide excellen R DS(ON)

More information

SIPMOS Small-Signal-Transistor

SIPMOS Small-Signal-Transistor SIPMOS Small-Signal-Transistor Features P-Channel Enhancement mode Logic level Product Summary V DS - V R DS(on),max 8 mw I D - A Avalanche rated Pb-free lead plating; RoHS compliant PG-SOT-3 Qualified

More information

OptiMOS Power-Transistor

OptiMOS Power-Transistor OptiMOS Power-Transistor Features N-channel - Enhancement mode Automotive AEC Q11 qualified MSL1 up to 26 C peak reflow 175 C operating temperature Green package (lead free) Product Summary V DS 75 V R

More information

SSF65R580F. Main Product Characteristics 700V. V J max. 0.52Ω (typ.) I D 8.0A TO-220F. Features and Benefits. Description

SSF65R580F. Main Product Characteristics 700V. V J max. 0.52Ω (typ.) I D 8.0A TO-220F. Features and Benefits. Description Main Product Characteristics V DSS @T J max R DS (on) 700V 0.52Ω (typ.) 8.0A TO-220F Schematic Diagram Features and Benefits Low R DS(on) and FOM Extremely low switching loss Excellent stability and uniformity

More information

Data Sheet BUY25CS54A-01

Data Sheet BUY25CS54A-01 HiRel RadHard Power-MOS Low R DS(on) Single Event Effect (SEE) hardened LET 85, Range: 118µm LET 55, Range: 90µm V GS = -10V, V DS = 250V V GS = -15V, V DS = 250V V GS = -15V, V DS = 120V V GS = -20V,

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor CoolMOS TM Power Transistor Features New revolutionary high voltage technology Extreme dv/dt rated High peak current capability Product Summary V DS 8 V R DS(on)max @ T j = 25 C.29 Ω Q g,typ 88 nc Qualified

More information

OptiMOS 3 Power-Transistor

OptiMOS 3 Power-Transistor BSC27N4LS G OptiMOS 3 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC ) for target applications Product Summary V DS 4 V

More information

AO V Dual P + N-Channel MOSFET

AO V Dual P + N-Channel MOSFET 4V Dual P + N-Channel MOSFET General Description The AO467 uses advanced trench technology MOSFETs to provide excellent and low gate charge. The complementary MOSFETs may be used in H-bridge, Inverters

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor CoolMOS TM Power Transistor Features Lowest figure of merit R ON x Q g Ultra low gate charge Extreme dv/dt rated Product Summary V DS @T jmax 55 V R DS(on),max.52 Ω Q g,typ 13 nc High peak current capability

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor SPP15N6CFD CoolMOS TM Power Transistor Features Intrinsic fast-recovery body diode Extremely low reverse recovery charge Ultra low gate charge Extreme dv /dt rated High peak current capability Product

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor BSC32N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for notebook DC/DC converters Qualified according to JEDEC 1 for target applications Product Summary V

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor CoolMOS TM Power Transistor Features New revolutionary high voltage technology Extreme dv/dt rated High peak current capability Product Summary V DS 8 V R DS(on)max @ T j = 5 C.7 W Q g,typ 1 nc Qualified

More information

SIPMOS Small-Signal-Transistor

SIPMOS Small-Signal-Transistor SIPMOS Small-Signal-Transistor Features P-Channel Enhancement mode / Logic level Avalanche rated Product Summary V DS - V R DS(on),max.8 W I D -.36 A Pb-free lead plating; RoHS compliant Footprint compatible

More information

Automotive N- and P-Channel 40 V (D-S) 175 C MOSFET

Automotive N- and P-Channel 40 V (D-S) 175 C MOSFET SQJ54EP Automotive N- and P-Channel 4 V (D-S) 75 C MOSFET 6.5 mm mm PowerPAK SO-8L Dual 5.3 mm D D 4 G 3 S G S FEATURES TrenchFET power MOSFET AEC-Q qualified % R g and UIS tested Material categorization:

More information

P-Channel Enhancement Mode Mosfet

P-Channel Enhancement Mode Mosfet WPM34 WPM34 P-Channel Enhancement Mode Mosfet Http://www.sh-willsemi.com Features Higher Efficiency Extending Battery Life Miniature SOT3-3 Surface Mount Package Super high density cell design for extremely

More information

OptiMOS TM 3 Power-Transistor

OptiMOS TM 3 Power-Transistor OptiMOS TM 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 15 V R DS(on),max (TO263) 1.8 mw I D 83

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor IPB12CN1N G OptiMOS 2 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 1 V R DS(on),max (TO252) 12.4

More information

OptiMOS -5 Power-Transistor

OptiMOS -5 Power-Transistor OptiMOS -5 Power-Transistor Product Summary V DS 4 V R DS(on),max mw Features OptiMOS - power MOSFET for automotive applications I D A PG-HSOF-5 N-channel - Enhancement mode - Normal Level AEC Q qualified

More information

GP1M003A080H/ GP1M003A080F GP1M003A080HH/ GP1M003A080FH

GP1M003A080H/ GP1M003A080F GP1M003A080HH/ GP1M003A080FH Features Low gate charge 1% avalanche tested Improved dv/dt capability RoHS compliant Halogen free package JEDEC Qualification S = 88 V @T jmax = 3A R DS(ON) =. (max) @ = 1 V D G Absolute Maximum Ratings

More information

OptiMOS 3 Power-Transistor

OptiMOS 3 Power-Transistor Type IPD135N3L G OptiMOS 3 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC 1) for target applications Product Summary V DS

More information

CoolMOS TM Power Transistor

CoolMOS TM Power Transistor CoolMOS TM Power Transistor Features Worldwide best R DS,on in TO22 Lowest figure of merit R ON x Q g Ultra low gate charge Product Summary V DS @T jmax 55 V R DS(on),max.14 Ω Q g,typ 48 nc Extreme dv/dt

More information

OptiMOS TM Power-MOSFET

OptiMOS TM Power-MOSFET BSC1NE2LS OptiMOS TM Power-MOSFET Features Optimized for high performance Buck converter Very low on-resistance R DS(on) @ V GS =4.5 V 1% avalanche tested Superior thermal resistance N-channel Qualified

More information

SPECIFICATIONS (T J = 25 C, unless otherwise noted)

SPECIFICATIONS (T J = 25 C, unless otherwise noted) N-Channel V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) () I D (A) a, e Q g (Typ.). at V GS = V. at V GS = 4.5 V nc DFN 3x3 EP Top View Bottom View FEATURES APPLICATIONS Top View D 3 4 8 7 6 5 G Pin

More information

Features. Symbol Parameter Rating Units V DS Drain-Source Voltage 600 V V GS Gate-Source Voltage ±30 V

Features. Symbol Parameter Rating Units V DS Drain-Source Voltage 600 V V GS Gate-Source Voltage ±30 V General Description These N-Channel enhancement mode power field effect transistors are planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance,

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor IPB26CN1N G IPD25CN1N G OptiMOS 2 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 1 V R DS(on),max

More information

OptiMOS TM Power-Transistor

OptiMOS TM Power-Transistor Type OptiMOS TM Power-Transistor Features Optimized for high performance SMPS, e.g. sync. rec. % avalanche tested Superior thermal resistance N-channel Qualified according to JEDEC ) for target applications

More information

OptiMOS TM 3 Power-Transistor

OptiMOS TM 3 Power-Transistor IPB2N25N3 G OptiMOS TM 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 25 V R DS(on),max 2 mw I D

More information

Distributed by: www.jameco.com 1-8-831-4242 The content and copyrights of the attached material are the property of its owner. BSC22N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS

More information

Product Summary: BVDSS 30V RDSON (MAX.) 50mΩ 4.5A I D. Pb Free Lead Plating & Halogen Free EMB50P03J

Product Summary: BVDSS 30V RDSON (MAX.) 50mΩ 4.5A I D. Pb Free Lead Plating & Halogen Free EMB50P03J P Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: BVDSS V RDSON (MAX.) ID 5mΩ.5A Pb Free Lead Plating & Halogen Free D G S ABSOLUTE MAXIMUM RATINGS (T A = 5 C Unless Otherwise

More information

CoolMOS Power Transistor

CoolMOS Power Transistor CoolMOS Power Transistor Features Lowest figure-of-merit R ON x Q g Extreme dv/dt rated High peak current capability Product Summary V DS @ T J =25 C 9 V R DS(on),max @ T J = 25 C.5 Ω Q g,typ 68 nc Qualified

More information

OptiMOS TM Power-Transistor

OptiMOS TM Power-Transistor Type BSC14N6NS OptiMOS TM Power-Transistor Features Optimized for high performance SMPS, e.g. sync. rec. 1% avalanche tested Superior thermal resistance N-channel Qualified according to JEDEC 1) for target

More information

OptiMOS -P Small-Signal-Transistor

OptiMOS -P Small-Signal-Transistor OptiMOS -P Small-Signal-Transistor Features P-Channel Enhancement mode Super Logic level ( 2.5 V rated) 5 C operating temperature Avalanche rated Product Summary V DS -2 V R DS(on),max 55 mω I D -.63 A

More information

Automotive N- and P-Channel 100 V (D-S) 175 C MOSFET

Automotive N- and P-Channel 100 V (D-S) 175 C MOSFET SQJ57EP Automotive N- and P-Channel V (D-S) 75 C MOSFET PRODUCT SUMMARY N-CHANNEL P-CHANNEL V DS (V) - R DS(on) ( ) at V GS = ± V.45 46 R DS(on) ( ) at V GS = ± 4.5 V.58.265 I D (A) 5-9.5 Configuration

More information

OptiMOS TM Power-MOSFET

OptiMOS TM Power-MOSFET BSNNE2LS OptiMOS TM Power-MOSFET Features Optimized for high performance Buck converter Very low parasitic inductance Low profile (

More information

OptiMOS TM Power-Transistor

OptiMOS TM Power-Transistor Type IPD25N6N OptiMOS TM Power-Transistor Features Optimized for synchronous rectification % avalanche tested Superior thermal resistance N-channel, normal level Qualified according to JEDEC ) for target

More information

OptiMOS -T2 Power-Transistor

OptiMOS -T2 Power-Transistor OptiMOS -T2 Power-Transistor Product Summary V DS 4 V R DS(on),max 4.1 mω Features N-channel - Enhancement mode AEC qualified I D 9 A PG-TO252-3-313 MSL1 up to 26 C peak reflow 175 C operating temperature

More information

OptiMOS 3 Power-MOSFET

OptiMOS 3 Power-MOSFET BSB14N8NP3 G OptiMOS 3 Power-MOSFET Features Optimized technology for DC/DC converters Excellent gate charge x R DS(on) product (FOM) Low profile (

More information

TO-247-3L Inner Circuit Product Summary I C) R DS(on)

TO-247-3L Inner Circuit Product Summary I C) R DS(on) Silicon Carbide Power MOSFET N-CHANNEL ENHANCEMENT MODE TO-247-3L Inner Circuit Product Summary V DS I D(@25 C) R DS(on) 1200V 20A 120mΩ Features u Low On-Resistance u Low Capacitance u Avalanche Ruggedness

More information

Dual N-Channel OptiMOS MOSFET

Dual N-Channel OptiMOS MOSFET Dual N-Channel OptiMOS MOSFET Features Dual N-channel OptiMOS MOSFET Optimized for high performance Buck converter Logic level (4.5V rated) 1% avalanche tested Qualified according to JEDEC 1) for target

More information

OptiMOS 2 Power-Transistor

OptiMOS 2 Power-Transistor BSC79N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for notebook DC/DC converters Qualified according to JEDEC 1) for target applications Product Summary

More information

OptiMOS TM Power-MOSFET

OptiMOS TM Power-MOSFET OptiMOS TM Power-MOSFET Features Optimized for high performance SMPS Integrated monolithic Schottky-like diode Very low on-resistance R DS(on) @ V GS =4.5 V 1% avalanche tested Superior thermal resistance

More information

OptiMOS TM 3 Power-Transistor

OptiMOS TM 3 Power-Transistor Type OptiMOS TM 3 Power-Transistor Features Optimized for dc-dc conversion N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Low on-resistance R DS(on) 15 C operating temperature BSZ12DN2NS3

More information

OptiMOS 2 Small-Signal-Transistor

OptiMOS 2 Small-Signal-Transistor OptiMOS Small-Signal-Transistor Features N-channel Enhancement mode Logic level (4.5V rated) Avalanche rated Product Summary V DS 3 V R DS(on),max V GS =1 V 16 mω V GS =4.5 V 8 I D 1.4 A Qualified according

More information

OptiMOS -T2 Power-Transistor Product Summary

OptiMOS -T2 Power-Transistor Product Summary OptiMOS -T2 Power-Transistor Product Summary V DS 6 V R DS(on),max 9. mω Features N-channel - Enhancement mode I D 5 A PG-TO252-3-11 AEC qualified MSL1 up to 26 C peak reflow 175 C operating temperature

More information

CoolMOS Power Transistor

CoolMOS Power Transistor CoolMOS Power Transistor Features Product Summary V DS @ T j,max 65 V Lowest figure-of-merit R ON xq g R DS(on),max @T j = 25 C.25 Ω Ultra low gate charge 6.6 Q g,typ Extreme dv/dt rated 26 nc High peak

More information

OptiMOS TM Power-MOSFET

OptiMOS TM Power-MOSFET BSC16N6NS OptiMOS TM Power-MOSFET Features Optimized for synchronous rectification 1% avalanche tested Superior thermal resistance N-channel Qualified according to JEDEC 1) for target applications Pb-free

More information

A I DM. W/ C V GS Gate-to-Source Voltage ± 16. Thermal Resistance Symbol Parameter Typ. Max. Units

A I DM. W/ C V GS Gate-to-Source Voltage ± 16. Thermal Resistance Symbol Parameter Typ. Max. Units V DSS 40 V V GS Max ± 6 V R DS(on) max (@V GS = V) 56 mω G 3 D PD - 96309A HEXFET Power MOSFET R DS(on) max (@V GS = 4.5V) Application(s) Load/ System Switch DC Motor Drive 78 mω S 2 Micro3 TM (SOT-23)

More information

OptiMOS P2 Small-Signal-Transistor

OptiMOS P2 Small-Signal-Transistor OptiMOS P Small-Signal-Transistor Features P-channel Enhancement mode Super Logic Level (.5V rated) Avalanche rated Qualified according to AEC Q % lead-free; RoHS compliant Product Summary V DS - V R DS(on),max

More information

OptiMOS TM -T2 Power-Transistor

OptiMOS TM -T2 Power-Transistor OptiMOS TM -T2 Power-Transistor Product Summary V DS 4 V R DS(on),max 7.2 mω I D 5 A Features Dual N-channel Logic Level Common Drain - Enhancement mode PG-TO252-5 AEC qualified MSL1 up to 26 C peak reflow

More information

N-channel TrenchMOS transistor

N-channel TrenchMOS transistor PSMN2-5W FEATURES SYMBOL QUICK REFERENCE DATA Trench technology Very low on-state resistance Fast switching Low thermal resistance g d s V DSS = 5 V I D = 73 A R DS(ON) 2 mω GENERAL DESCRIPTION PINNING

More information

SSF8NP60U. Main Product Characteristics: 600V V DSS. 0.73Ω (typ.) Features and Benefits: Description: Absolute max Rating:

SSF8NP60U. Main Product Characteristics: 600V V DSS. 0.73Ω (typ.) Features and Benefits: Description: Absolute max Rating: Main Product Characteristics: V DSS 600V R DS (on) 0.73Ω (typ.) I D 8A 1 Features and Benefits: TO-220 Marking and pin Assignment Schematic diagram High dv/dt and avalanche capabilities 100% avalanche

More information

OptiMOS -T2 Power-Transistor

OptiMOS -T2 Power-Transistor OptiMOS -T2 Power-Transistor Product Summary V DS 4 V R DS(on),max 7.3 mω Features N-channel - Enhancement mode AEC qualified I D 5 A PG-TO252-3-33 MSL up to 26 C peak reflow 75 C operating temperature

More information

OptiMOS -5 Power-Transistor

OptiMOS -5 Power-Transistor OptiMOS -5 Power-Transistor Product Summary V DS V R DS(on).5 m Features N-channel - Enhancement mode AEC qualified MSL up to 26 C peak reflow 75 C operating temperature I D 3 A P/G-HSOF-8- Tab 8 Tab Green

More information

OptiMOS TM Power-MOSFET

OptiMOS TM Power-MOSFET BSC18NE2LSI OptiMOS TM Power-MOSFET Features Optimized for high performance Buck converter Monolithic integrated Schottky like diode Very low on-resistance R DS(on) @ V GS =4.5 V 1% avalanche tested N-channel

More information

SIPMOS Power-Transistor

SIPMOS Power-Transistor SPB18P6P G SIPMOS Power-Transistor Features P-Channel Enhancement mode Avalanche rated Product Summary V DS -6 V R DS(on),max.13 Ω I D -18.6 A dv /dt rated 175 C operating temperature PG-TO63-3 Halogen-free

More information

OptiMOS TM -T2 Power-Transistor

OptiMOS TM -T2 Power-Transistor OptiMOS TM -T2 Power-Transistor Product Summary V DS 1 V R DS(on),max 6.7 mw Features N-channel - Normal Level - Enhancement mode AEC qualified I D 9 A PG-TO252-3-313 TAB MSL1 up to 26 C peak reflow 175

More information

OptiMOS Power-Transistor

OptiMOS Power-Transistor IPB8N6S2L-11 IPP8N6S2L-11, IPI8N6S2L-11 OptiMOS Power-Transistor Features N-channel Logic Level - Enhancement mode Automotive AEC Q11 qualified MSL1 up to 26 C peak reflow Product Summary V DS 55 V R DS(on),max

More information

CoolMOS Power Transistor

CoolMOS Power Transistor IPP9R1K2C3 CoolMOS Power Transistor Features Lowest figure-of-merit R ON x Q g Extreme dv/dt rated High peak current capability Qualified according to JEDEC 1) for target applications Pb-free lead plating;

More information

OptiMOS -P2 Power-Transistor Product Summary

OptiMOS -P2 Power-Transistor Product Summary IPB8P3P4L-4 OptiMOS -P2 Power-Transistor Product Summary V DS -3 V R DS(on) (SMD Version) 4.1 mω Features P-channel - Logic Level - Enhancement mode I D -8 A AEC qualified PG-TO263-3-2 PG-TO262-3-1 PG-TO22-3-1

More information

OptiMOS -T2 Power-Transistor

OptiMOS -T2 Power-Transistor OptiMOS -T2 Power-Transistor Product Summary V DS 4 V R DS(on),max (SMD version).8 mω Features N-channel - Enhancement mode I D 2 A PG-TO263-3-2 PG-TO262-3- PG-TO22-3- AEC qualified MSL up to 26 C peak

More information

P-Channel Enhancement Mode Field Effect Transistor PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS

P-Channel Enhancement Mode Field Effect Transistor PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS PRODUCT SUMMARY D V (BR)DSS R DS(ON) I D -4V 15mΩ -45A G 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (T A = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source

More information

Silicon carbide Power MOSFET 650 V, 90 A, 18 mω (typ., T J = 25 C) in an H²PAK-7 package. Order code V DS R DS(on) max. I D

Silicon carbide Power MOSFET 650 V, 90 A, 18 mω (typ., T J = 25 C) in an H²PAK-7 package. Order code V DS R DS(on) max. I D Datasheet Silicon carbide Power MOSFET 650 V, 90 A, 18 mω (typ., T J = 25 C) in an H²PAK-7 package TAB Features Order code V DS R DS(on) max. I D 1 H2PAK-7 7 SCTH90N65G2V-7 650 V 25 mω 90 A Very high operating

More information

OptiMOS -T Power-Transistor

OptiMOS -T Power-Transistor IPB35N2S3L-26 OptiMOS -T Power-Transistor Product Summary V DS 2 V R DS(on),max 26.3 mw Features OptiMOS - power MOSFET for automotive applications N-channel - Enhancement mode I D 35 A PG-TO263-3-2 Tab

More information

P-Channel Enhancement Mode Mosfet

P-Channel Enhancement Mode Mosfet WPM34 WPM34 P-Channel Enhancement Mode Mosfet Features Higher Efficiency Extending Battery Life Miniature SOT3-3 Surface Mount Package Super high density cell design for extremely low RDS (ON) http://www.willsemi.com

More information

OptiMOS -5 Power-Transistor

OptiMOS -5 Power-Transistor OptiMOS -5 Power-Transistor Product Summary V DS 8 V R DS(on).2 m Features N-channel - Enhancement mode AEC qualified I D 3 A H-PSOF-8- Tab MSL up to 26 C peak reflow 75 C operating temperature Green product

More information

OptiMOS 3 Power-Transistor

OptiMOS 3 Power-Transistor IPI2N15N3 G IPP2N15N3 G OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 15 V R DS(on),max 2 mw I D 5 A Very low on-resistance

More information