SPICE Modeling of STT-RAM for Resilient Design. Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU
|
|
- Augusta Chambers
- 6 years ago
- Views:
Transcription
1 SPICE odeling of STT-RA for Resilient Design Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU
2 OUTLINE Heterogeneous emory Design A Promising Candidate: STT-RA Fundamentals of STT-RA Previous approaches Hierarchical odeling Solution SPICE odel of STT-RA Equivalent Circuit odel Device Parameter odel STT-RA Single Cell Simulation Summary and Future Work
3 Trend of Technology Scaling Bulk/SOI OSFET Strained OSFET HKG OSFET G OSFET SRA Flash PC STT DRA FRA RRA Tremendous variety in memory physics, materials, structures, and devices! - 3 -
4 Read + Write Time Tremendous Diversity Performance STT-RA Advantages: Access time comparable to SRA Density comparable to DRA Low standby power High endurance (>10 16 ) STT-RA Cell Size (F 2 ) [R. Venkatesan, ISLPED 2012] Scalable to lower technology nodes Can be used for logic design - 4 -
5 STT-RA Fundamental emory Cell agnetic Tunnel Junction Bit Line TJ Word Line Source Line Parallel Low R => bit 0 Anti-Parallel High R => bit 1 agnetic Tunnel Junction (TJ) consists of thin insulating layer (Dielectric-gO) about ~1nm thick, sandwiched between two layers of ferromagnetic material. agnetization of one layer is fixed while that of other layer is free. Direction of magnetization angle in free layer governs the resistance of TJ. Resistance is translated to logical value of the data that is stored. Parallel state corresponds to bit 0 being stored and anti-parallel state corresponds to bit
6 LLG Equation d dt H d ( u ) ( u 0 2 ea ea s dt s K ) Zeeman (external) Zeeman energy tends to align the magnetization field with the applied field. Damping energy is the energy loss of the precession of magnetization. Anisotropic energy is responsible for self-alignment of magnetization along easy axis. u ea Damping (internal) γ rad s 1 T 1 gyromagnetic ratio μ 0 = 4π 10 7 N A 2 permeability constant K is anisotropy constant dependent on material Anisotropic (internal)
7 Numerical ethod Numerically solve 3D LLG equation Capture both static and transient behavior of magnetization Difficult implementation and low efficiency [J. B. Kammerer, TED 2010] - 7 -
8 acro odel Based on calculated switching (threshold) current J C0 = αγe st FL μ B g H ext ± H ani ± H d 2 J C = J C0 1 k BT E ln τ τ 0 Capture the relation of switching current amplitude and pulse width Cannot capture transient behavior and variation issues [J. D. Harms, TED 2010] - 8 -
9 Hierarchical emory odel ulti-level modeling for design analysis, optimization and path-finding / inverse path-finding Behavioral Structural/ Circuit Device Finite State achine Equivalent Circuit Compact odel (nominal) Process/ aterials Variations Temporal Shift - 9 -
10 SPICE odel cos sin sin 0 K dt d H dt d s s s ) ( ) ( 2 0 ea ea s s u u K dt d H dt d 3D 1D θ Equivalent Circuit
11 Equivalent Circuit odel 0 s H sin 180 θ (Degrees) 90 K sin cos 0 I decreasing 10.0n 15.0n 20.0n 25.0n Be able to simulate transient behavior Time (s) Easy implementation with SPICE components and Verilog-A models Differential equation is solved by SPICE simulator reducing computation time
12 Saturation agnetization ( s ) dθ s dt = γ μ dθ 0 s H sin θ + α s dt aterial and geometry dependent s D = S b 1 exp 3 s0 2D ch 1 3R 2D ch 1 D: diameter of TJ layer s0 : s of bulk ferromagnetic material c: a constant (0<c 1) depends on the interface h: atomic diameter S b : bulk solid-vapour transition entropy + γ K sin θ cos θ R: ideal gas constant [H.. Lu, J. Phys. D 2007]
13 agnetic Field (H) dθ s dt = γ μ dθ 0 s H sin θ + α s dt H = H ex + H 0 H ex is the external magnetic field generated by input current H 0 captures the asymmetric switching threshold + γ K sin θ cos θ H ex Ir 2r I 2r 2 0 r r r r 0 0 Ιr 2 2πr 0 Ι 2πr
14 agnetic Angle to Resistance (Degrees) R () R R P R AP n 15.0n 20.0n 25.0n Time (s) R = R P [ TR(1 cos θ)] R P = t ox F φa exp 1.025t ox φ [J. C. Slonczewski, Phys. Rev. B 2005, Y. Zhang, TED 2012] As θ approaches 180 o, R = R AP t ox Oxide thickness 0.85 nm F aterial parameter φ Potential barrier 0.4 ev A Area 3318 nm
15 Resistance () Voltage Dependence of TR Tunnel agnetoresistance (TR) is the resistance difference ratio of TJ of the two states. TR = R AP R P R P TR depends on the voltage across the TJ. TR TR V Vh 5000 SPICE odel acro odel [Y. Zhang, TED 2012] TR 0 is the TR ratio with 0 voltage. V h is the voltage as TR = 0.5 TR Voltage (mv)
16 odel Summary Equivalent Circuit: 0 s H sin K sin cos θ dθ s dt = γ μ dθ 0 s H sin θ + α s + γ K sin θ cos θ dt Device odels and Parameter Values (65nm) : s D = S b 1 exp 3 s0 2D ch 1 3R 2D ch 1 H 2 Ιr πr 2 0 H 0 R = R P [ TR(1 cos θ)] s0 D 4.94x10 5 A/m 65 nm c 1 h 0.24 nm S b /R 13 r 0 H nm 49 A/m TR TR V h R P TR V Vh 0.5 V 1.2 kω
17 Resistance () Resistance () Geometry Dependence t ox = 0.85nm, 1nm, 1.15nm 1500 r = 30nm, 32.5nm, 35nm Time (ns) Time (ns) This model captures the transition behavior under process variation
18 Temperature Dependence Resistance sin (λt) R T = R(0) λt R(0) is the resistance at T=0K λ = πt oxk ћ 2m e e t ox is oxide thickness, k is Boltzmann constant, ћ is reduced plank constant, m e is electron mass. [. El Baraji, J. Appl. Phys. 2009] agnetic field Thermal fluctuating field H fluc [Y. Zhang, ICCAD 2011]
19 Finite Element ethod agnetic field being function of radius r, the field is nonuniform across TJ causing different switching of magnetization angle. Finite element method helps to capture the non-uniform distribution of magnetic field
20 Resistance () Finite Element Simulations 2500 Simulation time Elements 1.72 s 8 Elements 4.01 s Finite Elements Time (ns) 8 Finite Elements Time (ns) For accurate and fast simulation, we choose 8 elements in the simulation. Increasing number of finite element for simulation increases simulation time with marginal improvement in accuracy
21 Normalized Resistance odel Validation µ µ µ µ 400.0µ 600.0µ Current (A) [Z. Diao, J. Phys. 2007] Hysteresis effect predicted by model validated by experimental data for two different TJs
22 Simulation Setup Bit Line 0 s H sin θ Word Line K sin cos Source Line 8X Finite Elements Read operation: current lower than critical value is applied to TJ to determine its resistance state. During write operation, BL and SL are charged to opposite values depending on bit value that is to be stored. For write-0, BL=V dd, SL=0V; write-1, BL=0V and SL=V dd
23 Simulation Results Evaluation of STT-RA performance with proposed model using 10ns pulse. Write energy for single cell 0 -> pj 1 -> pj Based on the proposed SPICE model, cell level parameters such as resistance, current and geometry dependent variables can be obtained. Using above parameters, a system level memory simulator (CACTI) evaluates memory access time, cycle time, area, leakage, and dynamic power for entire architecture
24 Summary and Future Work SPICE model of STT-RA Hierarchical modeling approach Equivalent circuit model Geometry dependence of model parameters Next step: Validation with silicon data Variability and reliability effects Implementation into multi-level memory design tools Adaptive design techniques: R/W, ECC, etc. Integration of heterogeneous memory devices
A Universal Memory Model for Design Exploration. Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU
A Universal Memory Model for Design Exploration Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU Universal Memory Modeling because there is no universal memory device! Modeling needs in
More informationPerpendicular MTJ stack development for STT MRAM on Endura PVD platform
Perpendicular MTJ stack development for STT MRAM on Endura PVD platform Mahendra Pakala, Silicon Systems Group, AMAT Dec 16 th, 2014 AVS 2014 *All data in presentation is internal Applied generated data
More informationFrom Spin Torque Random Access Memory to Spintronic Memristor. Xiaobin Wang Seagate Technology
From Spin Torque Random Access Memory to Spintronic Memristor Xiaobin Wang Seagate Technology Contents Spin Torque Random Access Memory: dynamics characterization, device scale down challenges and opportunities
More informationA Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies
A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies Model download website: mtj.umn.edu Jongyeon Kim 1, An Chen 2, Behtash Behin-Aein 2, Saurabh Kumar 1,
More informationMagnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY
Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY Magnetic Tunnel Junctions (MTJs) Structure High density memory
More informationLecture 6 NEW TYPES OF MEMORY
Lecture 6 NEW TYPES OF MEMORY Memory Logic needs memory to function (efficiently) Current memories Volatile memory SRAM DRAM Non-volatile memory (Flash) Emerging memories Phase-change memory STT-MRAM (Ferroelectric
More informationA Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node
A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node U.K. Klostermann 1, M. Angerbauer 1, U. Grüning 1, F. Kreupl 1, M. Rührig 2, F. Dahmani 3, M. Kund 1, G. Müller 1 1 Qimonda
More informationThis document is an author-formatted work. The definitive version for citation appears as:
This document is an author-formatted work. The definitive version for citation appears as: A. Roohi, R. Zand, D. Fan and R. F. DeMara, "Voltage-based Concatenatable Full Adder using Spin Hall Effect Switching,"
More informationMTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application
2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112 MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application Takahiro Hanyu 1,3, S. Matsunaga 1, D. Suzuki
More informationPage 1. A portion of this study was supported by NEDO.
MRAM : Materials and Devices Current-induced Domain Wall Motion High-speed MRAM N. Ishiwata NEC Corporation Page 1 A portion of this study was supported by NEDO. Outline Introduction Positioning and direction
More informationAuthor : Fabrice BERNARD-GRANGER September 18 th, 2014
Author : September 18 th, 2014 Spintronic Introduction Spintronic Design Flow and Compact Modelling Process Variation and Design Impact Semiconductor Devices Characterisation Seminar 2 Spintronic Introduction
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationSPIN TRANSFER TORQUES IN HIGH ANISOTROPY MAGNETIC NANOSTRUCTURES
CRR Report Number 29, Winter 2008 SPIN TRANSFER TORQUES IN HIGH ANISOTROPY AGNETIC NANOSTRUCTURES Eric Fullerton 1, Jordan Katine 2, Stephane angin 3, Yves Henry 4, Dafine Ravelosona 5, 1 University of
More informationFabrication and Measurement of Spin Devices. Purdue Birck Presentation
Fabrication and Measurement of Spin Devices Zhihong Chen School of Electrical and Computer Engineering Birck Nanotechnology Center, Discovery Park Purdue University Purdue Birck Presentation zhchen@purdue.edu
More informationNRAM: High Performance, Highly Reliable Emerging Memory
NRAM: High Performance, Highly Reliable Emerging Memory Sheyang Ning,2, Tomoko Ogura Iwasaki, Darlene Viviani 2, Henry Huang 2, Monte Manning 2, Thomas Rueckes 2, Ken Takeuchi Chuo University 2 Nantero
More information9. Spin Torque Majority Gate
eyond MOS computing 9. Spin Torque Majority Gate Dmitri Nikonov Thanks to George ourianoff Dmitri.e.nikonov@intel.com 1 Outline Spin majority gate with in-pane magnetization Spin majority gate with perpendicular
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationWouldn t it be great if
IDEMA DISKCON Asia-Pacific 2009 Spin Torque MRAM with Perpendicular Magnetisation: A Scalable Path for Ultra-high Density Non-volatile Memory Dr. Randall Law Data Storage Institute Agency for Science Technology
More informationarxiv: v1 [physics.app-ph] 1 May 2017
Magnetic Skyrmions for Cache Memory Mei-Chin Chen 1 and Kaushik Roy 1 1 School of Electrical and Computer Engineering, Purdue University, West Lafayette, 47906, USA * chen1320@purdue.edu ABSTRACT arxiv:1705.01095v1
More informationPS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability Analysis Method
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability Analysis Method ujie en, Yaojun Zhang, Yiran Chen Yu ang Yuan Xie University of Pittsburgh Tsinghua University Pennsylvania State University
More informationEmerging spintronics-based logic technologies
Center for Spintronic Materials, Interfaces, and Novel Architectures Emerging spintronics-based logic technologies Zhaoxin Liang Meghna Mankalale Jian-Ping Wang Sachin S. Sapatnekar University of Minnesota
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationMRAM: Device Basics and Emerging Technologies
MRAM: Device Basics and Emerging Technologies Matthew R. Pufall National Institute of Standards and Technology 325 Broadway, Boulder CO 80305-3337 Phone: +1-303-497-5206 FAX: +1-303-497-7364 E-mail: pufall@boulder.nist.gov
More informationLow Energy Spin Transfer Torque RAM (STT-RAM / SPRAM) Zach Foresta April 23, 2009
Low Energy Spin Transfer Torque RAM (STT-RAM / SPRAM) Zach Foresta April 23, 2009 Overview Background A brief history GMR and why it occurs TMR structure What is spin transfer? A novel device A future
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More information7. Basics of Magnetization Switching
Beyond CMOS computing 7. Basics of Magnetization Switching Dmitri Nikonov Dmitri.e.nikonov@intel.com 1 Outline Energies in a nanomagnet Precession in a magnetic field Anisotropies in a nanomagnet Hysteresis
More informationCorrelations between spin accumulation and degree of time-inverse breaking for electron gas in solid
Correlations between spin accumulation and degree of time-inverse breaking for electron gas in solid V.Zayets * Spintronic Research Center, National Institute of Advanced Industrial Science and Technology
More informationSpin pumping in magnetic trilayer structures with an MgO barrier Supplementary Information.
Spin pumping in magnetic trilayer structures with an MgO barrier Supplementary Information. A. A. Baker, 1, 2 A. I. Figueroa, 2 D. Pingstone, 3 V. K. Lazarov, 3 G. van der Laan, 2 and 1, a) T. Hesjedal
More informationNonvolatile CMOS Circuits Using Magnetic Tunnel Junction
November 3-4, 2011 Berkeley, CA, USA Nonvolatile CMOS Circuits Using Magnetic Tunnel Junction Hideo Ohno 1,2 1 Center for Spintronics Integrated Systems, Tohoku University, Japan 2 Laboratory for Nanoelectronics
More informationMSE 7025 Magnetic Materials (and Spintronics)
MSE 7025 Magnetic Materials (and Spintronics) Lecture 14: Spin Transfer Torque And the future of spintronics research Chi-Feng Pai cfpai@ntu.edu.tw Course Outline Time Table Week Date Lecture 1 Feb 24
More informationA Robustness Optimization of SRAM Dynamic Stability by Sensitivity-based Reachability Analysis
ASP-DAC 2014 A Robustness Optimization of SRAM Dynamic Stability by Sensitivity-based Reachability Analysis Yang Song, Sai Manoj P. D. and Hao Yu School of Electrical and Electronic Engineering, Nanyang
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationSpin orbit torque driven magnetic switching and memory. Debanjan Bhowmik
Spin orbit torque driven magnetic switching and memory Debanjan Bhowmik Spin Transfer Torque Fixed Layer Free Layer Fixed Layer Free Layer Current coming out of the fixed layer (F2) is spin polarized in
More informationNew Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM)
New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM) Hiroaki Yoda Corporate Research & Development Center, Toshiba
More informationCurrent-driven Magnetization Reversal in a Ferromagnetic Semiconductor. (Ga,Mn)As/GaAs/(Ga,Mn)As Tunnel Junction
Current-driven Magnetization Reversal in a Ferromagnetic Semiconductor (Ga,Mn)As/GaAs/(Ga,Mn)As Tunnel Junction D. Chiba 1, 2*, Y. Sato 1, T. Kita 2, 1, F. Matsukura 1, 2, and H. Ohno 1, 2 1 Laboratory
More informationAN ABSTRACT OF THE THESIS OF
AN ABSTRACT OF THE THESIS OF Linda Engelbrecht for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on March 18, 2011. Title: Modeling Spintronics Devices in Verilog-A
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationPhysics 2020 Exam 2 Constants and Formulae
Physics 2020 Exam 2 Constants and Formulae Useful Constants k e = 8.99 10 9 N m 2 /C 2 c = 3.00 10 8 m/s ɛ = 8.85 10 12 C 2 /(N m 2 ) µ = 4π 10 7 T m/a e = 1.602 10 19 C h = 6.626 10 34 J s m p = 1.67
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationAn Overview of Spin-based Integrated Circuits
ASP-DAC 2014 An Overview of Spin-based Integrated Circuits Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafiné Ravelosona, and Claude Chappert
More information2 Title: "Ultrathin flexible electronic device based on tunneling effect: a flexible ferroelectric tunnel
Electronic Supplementary Material (ESI) for Journal of Materials Chemistry C. This journal is The Royal Society of Chemistry 208 Supplementary information 2 Title: "Ultrathin flexible electronic device
More informationCURRENT-INDUCED MAGNETIC DYNAMICS IN NANOSYSTEMS
CURRENT-INDUCED MAGNETIC DYNAMICS IN NANOSYSTEMS J. Barna Department of Physics Adam Mickiewicz University & Institute of Molecular Physics, Pozna, Poland In collaboration: M Misiorny, I Weymann, AM University,
More informationStrong-electric-field effects and antenna resonances in single-wall carbon nanotube films
Strong-electric-field effects and antenna resonances in single-wall carbon nanotube films Dalius Seliuta Center for Physical Sciences and Technology, Vilnius, Lithuania Liudas Subačius, Irmantas Kašalynas,
More informationSize-dependent Metal-insulator Transition Random Materials Crystalline & Amorphous Purely Electronic Switching
Nanometallic RRAM I-Wei Chen Department of Materials Science and Engineering University of Pennsylvania Philadelphia, PA 19104 Nature Nano, 6, 237 (2011) Adv Mater,, 23, 3847 (2011) Adv Func Mater,, 22,
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal
More informationHandout 10: Inductance. Self-Inductance and inductors
1 Handout 10: Inductance Self-Inductance and inductors In Fig. 1, electric current is present in an isolate circuit, setting up magnetic field that causes a magnetic flux through the circuit itself. This
More informationAdvanced Flash and Nano-Floating Gate Memories
Advanced Flash and Nano-Floating Gate Memories Mater. Res. Soc. Symp. Proc. Vol. 1337 2011 Materials Research Society DOI: 10.1557/opl.2011.1028 Scaling Challenges for NAND and Replacement Memory Technology
More informationSUPPLEMENTARY INFORMATION
SUPPLEMENTARY INFORMATION doi: 10.1038/nPHYS147 Supplementary Materials for Bias voltage dependence of perpendicular spin-transfer torque in asymmetric MgO-based magnetic tunnel junctions Se-Chung Oh 1,
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationTime resolved transport studies of magnetization reversal in orthogonal spin transfer magnetic tunnel junction devices
Invited Paper Time resolved transport studies of magnetization reversal in orthogonal spin transfer magnetic tunnel junction devices Georg Wolf a, Gabriel Chaves-O Flynn a, Andrew D. Kent a, Bartek Kardasz
More informationFloating Gate Devices: Operation and Compact Modeling
Floating Gate Devices: Operation and Compact Modeling Paolo Pavan (1), Luca Larcher (1) and Andrea MarmirolI (2) (1) Università di Modena e Reggio Emilia, Via Fogliani, 1 42100 Reggio Emilia (Italy) -
More informationCenter for Spintronic Materials, Interfaces, and Novel Architectures. Voltage Controlled Antiferromagnetics and Future Spin Memory
Center for Spintronic Materials, Interfaces, and Novel Architectures Voltage Controlled Antiferromagnetics and Future Spin Memory Maxim Tsoi The University of Texas at Austin Acknowledgments: H. Seinige,
More informationμ (vector) = magnetic dipole moment (not to be confused with the permeability μ). Magnetism Electromagnetic Fields in a Solid
Magnetism Electromagnetic Fields in a Solid SI units cgs (Gaussian) units Total magnetic field: B = μ 0 (H + M) = μ μ 0 H B = H + 4π M = μ H Total electric field: E = 1/ε 0 (D P) = 1/εε 0 D E = D 4π P
More informationMaria-Alexandra PAUN, PhD
On the modelisation of the main characteristics of SOI Hall cells by three-dimensional physical simulations Maria-Alexandra PAUN, PhD Visiting Researcher High Voltage Microelectronics and Sensors (HVMS)
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationStatistical Analysis of Random Telegraph Noise in Digital Circuits
Nano-scale Integrated Circuit and System (NICS) Laboratory Statistical Analysis of Random Telegraph Noise in Digital Circuits Xiaoming Chen 1, Yu Wang 1, Yu Cao 2, Huazhong Yang 1 1 EE, Tsinghua University,
More informationAdaptive Compact Magnetic Tunnel Junction Model
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014 3883 Adaptive Compact Magnetic Tunnel Junction Model Mohammad Kazemi, Student Member, IEEE, Engin Ipek, Member, IEEE, and Eby G. Friedman,
More informationLow Energy SPRAM. Figure 1 Spin valve GMR device hysteresis curve showing states of parallel (P)/anti-parallel (AP) poles,
Zachary Foresta Nanoscale Electronics 04-22-2009 Low Energy SPRAM Introduction The concept of spin transfer was proposed by Slonczewski [1] and Berger [2] in 1996. They stated that when a current of polarized
More informationCompact Models for Giga-Scale Memory System. Mansun Chan, Dept. of ECE, HKUST
Compact Models for Giga-Scale Memory System Mansun Chan, Dept. of ECE, HKUST Memory System Needs BL0 Bitline Precharge Circuits BLn WL Read Address Address Decoder H.-S. P. Wong, Stanford Timing Circuits
More informationLouisiana State University Physics 2102, Exam 3 April 2nd, 2009.
PRINT Your Name: Instructor: Louisiana State University Physics 2102, Exam 3 April 2nd, 2009. Please be sure to PRINT your name and class instructor above. The test consists of 4 questions (multiple choice),
More informationSpin Switch: Model built using Verilog-A Spintronics Library
Spin Switch: Model built using Verilog-A Spintronics Library Samiran Ganguly, Kerem Y. Camsari, Supriyo Datta Purdue University August, 2014 Abstract We present a circuit/compact model for the Spin Switch
More informationLeveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM
Leveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM Seyed Mohammad Seyedzadeh, Rakan Maddah, Alex Jones, Rami Melhem University of Pittsburgh Intel Corporation seyedzadeh@cs.pitt.edu,
More informationBit -Line. Bit -Line. 2.1 Concept. Local Word Line. Global Word Line. Sub Bit-Line. Figure 1. Divided Bit-Line Approach, M = Theoretical Basis
ow Power SRA Design using Hierarchical Divided Bit-ine Approach Ashish Karandikar y Intel orporation, Santa lara, A 95052, USA E-mail: akarand@td2cad.intel.com Keshab K. Parhi Dept. of Electrical and omputer
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationQ. 1 Q. 25 carry one mark each.
GATE 5 SET- ELECTRONICS AND COMMUNICATION ENGINEERING - EC Q. Q. 5 carry one mark each. Q. The bilateral Laplace transform of a function is if a t b f() t = otherwise (A) a b s (B) s e ( a b) s (C) e as
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationAnnouncements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationMagnetism and Magnetic Switching
Magnetism and Magnetic Switching Robert Stamps SUPA-School of Physics and Astronomy University of Glasgow A story from modern magnetism: The Incredible Shrinking Disk Instead of this: (1980) A story from
More informationConventional Paper I (a) (i) What are ferroelectric materials? What advantages do they have over conventional dielectric materials?
Conventional Paper I-03.(a) (i) What are ferroelectric materials? What advantages do they have over conventional dielectric materials? (ii) Give one example each of a dielectric and a ferroelectric material
More informationarxiv: v1 [cond-mat.mtrl-sci] 28 Jul 2008
Current induced resistance change of magnetic tunnel junctions with ultra-thin MgO tunnel barriers Patryk Krzysteczko, 1, Xinli Kou, 2 Karsten Rott, 1 Andy Thomas, 1 and Günter Reiss 1 1 Bielefeld University,
More informationSpin Torque and Magnetic Tunnel Junctions
Spin Torque and Magnetic Tunnel Junctions Ed Myers, Frank Albert, Ilya Krivorotov, Sergey Kiselev, Nathan Emley, Patrick Braganca, Greg Fuchs, Andrei Garcia, Ozhan Ozatay, Eric Ryan, Jack Sankey, John
More informationMagnetic domain theory in dynamics
Chapter 3 Magnetic domain theory in dynamics Microscale magnetization reversal dynamics is one of the hot issues, because of a great demand for fast response and high density data storage devices, for
More informationEE650R: Reliability Physics of Nanoelectronic Devices Lecture 18: A Broad Introduction to Dielectric Breakdown Date:
EE650R: Reliability Physics of Nanoelectronic Devices Lecture 18: A Broad Introduction to Dielectric Breakdown Date: Nov 1, 2006 ClassNotes: Jing Li Review: Sayeef Salahuddin 18.1 Review As discussed before,
More informationAdvanced Topics In Solid State Devices EE290B. Will a New Milli-Volt Switch Replace the Transistor for Digital Applications?
Advanced Topics In Solid State Devices EE290B Will a New Milli-Volt Switch Replace the Transistor for Digital Applications? August 28, 2007 Prof. Eli Yablonovitch Electrical Engineering & Computer Sciences
More informationLow-power non-volatile spintronic memory: STT-RAM and beyond
IOP PUBLISHING JOURNAL OF PHYSICS D: APPLIED PHYSICS J. Phys. D: Appl. Phys. 46 (2013) 074003 (10pp) doi:10.1088/0022-3727/46/7/074003 Low-power non-volatile spintronic memory: STT-RAM and beyond K L Wang,
More informationPHY 114 Summer Midterm 2 Solutions
PHY 114 Summer 009 - Midterm Solutions Conceptual Question 1: Can an electric or a magnetic field, each constant in space and time, e used to accomplish the actions descried elow? Explain your answers.
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationMODELING OF THE ADVANCED SPIN TRANSFER TORQUE MEMORY: MACRO- AND MICROMAGNETIC SIMULATIONS
MODELING OF THE ADVANCED SPIN TRANSFER TORQUE MEMORY: MACRO- AND MICROMAGNETIC SIMULATIONS Alexander Makarov, Viktor Sverdlov, Dmitry Osintsev, Josef Weinbub, and Siegfried Selberherr Institute for Microelectronics
More informationLecture 10 Charge Carrier Mobility
Lecture 10 Charge Carrier Mobility Schroder: Chapter 8 1/64 Announcements Homework 2/6: Is online now. Due Today. I will return it next monday (7 th May). Midterm Exam: Friday May 4 th at 10:00am in STAG113
More informationCharge fluctuators, their temperature and their response to sudden electrical fields
Charge fluctuators, their temperature and their response to sudden electrical fields Outline Charge two-level fluctuators Measuing noise with an SET Temperature and bias dependence of the noise TLF temperature
More informationarxiv: v1 [cond-mat.mtrl-sci] 7 Nov 2012
Spin torque switching in perpendicular films at finite temperature, HP-13 Ru Zhu and P B Visscher arxiv:12111665v1 [cond-matmtrl-sci] 7 Nov 212 MINT Center and Department of Physics and Astronomy University
More informationWARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays Mahadevan Gomathisankaran Iowa State University gmdev@iastate.edu Akhilesh Tyagi Iowa State University tyagi@iastate.edu ➀ Introduction
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More information( (Chapter 5)(Magnetism and Matter)
Additional Exercises Question 5.16: Answer the following questions: (a) Why does a paramagnetic sample display greater magnetisation (for the same magnetising field) when cooled? (b) Why is diamagnetism,
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationALCT Measurement Principles
Current-based Measurements At a basic electronics level, a liquid crystal sample cell may be modeled as a combination dynamic capacitor and resistor in parallel. As such, the majority of ALCT measurements
More informationQuantum Size Effect of Two Couple Quantum Dots
EJTP 5, No. 19 2008) 33 42 Electronic Journal of Theoretical Physics Quantum Size Effect of Two Couple Quantum Dots Gihan H. Zaki 1), Adel H. Phillips 2) and Ayman S. Atallah 3) 1) Faculty of Science,
More informationMagnetic bubblecade memory based on chiral domain walls
Magnetic bubblecade memory based on chiral domain walls Kyoung-Woong Moon, Duck-Ho Kim, Sang-Cheol Yoo, Soong-Geun Je, Byong Sun Chun, Wondong Kim, Byoung-Chul Min, Chanyong Hwang & Sug-Bong Choe 1. Sample
More informationSUPPLEMENTARY INFORMATION
Systematic shift caused by trap asymmetry The major systematic correction in the reported cyclotron frequency ratio comparison of an antiproton at ν c, p and a negatively charged hydrogen ion (H ) at ν
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationCM300DY-24A. APPLICATION AC drive inverters & Servo controls, etc CM300DY-24A. IC...300A VCES V Insulated Type 2-elements in a pack
CM00DY-A CM00DY-A IC...00A CES... 0 Insulated Type -elements in a pack APPLICATION AC drive inverters & Servo controls, etc OUTLINE DRAWING & CIRCUIT DIAGRAM Dimensions in mm 8 9±0. -M6 NUTS G +1.0 0 0.
More information250 P C = 25 C Power Dissipation 160 P C = 100 C Power Dissipation Linear Derating Factor
PDP TRENCH IGBT PD - 9634 IRG6B33UDPbF Features l Advanced Trench IGBT Technology l Optimized for Sustain and Energy Recovery Circuits in PDP Applications l Low V CE(on) and Energy per Pulse (E PULSE TM
More informationFluctuation Theorem for a Small Engine and Magnetization Switching by Spin Torque
Fluctuation Theorem for a Small Engine and Magnetization Switching by Spin Torque Yasuhiro Utsumi Tomohiro Taniguchi Mie Univ. Spintronics Research Center, AIST YU, Tomohiro Taniguchi, PRL 114, 186601,
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar
More informationModeling and Simulation of Variations in Nano-CMOS Design. Yun Ye
Modeling and Simulation of Variations in Nano-CMOS Design by Yun Ye A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Approved April 2011 by the Graduate
More informationSaroj P. Dash. Chalmers University of Technology. Göteborg, Sweden. Microtechnology and Nanoscience-MC2
Silicon Spintronics Saroj P. Dash Chalmers University of Technology Microtechnology and Nanoscience-MC2 Göteborg, Sweden Acknowledgement Nth Netherlands University of Technology Sweden Mr. A. Dankert Dr.
More informationDesign for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
More informationSolutions to PHY2049 Exam 2 (Nov. 3, 2017)
Solutions to PHY2049 Exam 2 (Nov. 3, 207) Problem : In figure a, both batteries have emf E =.2 V and the external resistance R is a variable resistor. Figure b gives the electric potentials V between the
More information