Low Energy SPRAM. Figure 1 Spin valve GMR device hysteresis curve showing states of parallel (P)/anti-parallel (AP) poles,

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1 Zachary Foresta Nanoscale Electronics Low Energy SPRAM Introduction The concept of spin transfer was proposed by Slonczewski [1] and Berger [2] in They stated that when a current of polarized electrons enters a ferro-magnet there is generally a transfer of angular momentum between propagating electrons and the magnetization of the film [3]. This concept evolved from giant magneto-resistance (GMR) and tunneling magneto-resistance (TMR) devices that predated its conception therefore to understand the future technology we will look into the past. Background In 1988 Albert Fert and Peter Grünberg working independently both discovered GMR (for which they received the 2007 Nobel Prize in Physics). Figure 1 below illustrates a typical spin valve GMR device which has been used since 1991 and is commonly utilized in magnetic recording devices such as read heads for hard disks. The device consists of two magnetic layers with a nonmagnetic layer in between. In this configuration there is a pinned layer in which the field direction does not change and a free layer in which the field is free to change direction. The pinned layer acts as a reference never changing while the free layer can vary yielding states of parallel (P) and anti-parallel (AP) magnetic poles. The fundamental idea of this device is that when it enters into the P-state the resistance is minimal and when switched to the AP-state the resistance is at its maximum. Using this difference in resistance, devices can differentiate between a 1 and 0 in magnetic memory discs by reading out the voltage through the spin valve. Figure 1 below illustrates the hysteresis curve going from AP to P; note the scale denoting the magnitude of the field needed to switch the orientation of the pinned layer. [4]. Figure 1 Spin valve GMR device hysteresis curve showing states of parallel (P)/anti-parallel (AP) poles, To keep the spin valve GMR device operating properly the pinned layer must stay at one particular orientation. The pinned layer is typically made so by connecting to an anti-ferromagnetic (AF) 1

2 layer. The AF layer causes the ferro-magnetic (FM) layer below it to fix its pole direction due to the interface induced exchange-biased effect. The AF layer has its own preferential magnetic direction called the easy axis which interacts with the FM layer causing its pole to align. The exchange-biased effect essentially causes a shift in the magnetic field needed to induce pole switching (in figure 1 above this value is ). Materials suitable for AF layer must have high Neel Temperature, large magnetocrystalline anisotropy and good chemical and structural compatibility with the FM film layer. The Neel Temperature is a parameter which dictates the critical point temperature at which the AF material will stop having a preferred magnetic direction and become paramagnetic (i.e. losing magnetization in absence of field). Magneto-crystalline anisotropy refers to the amount of energy needed to align the magnetization of a crystalline material to another direction. Therefore the higher the Magnetocrystalline anisotropy the greater the magnetic field needed to switch magnetization directions. Common exchange bias materials used for AF layers in these GMR devices are anti-ferromagnetic oxides (NiO, CoO) and inter-metallic alloys (FeMn, NiMn, IrMn). Why GMR occurs The physical characteristics of a common GMR device physics were seen above, but what are the physical principles governing this GMR effect? Earlier it was seen that when in a magnetic field the poles on the free FM layers of the GMR device would line up with the orientation, then a current is run perpendicular through the device layers and a resistance change is observed. The cause for this resistance change lies in the principal of electron scattering. As the Stern-Gerlach experiment (seen below in figure 2) in 1922 illustrated, electrons had quantized angular momentum. In the experiment silver atoms were sent through an inhomogeneous magnetic field, the expected result was that the particles would create a smear impact on the screen showing that there was an infinite set of possible angular momentum states. On the contrary though, the experiment yielded two dots on the screen which lead to the understanding of the intrinsic angular momentum (S) and the spin quantum number ( ). They discovered electrons had an S = and = ±. This discovery led to the understanding of electrical resistance being the scattering of electrons due to density of opposing spin states. The probability of scattering depends on the number of available quantum states for the electron to scatter into, which depends strongly on the relative direction of the electron's spin and the magnetic field inside the FM layer. Figure 2 Stern-Gerlach experiment circa

3 Figure 3 below shows the GMR effect in the P and AP states. For the parallel state and up spin electron experiences no scattering due to a lack of available states, whereas the anti-parallel state scatters both the up and down spin electrons. Since the flow of electrons is impeded by this scattering effect there is a perceived electrical resistance (R) for each state; as I decreases R must necessarily increase for a constant voltage. Since the rate of electron transport is less in the APstate the resistance is higher than that of the P-state. Figure 3 P and AP states for a GMR device, the P-state experiences 50% less scattering Spin Transfer RAM s (STT-RAM or SPRAM) Components SPRAM s configuration is similar to that of the spin valve GMR such that it depends on a tri-layer of FM/Insulator (in GMR this layer is a nonmagnetic)/fm interface. Main differences in operation will be discussed in the novel device section, but in general SPRAM devices operate using current to switch the magnetic orientation instead of magnetic fields via a mechanism called spin transfer. The insulator of this device needs to be necessarily thin (~1nm) for tunneling to occur. The spin is transferred from ferromagnetic layers via preservation of the spin momentum through the insulator region. The greater the thickness of this layer the more the GMR effect is reduced and more current is needed to get the same results. Why Co/MgO/Co? SPRAM uses the principle of tunneling magneto-resistance (TMR), which in application makes use of the same principles as that of GMR with the exception of using magnetic fields induced by current for pole switching; SPRAM utilizes the same TMR structures but has a different means of switching the pole states. Most spin transfer torque devices use a variant of Cobalt (Co)/ Magnesium oxide (MgO)/ Cobalt tri-layer. In the next section we will discuss the reasons why this structure provides better results than pre-existing ones and how they were developed. 3

4 Figure 4 Periodic table highlighting the elements used for TMR devices in SPRAM In Neville Mott developed a model for electrical resistances of the ferromagnetic transition-metals, in which he stated that the 4s electrons carry the current while the 3d electrons at the Fermi level act as localized scatterers [5]. Cobalt is a ferromagnetic transition-metal with electron configuration where the 3d level is missing three electrons; it is also good to note that Fe is another good element for use in GMR/TMR devices due to its missing four electrons in the 3d level. As figure 5 below shows the spin density at the Fermi Energy for Co is predominantly minority spin (spin down) in the 3d level. This means the majority spin (spin up) in this level is already filled (therefore Co is a spin up material). Both Fert and Grünberg took advantage of this discrepancy of spin states in the crucial 3d level and realized they could grow a sandwich of two such materials (aligned to have opposite pole directions) between an non-magnetic layer and by applying a magnetic field parallelize the configuration resulting in GMR. GMR devices used a non-magnetic metal layer, but when Tunneling Magneto-resistance (TMR) was discovered it was found out both theoretically and experimentally that using an insulating layer of manganese oxide (MgO) provided far greater differences in resistance between states on the order of 200% [6]. Figure 5 - Spin-projected densities of states vs. (from Fermi Energy) for Co, [7]. TMR was discovered by Michel Julliere in 1975 using Fe/Germanium (Ge)/Fe yielding GMR type results with resistance differences on the order of 14%. Julliere s work was mostly disregarded due to 4

5 the need for low temperature (4.2 Kelvin) operation to achieve his TMR. It was twenty years later when room temperature TMR was discovered. In TMR devices instead of applying a magnetic field directly, one is induced via a current which does the pole switching. Additionally, TMR devices use tunneling of current to achieve resistance reading providing much higher changes in resistances between states. In 1996 and 2001 room temperature TMR was discovered and a theoretical change in resistance of 1000% was predicted [6]. This percentage resistance change is known as the TMR ratio with the formula below. The reason for this incredible jump in resistance can be attributed to the MgO insulating layer. Manganese oxide has a crystalline structure, as seen in figure 6 below, which allows for far greater conservation of angular momentum in electron transport, prior to this amorphous structures such as alumina were used; MgO has a cubic crystal structure with sides of length Angstroms. A Novel Device Figure 6 cubic crystal structure of MgO conserves the momentum of the traveling electron The motivation behind building a SPRAM memory device lies in the need for a non-volatile universal memory which can provide instant-on processing, fast read/write times, large memory to area ratio, and uses low energy. A universal memory such as the one illustrated in figure 7 below has the possibility to replace both RAM and ROM. A group [8] developed a 1.8 V 2Mb SPRAM chip using a 2µm logic process with an MgO tunneling barrier TMR memory cell. This device has its advantages of fast read/write times as well as the potential for low energy instant ON operation, but issues of accidental writing while reading make SPRAM difficult to control. Figure 7 a diagram showing the potential of universal RAM such as SPRAM, ROM/RAM is replaced. 5

6 The layout of this memory structure is seen below in figure 8 for both P and AP states. The device consists of a Bit Line (BL), TMR device, Word Line (WL), and Source Line (SL). The figure also shows the equivalent circuit diagram with a transistor and a two state resistor. The transistor or the WL controls the state (on/off) of current flow into or out of the Source Line which changes the resistor to P and AP states respectively. The BL is where (depending on the state) a 1 or a 0 is read. Figure 8 a) layout of one Bit of SPRAM memory b) Electric circuit equivalent The process of writing is straightforward the following is an example of how to write a 1 and 0. In figure 9a below the process for writing a 0 is shown. To start writing a 0 current flows from BL to SL therefore electrons are tunneled from SL to BL. The electron enters the pinned region where its spin is polarized to the direction of the field and then tunnels through the MgO barrier into the free layer where the preferred magnetization under goes a torque due to the momentum change from electron spin polarization. Eventually when the threshold current is exceeded the free layer becomes parallel with the pinned layer resulting in lower resistance and a 0 for memory. The process for writing a 1 is similar, but with current going from SL to BL and reflected electrons causing the torque. Reflection of electrons occurs when an electron of opposing spin enters the free layer. Once again when the current exceeds the free layer becomes anti-parallelized with the pinned layer. Note both and are determined by materials and structure of TMR device and are directly proportional to the area of the TMR device (i.e. means ). Figure 9 - a) writing a 0 (parallelizing), b) writing a 1 (anti-parallelizing) Now we come to one of the major pitfalls of this device, reading data. Reading data is simple in theory because it involves the same processes involved in writing data with exception of reaching the critical current for pole shifting. Reading works by sensing differences in. The only difference is that a lower amount of current is used in order not to mistakenly write while reading. As seen in figure 6

7 10 below there are two directions for reading a bit AP and P. If the AP direction is chosen then current runs from SL to BL. This reading method works when reading a 1, but must be monitored so as not to pass the threshold current ( ) when reading a 0. Physically this disturbance is illustrated in figure 10b showing a 0 being read at different currents, the first uses a higher current thus reversing occurs. The goal in making a successful SPRAM device is in controlling the read current and writing direction current. Figure 10 - a) hysteresis / probability of spin reversal b) disturbed state of reading The writing process for this device is identical for both the 0 and 1 process therefore a symmetric bi-directional current device is needed for writing. This is achieved using a current source and sink as seen in the figure 11 the current switches through a flip flop gate with inputs SALT /SALB. The timing diagram is seen in figure 12a which shows the different states corresponding to load/write cycles. For instance, to write a 0 to a memory cell first data from the latch circuit is sent to the write driver via the IO line then SALT is set to H (high) and SALB is set to L (low). With these selectors driving the flip flop circuit the current source is chosen to be BL and the current sink is SL meaning the flow is parallelizing. For 1 writing the process is similar but SALT is set to L and SALB is set to H. An interesting benefit of this process is the data loading capability, it is possible to load individual requests for 0 or 1 for each latch circuit giving the name to this device of bit-by-bit information storage. 7

8 Figure 11 current switching via a sense amp/latch flip flop circuit Figure 12 a) flip flop timing chart, b) data to sense latch from IO, c) write 0, d) write 1 The writing circuit in figure 11 takes care of the issue of current direction, but this scheme does not address accidental writing occurrences. In figure 13 below the R-I hysteresis curve shows that the disturbance (difference in current between reading and writing) is larger in reading AP-state than the P- state. Disturbance is a good indication of spin reversal. The larger the disturbance the less likely there is to be an accidental write while reading. For this reason the device uses parallelizing direction current. The effect of the memory cell s TMR ratio was also investigated (figure 14) and it was found that as the TMR ratio was increased the amount of current needed to read increased and the possibility of spin 8

9 reversal decreased. The results also revealed the lack of dependence on TMR ratio while reading in the parallelizing direction; this is due to being the same regardless of TMR ratio. This graph was very useful in picking the writing direction of P current for the device showing that for a read cycle (using 40µA) of 10 years and TMR ratio of 300% will safely yield more than 2-3 orders of magnitude less disturbances than the anti-parallelizing direction. Figure 13 The R-I hysteresis curve for reading in parallel / anti-parallel directions Figure 14 The reversal possibility dependence on TMR ratio for parallelizing current reading The SPRAM device features can be seen in figure 15 below. The built chip had 2Mb using a processor of 0.2 µm CMOS chip. The memory cell size was 1.6 x 1.6 µm which can be seen in figure 16. The finished device is 5.32 x 2.50 mm in size and consists of sixteen 128kB arrays with accompanying circuitry as seen in figure 17. The final result yielded write/read times of 100 and 40 ns respectively. The chip was put through a cycle of writing which showed that after write cycles the resistance for both AP and P states remained the same with only the switching current degrading (figure 18). The TMR device used in this chip was a structure of NiFe(2nm)/ CoFe(1nm)/MgO(1nm)/CoFe(1nm), which can be seen in figure 18. 9

10 Figure 15 SPRAM chip characteristics Figure 16 micrograph of SPRAM chip cross section Figure 17 photograph of finished chip 10

11 Figure 18 a) diagram of SPRAM chip / TMR cross section b) R-I characteristic for 1 billion writing cycles Future of Spin Transfer Torque RAM The future of SPRAM seems promising with its fast read/write times and its ability to be scaled down to the nanoscale. In a comparison with MRAM (Magneto-resistive RAM) the scalability of SPRAM is far greater as well as the potential for lower energy operation. In figure 19 below the graph on the right show the write current per bit for MRAM skyrockets with nanoscale applications whereas the write current per byte of SPRAM (left) decreases with device width. This is because SPRAM is only dependent on the current density meaning that when the width is decreased by twice its original dimension the current need only be a quarter of its original threshold density for proper operation. Both of these memory types are nonvolatile and have the potential for instant ON operation which will substantially improve power operation, but MRAM is limited due to its method of pole switching (as previously stated in TMR device operation). Figure 19 Comparison of write current vs. TMR device width between SPRAM (left) and MRAM (right) Though there has been much progress on the front of GMR/TMR based memory systems there remains new and necessary obstacles to conquer. SPRAM promises to help extend Moore s Law for memory into the near future, but practical minimization has yet to be seen for these devices. The chip that was described above found a way to get around the two major issues with SPRAM memory devices (accidental spin reversal and current directional switching), but their solution made for slightly slower read/write times than are actually possible. In research by Sarah Gerretsen [9], Department of Physics and Astronomy, University of California it was found that a TMR device of Co (20nm) /MgO (5nm) /Co (5nm) with a switching current of 1.96mA resulted in a 0.104ns P to AP state switching time. This is an example of the very high potential that exists for SPRAM devices in the future. 11

12 Work Cited 1. J. C. Slonczewski, J. Magn. Magn. Mater. 159, L1 (1996); 195, L261 (1999). 2. L. Berger, Phys. Rev. B 54, 9353 (1996); J. Appl. Phys. 81, 4880 (1997); Phys. Rev. B 59, (1999); J. Appl. Phys. 89, 5521 (2001); Interaction of electrons with spinwaves in the bulk and in multilayers condmat / M.D. Stiles & A. Zangwill. Anatomy of Spin-Transfer Torque. May Alain Schuhl, Daniel Lacour, C. R. Physique 6 (2005) P. M. Levy An Idiosyncratic History of Giant Magnetoresistance. NSDL Classic Articles in Context. Issue 2, December < wiki.nsdl.org/index.php/pale:classicarticles/gmr> 6. Butler, W.H., Zhang, X.G., Schulthess, T.C. & MacLaren, J.M., Spin-dependent Tunneling Conductance of Fe MgO Fe Sandwiches. Phys. Rev. B 63, and Mathon, J. & A. Umerski, A., Theory of Tunneling Magnetoresistance of an Epitaxial Fe/MgO/Fe(001) Junction. Phys. Rev. 63, (R) 7. S. Maekawa & T. Shinjo. Spin Dependent Transport in Magnetic Nanostructures. (Eds.) London: Taylor and Francis (2002) pg Kawahara, T., Takemura, R., Miura, K., Hayakawa, J., Ikeda, S., Lee, Y.M., Sasaki, R., Goto,Y., Ito,K., Meguro, T., Matsukura, F., Takahashi, H., Matsuoka, H. & Ohno, H.. 2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE Journal of Solid-State Circuits, vol. 43, NO. 1, January 2008 pg Sarah Gerretsen. Spin Transfer Torque in Ferromagnetic Materials. Department of Physics and Astronomy, University of California, Los Angles, Ca, J. C. Sankey, Y.-T. Cui, R. A. Buhrman, D. C. Ralph, J. Z. Sun, J. C. Slonczewski. Measurement of the Spin- Transfer-Torque Vector in Magnetic Tunnel Junctions. Nature Physics 4, (2008) 11. V. K. Dugaev, J. Barnas. Classical description of current-induced spin-transfer torque in multilayer structures. J. Appl. Phys. 97, (2005) 12. Evgeny Y. Tsymbal. "Magnetic Tunnel Junction." < physics.unl.edu/~tsymbal/tsymbal_files/tmr/sdt_files/page0001.html>. 12