Thermal Magnetic Random Access Memory

Transcription

1 Thermal Magnetic andom Access Memory IEEE International Conference on Computer Design New Memory Technologies San Jose, CA October 4, 2005 James Deak NVE Corporation

2 Participants Jim Daughton - PI Art Pohm Dexin Wang Dave Brownell Pete Eames John Taylor Supported in part by DAPA

3 Motivation MAM combines the non-volatility and infinite endurance of magnetic based memories with silicon processing technology existing emerging Magnetoresistive andom Access Memory, By Saied Tehrani et al. MAM Issues: How to reliably select a random bit for writing How to combine low power and data retention

4 Outline MAM Introduction Status MAM Background MAM Scaling Issues Magnetothermal MAM Modes Curie, Neel/blocking temperature Design equirements Thermal Writing Experiments Conclusions

5 MAM Technology Status Currently Sampling Expected 2006

6 Magnetic Memories Hard drives Tape drives Floppy disks Magnetic Core Memory 1948 thru the 1970s 53k bit in 512 cubic inches

7 Inductive ead W Consider magnetic core memory Here bits are read destructively by detecting a voltage pulse in a read line. W W W Voltage pulse created by writing a toroid at the intersection of two write conductors. V sense dm ( Volume) dt ead signal decreases with decreasing magnetic bit size. Does not scale well.

8 Simple SDT Storage Element Die13 Ω AF Layer Pinned FM Layer Tunneling Barrier Free FM Layer Ohms at 0.1 ua H-EA (Oe) TEM Cross-section of NVE SDT Barrier AF FM FM AlO x

9 Tunneling Magnetoresistance Julliere s Model Phys. Lett. A 54, 225 (1975) Spin conserved during tunneling Two independent spin channels Parallel Low esistance Majority Majority Minority Minority Anti-Parallel High esistance Majority Minority Minority Majority oom Temperature Max. TM AlO x ~ 70% MgO ~ 260% Tunnel Conductance G G n n L L n n + n + n L L n n Magnetoresistance G G TM = = G Spin Polarization L L L L Parallel Anti-parallel AP n n n n PL = Left P = n + n n + n n ~ spin dependent DOS P P 2PL P = 1 P P L ight

10 Typical MAM Cell ead Mode Program Mode Sense Current Bit Line { Free Magnetic Layer, Information Storage. Program Current H e Tunneling { Barrier { Fixed Magnetic Layer Digit Line Program Current H h Isolation Transistor ON

11 Stoner-Wohlfarth Write Select Half Selected Cell Iy Operating Points Iy Ix Switch Switch Selected Cell No Switch Ix Ix, Iy Alone Doesn t Switch Cell Ix, Iy Together Switch Cell

12 Margins With Old Cell - Motorola A 0.18 mm 4Mb Toggling MAM, M. Durlam et al, 2003 IEEE Publication Control of the distribution of switching fields makes the SW- MAM implementation difficult to manufacture and scale. Becomes more difficult as cell size is reduced

13 Magnetic Energy Stability and Thermal Activation N y N x E 2 ( N N ) M V sin θ M ( H θ + H sinθ)v 1 2 y x s = s easy cos 2 hard 1 2 Eb = ( N y N x ) M sv = 2 H = 2K / c M s KV Probability for magnetization to be reversed by thermal activation in time t is 1 E = b ( H ) where = f 0 exp τ kbt P( t) 1 exp( t / τ) Increasing E b /k B T increases the retention time but also increases programming field

14 Energy Barrier and Error ate in MAM Error ate is related to the Barrier Height P( t) = err hr = N N rev bits = 1 e t / τ kbt ( WritFrac) N f e (3600 ) bits = 1 e 0 E ( H ) b tf E b / k B T 0e E k T N rev N b B rev tf e / 0 = ln 1 If N N bits N rev << N bits bits N rev err Eb / k = = N bits f0e t s B T s hr Energy barrier can thus be determined as E b = ln err / hr ( WrtFrac)( N )( f ) 0 k (3600) B T equired E b is thus directly related to the desired error rate, T, and N bits E b should be > 66 k B T ~ 3.7e-19 J, for 1 Mbit, 1e-10 err/hr, 400 K

15 Write Current and Cell Size Single - Domain Ellipse, Aspe ct a tio = KV KV /300 k B nm thick Small volume lowers thermal stability need to increase thickness with decreasing size KV (300k B) Width ( nm) Single - Domain Ellipse, 5 0 nm w ide, A = 1.5 KV Hc Thickness (nm) Hc (Oe) For small single layer free layers, increasing stability increases write field/current to impractical values

16 MAM Scaling Issues Control of switching field distributions Large write current required for stability

17 Alternative Write Methods Toggle Spin Momentum Transfer Thermal Writing Curie Point Write, T c Neel (T N ) or Blocking Temperature (T B ) Write Thermal Spin-Momentum Transfer Write, T-SMT

18 Savtchenko Toggle Write Enhanced write selectivity due to pulse sequence SAF Stack FM/u/FM

19 Toggle Switching Mode Freescale 4 Mbit MAM CMOS 0.18 µm 1T/1MTJ 25 ns Write/read 48 F 2 cell (1.55 µm 2 ) esults Excellent Selectivity High write current (~7 ma/line) Thermal stability at small bit size still an issue high write current

20 SMT Switching Basic Picture Free FM N Stable FM I No external field required to reverse magnetization N e - Free FM e - N Angular momentum exchange between spin polarized current and ferromagnet induces torque and precession Torque ~ ±J M 2 x (M 1 x M 2 ); J~10 7 A/cm2 Slonczewski (1996) At critical I precession large and magnetization precesses into reversed state eversed magnetization stable since torque becomes zero

21 7.0 simulated SMT SMT I c vs. E b A=1.5 A=2 A=3 Increasing E b 25 nm 25 nm Ic (ma) A = 2 A = 1.5 A = 3 50 nm 50 nm 50 nm 75 nm 100 nm 100 nm nm Vary L,W,t 0 2E-19 4E-19 6E-19 8E-19 1E E-18 KV (J) Increasing E b 200 nm E b must remain high as bit size is scaled down thickness must increase Switching roughly proportional to E b At fixed E b, smaller A bits require more current Smaller dimensions do not guarantee lower write current!

22 Magnetothermal MAM Principle of operation Use a very high stability storage layer to improve data retention. Apply current through the tunnel junction to heat the storage layer Storage layer coercivity reduced at high temperature Storage layer may be an AF/FM bilayer or a low T c FM pin storage write ead&heat Thermal via Barrier Thermal via Goal: Design for high density Heating current below 100 µa at 100 nm bit size

23 Curie Point MAM Thermal via High T B AF Coercivity drops due to reduction of free layer magnetization Si-SiN -CoFeNiSiB (16nm)-Ta (10nm) Curie } FM/u/FM pin barrier LTC FM - storage u Thermal via Ms (emu/cc) Oe parallel Temperature (deg C) H c H H Low T High T

24 Neel Point MAM Neel or T B Thermal via High T B AF }FM/u/FM pin barrier FM - storage Low T B AF u Thermal via Offset field (H ex ) drops to zero at high temperature (T B ) Blocking Temeprature ( C ) u(40)/irmn(x)/cofeb(40) Best mode since AF/FM bilayer easy to achieve high E B due to high FM/AF coupling and high AF anisotropy. Also has the best magnetic field immunity IrMn Thickness (nm) H Low T High T H

25 Previous T B MAM Work Heating through barrier confirmed T B writing mechanism verified w/ 10 ns write pulse NOL layers used to increase A and take stress off the barrier at the expense of TM V lim = 2 V Not expected to scale well due to stray field interaction in the FM/AF/FM storage layer Demonstrated >10 10 thermal writes Heating in four layers Ta Ta } Freelayer w/ heater barrier } Heating current CoFe/IrMn/CoFe Storage layer } barrier Freelayer w/ heater Digital value determined by freelayer (H) Ωµm 2 H

26 NVE Neel Point (or T B ) MAM Operation Write Sequence Apply heating and write currents Turn off heating current Turn off write current off on off off initial state: 1 heat field cool final state: 0 H H H

27 Neel Point MAM Considerations Need margin between high T b and Low T b layers (Easy) Low thermal conductivity vias to lower write current (several alternative materials such as PtMn and BiTe) Low thermal conductivity encapsulating material to lower write current (process requires some work) Barrier A must be optimized to permit efficient heating at low write current, while maintaining a large TM (Not too easy, but not impossible) AF must have H ex > H c, Low H c at T B, T B > 150 C (Easy)

28 esistance Area Product equirements L v L v K v T K v 300 K Thermal via MTJ - A Thermal via 300 K Heating current P = I 2 power junction resistance A junction area <A> = ρt Junction resistance area product K v via thermal conductivity L v via length I heating current th = L v /(2K v A) thermal resistance from barrier to 300 K heat sink Junction temperature: T = th P = L 2K v v A I 2 A A Heating current: I( T ) = A T 2K L A v v Heating current proportional to bit area Voltage: V ( T ) I( T ) Maximum A: A = T 2K v = Must limit < ~0.5 V for reliability max 2 VLim L 2 TK v v L v A Optimal value depends on V lim, th, and desired T.

29 Encapsulating Material Optimization nm vias, total = 9 kohm, K via = W/cm-K K v K m Heat diffuses into the encapsulating material Lowers heating efficiency Curie Layer Avg. T (K) Kv 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 Km (W/cm-K) nm vias, total = 9 kohm, K via = W/cm-K Looks as if the thermal vias have a larger effective area A eff = 2Kv T PL 1 A Best if K m <K v /10 via Effective Via Area Heat leak negligible if Km < Kv/10 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 K m (W/cm-K) Kv

30 Thermal Via Optimization K L v v 2 VLim 2 T A max Need minimum K v and large L v Can t increase L v too much Thermal rise time becomes too long oughness becomes too large for low A barrier Settle on 50 nm of PtMn low K v = 0.01 to W/cm-K Able to fabricate low A junctions at this thickness

31 Test Structure Fabrication Anneal Low T b AF +H Anneal Low T b AF -H E-beam and optical lithography IrMn Hex >0 IrMn Hex < Al 150 CrSi 200 Al 500 PtMn 220 Bit 500 PtMn Unpatterned film measurement 2000 SiN PtMn(50)/u(4)/IrMn(4)/CoFeB(4)/AlOx(x)/CoFeB(4)/u(0.7)/FeCo(4)/PtMn(50)/Al(20) 190 u(40)/irmn(x)/cofeb(40) Bits patterned from 0.05 µm to 5 µm. 170 Blocking Temeprature ( C ) T B ~ 110 C Slightly low IrMn Thickness (nm) Post bit ion mill Writing accomplished using external field Post top conductor etch

32 High A Junction (13 Å Al, 28 MΩµm 2 ) (Ω) 1.2E E E E E E E E E E+06 die µm x 4 µm ellipse ΜΩµm Burns out here 10 na 150 na 500 na 1000 na H (Oe) die µm x 4 µm ellipse ΜΩµm 2 Initial 10 na measurement 1 no change at 500 na No TM at 1000 na Check (H) at lower current (Ω ) (Ω ) die µm x 4 µm ellipse ΜΩµm 2 3.4E E E E E E E na 3.4E E E E E H (Oe) die µm x 4 µm ellipse ΜΩµm 2 2.0E E E E na 2.0E E E E E E H (Oe) (Ω ) 6.0E na -- initial 10 na post 1000 na 4.0E E+06 Final 10 na measurement 0.0E H (Oe) Device burns out before IrMn T b is exceeded

33 Low A Junction (6 Å Al, 5 Ωµm 2 ) 0.41 array 7 die nm array 7 die nm (Ω ) offset (Ω ) H (Oe) H (Oe) array 7 die nm array 7 die nm offset (Ω ) offset (Ω ) H (Oe) H (Oe) Changes from SV to PSV behavior Why?

34 Model Description Pinned layer/barrier/storage layer FM 1 (t 1,M s1,k 1 )/u(j U )/FM 2 (t 2,M s2,k 2 )/AlO x (J AlO )/FM 3 (t 3,M s3,k 3 ) Strong coupling Weak coupling φ 3 Total Energy External Fields Interlayer Exchange Anisotropy Demagnetization Fields E = E + E + E + tot z exc K E d [ M s1t1 cos( φ1 ) + M s2t2 cos( φ2) M s3t3 cos( φ3 )] [ M t sin( φ ) + M t sin( φ2) M t ( φ )] Ez = Bx + E B y s1 1 1 s2 2 + s3 3 sin ( φ φ ) + J ( φ φ ) exc = J U cos 1 2 AlO cos 2 2 ( φ ) + K t sin ( φ ) K t ( φ ) E K = K + 2 1t1 sin sin E d = µ 0t1M s1h d1 + µ 0t2M s2h d 2 + µ 0t H di = H H x i y i = N ( i, j) N ( i, 3 xx xy j= 1 N yx( i, j) N yy( i, j) 2 j) 3 M M x j y j 3 M 3 s3 H 3 d 3

35 Simulated esponse (arb) both layers pinned - low temperature K = 100,6000 t = 4,1 Bpin = 0.04, 0.01 J = 1e Bx (T) Apparently H c IrMn > (H c + H ex ) PtMn And pinned layer SAF not well matched Coercivity of the storage layer is too high at T B! one layer pinned - high temperature Wanted this at T B, H c < 50 Oe (arb) K = 3250,6000 t = 4,1 Bpin = 0.0, 0.01 J = 1e Bx (T) H Got this at T B, H c > 100 Oe

36 IrMn H ex and H c Must increase IrMn layer to 60 nm Increasing thickness of IrMn decreases H c and increases H e. T b would be increased 50 to 100 K. Increasing A to 10 Ωµm 2 would keep the write current at the present value and still permit safe writing T 2K v I( T ) = A L v A

37 Measured Programming Current Current through barrier required to exceed T b I (mα) wafer 393 y = x I - Tb Linear (I - Tb) area (µm 2 ) 8.3 ma/µm 2 Using only a single barrier and no heater layers 100 nm bit π*(0.1/2)*(0.1/2)*8.31 = ma

38 Conclusions Demonstrated heating through the barrier, and potential for < 100 µa write currents at 100 nm dimensions IrMn thickness needs to be increased A needs to be optimized, need roughly 50 Ωµm 2 Need to do a better job matching the SAF Lower thermal conductivity encapsulating material like BCB would further decrease write current If needed NOL heaters could be added to further decrease write current (at the expense of signal)