Magnetic Tunnel Junction for Integrated Circuits: Scaling and Beyond
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1 TUTORIAL: APPLIED RESEARCH IN MAGNETISM Magnetic Tunnel Junction for Integrated Circuits: Scaling and Beyond Hideo Ohno 1,2 1 Center for Spintronics Integrated Systems, Tohoku University, Japan 2 Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Japan Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, Katsuya Miura, Naoki Kasai, Hiroyuki Yamamoto, Kotaro Mizunuma, Huadong Gan, Michihiko Yamanouchi, Hideo Sato, Ryouhei Koizumi, Jun Hayakawa, Kenchi Itoh, Fumihiro Matsukura and many otehrs Work supported by the FIRST program of JSPS.
2 OUTLINE 1. Integrated circuits - needs and challenges - 2. What magnetism can offer - current status of magnetic tunnel junction - 3. Research directions 4. Further future
3 Semiconductor sales 2009 Memory ($45B) Analog ($32B) Logic ($65B) MOS Micro ($48B) TOTAL $190B 3 WSTS 2010
4 Semiconductor sales 2009 Memory ($45B) Analog ($32B) Logic ($65B) Possible area of impact MOS Micro ($48B) TOTAL $190B 4 WSTS 2010
5 DRAM Scaling Difficult to obtain enough storage capacitance (C s ), even using a cylindrical shaped capacitor structure with high aspect ratio, high-k insulator and metal electrodes in a1t1r cross-point cell (4F 2 ). Plate(Vcc/2) Cs Word-line Bit-line(Vcc, 0) Plate C s > ff Leakage current through MOSFET (No capacitor leakage) Refresh time Parasitic bit-line capacitance Sense amplifier margin Soft error Relative permittivity of thin film Insulator ε available SiO2 3.9 yes SiN 5-10 yes Ta2O yes In 25 nm generation (F=25nm) ε of capacitor insulator > 70 even if the cylinder height is 1000nm. BST >200 no 2F F; minimum feature size aspect ratio = 40 FEATURE SIZE Electrode film thickness < 10nm High resistance 5
6 Processing Power Power Density ( W/cm 2 ) Source: Intel Explosive increase of power consumption P C L f 3 POWER and DELAY Multicore technology (but with global delay) 6
7 High-performance transistor leaks E. Pop, Nano Res. 3, 147 (2010) Leakage requires power gating; basically shuts the power off the part that is not in use. Requires cost assessment (power and delay for power gating). STATIC POWER 7
8 Low voltage to counter active power E. Pop, Nano Res. 3, 147 (2010) DYNAMIC POWER 8
9 OUTLINE 1. Integrated circuits - needs and challenges - 2. What magnetism can offer - current status of magnetic tunnel junction - 3. Research directions 4. Further future
10 Magnetic Tunnel Junction Tunnel MagnetoRes istance (TMR) R AP R P R P 2 2P 1 P 2 Parallel E E Antiparallel Ferromagnet 1 Insulator Ferromagnet 2 Room temperature TMR: Miyazaki and Tezuka (Tohoku U.), J. Mag. Mag. Mat and Moodera et al. Phys. Rev. Lett For a review on integrated circuit application, see e.g. S. Ikeda et al. IEEE Trans. ED.54, 991 (2007)
11 MTJ Development (I) M. Julliere, Phys. Lett S. Maekawa and U. Gafvert, IEEE Trans. Mag. (1982) Room temperature TMR: Miyazaki and Tezuka (Tohoku U.), J. Mag. Mag. Mat and Moodera et al. Phys. Rev. Lett
12 MTJ Development (II) Spin-transfer torque Switching: J. Slonczewski, J. Magn. Magn. Mat. 159, L1 (1996). L. Berger, Phys. Rev. B 54, 9353 (1996). Domain wall motion: L. Berger, J. Appl. Phys. 55, 1954 (1984), J. Appl. Phys. 71, 2721 (1992). MgO-MTJ W. H. Butler, X.-G. Zhang, T. C. Schulthess, and J. M. MacLaren, Phys. Rev. B 63, J. Mathon and A. Umersky, Phys. Rev. B 63, R 2001.
13 TMR ratio of MgO-MTJs TMR ratio (%) トンネル磁気抵抗比 (%) MgO-barrier Tohoku-Hitachi AIST 604% S. Ikeda et al. Appl. Phys. Lett. 93, (2008) CanonANELVA & AIST AIST IBM AIST AlO x RT year 年
14 13.9 mm 15.5 mm Nonvolatile Logic-in-Memory Full adder block (for image processing) SUM P : Precharge phase E : Evaluate phase VDD P E Active Power-off P E P E Active Power-off P E Active Poweroff Poweroff Inputs (A,B and Ci) A=0,B=0,Ci=0 A=0, B=0,Ci=1 CLK Standby Standby Standby Standby Sbefore=0 Safter=0 S (=A B Ci) CARRY S (=A B Ci) Sbefore=1 S before=0 Safter=1 S after=0 780mV/div S before=1 S after=1 1mS/div 10.7 mm 0.18 mm CMOS/MTJ Process S. Matsunaga, H. Ohno, T. Hanyu, APEX, 1, (2008) MTJ: 100 x 200 nm 2 Nonvolatile: ultimate power gating (no static power) Memory in the back end + part of logic (reduced # of tr. = suppression of delay and dynamic power)
15 MTJ for VLSI: A wish list 1. Small footprint (F nm) 2. High output (TMR ratio > 100%) 3. Nonvolatility (E/k B T >40) 4. Low switching current (I C < F ma) 5. Back-end-of-the-line compatibility (350 o C) 6. Endurance 7. Fast read & write 8. Low resistance for low voltage operation 9. Low error rate 10. Low cost
16 perpendicular E V H M g e I V H M E K S B C K S m E Parallel Antiparallel Thermal fluctuation k B T E Parallel Antiparallel Thermal fluctuation k B T I c0 and D=E/k B T
17 Perpendicular MgO-CoFeB MTJ Al 2 O 3 V - Cr/Au Ru (5) Ta(5) CoFeB(1.7) MgO(0.85) V + interface perpendicular anisotropy CoFeB(1.0) Ta(5) Ru(10) Ta(5) 40 nm SiO 2 /Si sub. (nm) J C0 = 3.9 MA/cm 2 (I C0 = 49 μa), E/k B T = 43, TMR ratio 124% S. Ikeda et al., Nat. Mat. 9, 721 (2010)
18 Comparison of MTJs Type Stack structure (nm) Size (nm) MR (%) RA (Ωμm 2 ) J C0 (MA/cm 2 ) I C0 (μa) Δ=E/k B T I C0 /Δ T a ( o C) Ref. i-mtj CoFeB(2)/Ru(0.65)/CoF eb(1.8) SyF 100x200 >130 ~10 2 ~ ~ J. Hayakawa et al., IEEE T-Magn., 44, 1962 (2008) p-mtj L10- FePt(10)/Fe(t)/Mg(0.4)/ MgO(1.5)/L10-FePt(t) Blanket 120 (CIPT) 11.8k M. Yoshizawa et al., IEEE T-Magn., 44, 2573 (2008) p-mtj L10- FePt/CoFeB/MgO(1.5)/ CoFeB/Co based superlattice Blanket 202 (CIPT) H. Yoda et al., Magnetics Jpn. 5, 184 (2010) [in Japanese]. p-mtj [Co/Pt]CoFeB/CoFe/Mg OCoFe/CoFeB/TbFeCo Blanket (CIPT) K. Yakushiji et al., APEX 3, (2010) p-mtj [CoFe/Pd]/CoFeB/MgO/ CoFeB/[CoFe/Pd] 800x800 N 100 (113) 18.7k (20.2k) (325) K. Mizunuma et al., MMM&INTERMAG2010 p-mtj CoFeB (1)/ TbCoFe (3) 130 φ ~ p-mtj L1 0 -alloy φ M. Nakayama et al., APL 103, 07A710 (2008) T. Kishi et al., IEDM 2008 p-mtj Fe based L1 0 (2)/CoFeB (0.5) H.Yoda et al., Magnetics Jpn. 5, 184 (2010) [in Japanese]. p-mtj CoFeB(~1.7) 40 φ >110 <18 <4 <50 > S. Ikeda et al., Nat. Mat. 9 (2010) 721. K. Miura, et. al. HC-02, MMM 2010 MMM 2010 DT-05. (Poster session) M. Yamanouchi et al. DP-13. (Poster session) H. Yamamoto et al.
19 OUTLINE 1. Integrated circuits - needs and challenges - 2. What magnetism can offer - current status of magnetic tunnel junction - 3. Research directions 4. Further future
20 Scaling E/k B T perpendicular I High 1 E M S H KV 2 2e 1 0 M mbg 2 E C K u 1 2 M S H V 3 IC [ ma] for E 60k H K S K and low B 100 T = = = = I C0 = 100 ma I C0 = 50 ma I C0 = 30 ma I C0 = 20 ma
21 OUTLINE 1. Integrated circuits - needs and challenges - 2. What magnetism can offer - current status of magnetic tunnel junction - 3. Research directions 4. Further future
22 Magnetization manipulation by Magnetic field write/read heads for HDD 1 st generation MRAM Spin current L. Berger, J. Appl. Phys. 55, 1954 (1984). J. Slonczewski, J. Magn. Magn. Mat. 159, L1 (1996). L. Berger, Phys. Rev. B 54, 9353 (1996). Spin torque MRAM Spin torque oscillator Race-track memory Electric field 4Mb Array R. Takemura et al., VLSI Circ. Dig. p.84 (2009)
23 Spin-transfer switching VIt 0.5 (V) 30 ( ma) 1 (ns) 15 (fj) Electric field switching CV S d E (nm) ( ) 5 (nm) 9.8 (5 (MV/cm)) (fj)
24 Spin-split valence band of (Ga,Mn)As Ferromagnetic semiconductor (Ga,Mn)As: Mn gives rise to localized spin and hole k x,y,z [10 7 cm -1 ] T. Dietl et al. Science 2000 Material, Ferromagnetism and Functionalities; See H. Ohno, Science, 1998, T. Dietl et al. Science 2000, H. Ohno et al. Nature 2000, D. Chiba et al. Science 2003, M. Yamanouchi et al. Nature 2004, D. Chiba, Nature 2008
25 Electric-field control of magnetization direction K M Angle (deg.) 0-5 [100] axis Ferromagnetic Semiconductor (Ga,Mn)As -10 H = Gate electric Field E (MV/cm) D. Chiba et al. Nature (2008)
26 Electric-field effects on metals FePt, FePd: M. Weisheit et al., Science (2007). Fe/Au: T. Maruyama et al., Nature Nanotechnology (2009). Multiferroics: T. Arima et al., PASPS13 (2009/1/27). All at room temperature CoFe: M. Endoh, S. Kanai, S. Ikeda, F. Matsukura, and H, Ohno, Appl. Phys. Lett. 96, (2010).
27 Summary MTJ is much better positioned now than before with 30 nm dimension in sight. Once ready this could trigger a major paradigm shift. Material science determines the scaling, requiring understanding of involved physics. Eg. K U,, high speed switching Processing (and related fields) requires further development. One of the future directions is electric field switching (session AA). This may further reduce the power for switching drastically.
Magnetic Tunnel Junction for Integrated Circuits: Scaling and Beyond
TUTORIAL: APPLIED RESEARCH IN MAGNETISM Magnetic Tunnel Junction for Integrated Circuits: Scaling and Beyond Hideo Ohno 1,2 1 Center for Spintronics Integrated Systems, Tohoku University, Japan 2 Laboratory
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