Magnetic memories: from magnetic storage to MRAM and magnetic logic

Transcription

1 Magnetic memories: from magnetic storage to MRAM and magnetic logic WIND Claude CHAPPERT, CNRS Département "Nanospintronique" Institut d'electronique Fondamentale Université Paris Sud, Orsay, FRANCE Back to the basics Electrons carry a charge electronics transfer of information - storage and a spin quantum mechanics: r projection of angular momentum s : ± r μb r dipolar magnetic moment ms = g s h 1 2 h WIND/IMST - Memory tutorial - IMEC - 26 Nov

2 Back to the basics Electrons carry a charge electronics transfer of information - storage and a spin magnetism m r l m r s magnetic moments e - WIND/IMST - Memory tutorial - IMEC - 26 Nov Back to the basics Electrons carry a charge electronics transfer of information storage and a spin magnetism m r l m r s localized atomic magnetic moments e - magnetic storage WIND/IMST - Memory tutorial - IMEC - 26 Nov

3 Outlook - the basics of magnetic recording - the basics of spin electronics - the magnetic tunnel junction - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov Basics: magnetic energies for storage localized atomic magnetic moment picture basic magnetic energies Exchange interaction Magnetic anisotropy energy tends to keep parallel the atomic moments total energy changes with the orientation of M "magnetization" M in ferromagnets = magnetic moment per unit volume r μ = M V magnetic storage of the information "0" "1" ΔE = KV >> k T B WIND/IMST - Memory tutorial - IMEC - 26 Nov

4 Basics : exchange interaction and magnetization Zeeman energy: interaction with a magnetic field r r E = V H M I coil H Oerstedt WIND/IMST - Memory tutorial - IMEC - 26 Nov Basics : exchange interaction and magnetization Zeeman energy: interaction with a magnetic field r r E = V H M coil Magnetic anisotropy energy: preserves orientation of magnetization after writing WIND/IMST - Memory tutorial - IMEC - 26 Nov

5 Magnetic recording 1898: V. Poulsen s Drum Telegraphone 1933: Ring type head E. Schuller s: Magnetic tape: F. Pfleumer / BASF-AEG 1953: Magnetic core memory 1956: First HDD -IBM RAMAC WIND/IMST - Memory tutorial - IMEC - 26 Nov Speed: the natural dynamics of the magnetization The Landau-Lifshitz-Gilbert (LLG) equation r r dm r r α r dm = γ μ0 ( M H eff ) r dt M M dt H eff damping torque Damped precession of the magnetization M around its equilibrium axis M Effective field H eff : all the magnetic energies Precession frequency: f = f 0 H eff f 0 = 28 MHz / mt ( = 2.8 GHz / koe ) WIND/IMST - Memory tutorial - IMEC - 26 Nov

6 Precessional dynamics in thermally activated reversal Néel - Brown reversal = thermally activated precessional behavior within the energy well attempt frequency function of α, K U, WIND/IMST - Memory tutorial - IMEC - 26 Nov Non volatility: thermally excited switching The "magnetic non volatility" long term stability of the magnetic storage : spontaneous reversal of the magnetization due to thermal activation ΔE = KV Néel Brown model probability P for no reversal after a time t : P = t e τ τ 0 ~ 1 ns k B T = thermal energy T = temperature τ = τ 0 exp Δ ( E / k T ) B ex : stability on 10 years = s 1-P = 10-6 KV ~ 54 k B T "soft" error 1-P = KV ~ 68 k B T WIND/IMST - Memory tutorial - IMEC - 26 Nov

7 The necessary compromise in magnetic recording "0" "1" ΔE = KV >> k T B increase recording density reduce bit volume V reduce writing power thermal stability : ΔE = K V increase K reading : sensitivity, speed X Research / Innovation writing : H writing ~ K reduce K WIND/IMST - Memory tutorial - IMEC - 26 Nov Storing : scalability of solid state magnetic recording non volatility : 10-9 soft error rate in 10 years "0" "1" ΔE = KV 60 k B T nm today's best : FePt (L 1 0) 2 nm A potential for non volatile «nano»- spin electronics but H switching ~ 12 Teslas! field induced writing impossible spin transfer writing requires high currents precession speed ~ 33 GHz!!!! WIND/IMST - Memory tutorial - IMEC - 26 Nov

8 1988: a major step into Spin Electronics 1988: The giant magnetoresistance (GMR) in magnetic multilayers Fe/Cr multilayers R/R(H=0) NOBEL 2007 ~ 80% Fe Cr Fe 1988: GMR discovered simultaneously by Fert et al. (Orsay) and Grünberg et al. (Jülich) A bridge between magnetic storage and electronics? WIND/IMST - Memory tutorial - IMEC - 26 Nov Outlook - the basics of magnetic recording - the basics of spin electronics - the magnetic tunnel junction - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov

9 The foundation of spin electronics electrons traveling inside conductors N. Mott, Adv. Phys 13, 325 (1964) FertCampbell, PRL 1967 <> : mean free path λ relaxation time τ "spin flip" scattering event spin diffusion length l λ λ λ = λ sd sf sf : spin mean free path 0 weak spin flip scattering rate ( l sd >> λ ) "two channels" conduction model R R or R R R τ sf ferromagnetic metals: normal metals spin dependent λ WIND/IMST - Memory tutorial - IMEC - 26 Nov The foundation of spin electronics To directly «see» the «two-channel» conduction, one must make a material with internal structuration at the same scale as the λ et λ mean free path: the spin valve F ferromagnetic layer NM non magnetic layer (Cu,..) F ferromagneticlayer nano input: λ > e couches > λ WIND/IMST - Memory tutorial - IMEC - 26 Nov

10 Giant magnetoresistance in multilayers 1988: Fert et al. (Orsay) and Grünberg et al. (Jülich) nano input!!!! λ << λ ρ >> ρ λ, λ >> t layers (a few nm ) parallel configuration R P < R AP antiparallel configuration I F NM F F NM F ρ ρ ρ = P ( ρ ) ( ρ ρ ) = ρ ρ AP 4 Also: spin dependant "interface" scattering, reflection, WIND/IMST - Memory tutorial - IMEC - 26 Nov A first useful device : the "spin valve" B. Dieny et al., PRB 1991 current in plane (CIP) I θ "free" ferromagnetic layer (NiFe, CoFe,..) metallic (Cu) interlayer "pinned" ferromagnetic layer R = R 0 ΔR/2 cos (θ) ΔR/R ~ 6 à 20 % A convenient, compact, high sensitivity magnetic sensor! but low resistance, low signal amplitude planar geometry not well adapted to solid state electronics WIND/IMST - Memory tutorial - IMEC - 26 Nov

11 Outlook - the basics of magnetic recording - the basics of spin electronics - the magnetic tunnel junction - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov The tunnel junction Metal 1 insulating barrier (Al 2 O 3, ) Metal 2 transmission by tunnel effect through a very thin (~1nm) barrier insulator E F M 1 M 2 ev electron spin is not affected by the tunneling 0 E F WIND/IMST - Memory tutorial - IMEC - 26 Nov

12 The magnetic tunnel junction Jullière, Phys. Lett. A (1975) Ferromagnetic metal 1 tunnel barrier (Al 2 O 3, ) Ferromagnetic metal 2 parallel state insulator antiparallel state insulator F 1 F 2 F 1 F 2 E F ev E F ev 0 E F 0 E F spin dependant tunneling, MR = (R AP -R P ) / R P >> 1 WIND/IMST - Memory tutorial - IMEC - 26 Nov The magnetic tunnel junction Ferromagnetic metal 1 tunnel barrier (Al 2 O 3, ) Ferromagnetic metal 2 Jullière, Phys. Lett. A (1975) parallel state antiparallel state ev ev E F E F P = N N ( E ( E F F ) N ) N ( E ( E F F ) ) TMR ΔR = = R 2 1 P P2 P 1 AP P1 2 WIND/IMST - Memory tutorial - IMEC - 26 Nov

13 Coherent tunneling through single crystal MgO tunnel junctions S. Yuasa et al. Nature Mat. 3, 868 (2004) Fe(001) MgO(001) Fe(001) RA (kω.µm 2 ) H (Oe) giant ΔR/R : 250% at 20K 186% at 293 K (also: Parkin et al., Nat. Mat 3 (2004) origin: different attenuation for spin up and spin down electrons due to symmetry matching between metal and MgO states: up to 6000% predicted! [Butler et al, PRB63 (2001); Mathon et al., PRB 63 (2001) ; Butler & Gupta, Nat. Mat. 3, 845 (2004) ; Zhang et al., PRB (2004)] WIND/IMST - Memory tutorial - IMEC - 26 Nov The magnetic tunnel junction M. Jullières, 1975 J. Moodera, 1995 "free" ferromagnetic layer (NiFe, FeCo, FeCoB, ) tunnel barrier (ex: Al 2 O 3, MgO ) ~ 1 nm thick "pinned" ferromagnetic layer (NiFe, FeCo, FeCoB, ) I ΔR/R > 600 RT!!! (MgO single crystal tunnel barrier) practical value: ΔR/R ~ % for RA ~ 3-50 Ω.µm 2 A "vertical", high signal device for high density electronics! WIND/IMST - Memory tutorial - IMEC - 26 Nov

14 Outlook - the basics of magnetic recording - the basics of spin electronics - the magnetic tunnel junction - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov The magnetic RAM (M-RAM) Magnetic Random Access Memory (M-RAM) (IBM, NVE, > 1996) "0" "1" "cross point" architecture Principle : - store binary information on arrays of magnetic tunnel junctions connected by conducting lines, - that serve to address each cell individually for reading and writing WIND/IMST - Memory tutorial - IMEC - 26 Nov

15 The magnetic RAM: practical implementation "0" "1" "cross point" architecture practical MRAM cell: "1T1MTJ" architecture for reading Transistor incomplete integration of the writing function : needs magnetic field created by independent line for writing WIND/IMST - Memory tutorial - IMEC - 26 Nov MRAM: writing / Stoner-Wohlfarth scheme H K H Y (digit line) M H X (bit line) H K OR WIND/IMST - Memory tutorial - IMEC - 26 Nov

16 Magnetic RAM : "Savtchenko" toggle writing mode F1 F2 Ru free layer = synthetic antiferromagnet current lines at 45 deg. of easy axis toggle switching mode B. N. Engel et al., IEEE Trans. Magn. 41, 132 (2005) WIND/IMST - Memory tutorial - IMEC - 26 Nov Magnetic RAM : "Savtchenko" toggle writing mode excellent immunity to program errors (cf Korenivski, APL 86 (2005)) 4 Mbits Freescale demo : µm CMOS - ~47 F 2 cell size - 25 ns read/write cycle time V (Andre et al., IEEE JSSC 40, 301 (2005)) But : high currents (several ma) needed for writing!!! WIND/IMST - Memory tutorial - IMEC - 26 Nov

17 Magnetic RAM : reducing I writing Sending a current in a conducting line is not a very efficient way of creating a magnetic field on a nano-element!!!! channeling the magnetic field using magnetic "cladding" I gain of a factor of ~2 on the field/current ration limits the stray field on half-addressed cells other "tricks" can help gain additional factors, up to???? WIND/IMST - Memory tutorial - IMEC - 26 Nov Freescale: 1rst MRAM product in 2006 Above CMOS technology 4 Mbit standalone memory Toggle switching reliability, speed (30ns), cyclability Named "Product of the Year" [Electronics Products Magazine, Jan. 2007] in 2007 : achieved army specifications automotive applications NEW in Nov. 2008: - spin off company EVERSPIN - new products, target : battery backed SRAM WIND/IMST - Memory tutorial - IMEC - 26 Nov

18 "Field induced magnetic switching" : downscaling prospect to ensure required non volatility (Neel's model) energy barrier KV >40 k B T, if V as F 2, then K ~ 1/F 2 I field induced switching : requires a current in a conducting line electromigration limit 10 7 A/cm 2 ~ 100 ma/µm constant j : available H write decreases ~ as F F realistic estimation for 2 different width W of magnetic element: W = 4/3 F and 2 F I (ma) Imax (electromigration limit) I for switching - W= (4/3) F I for switching - W= 2 F WIND/IMST - Memory tutorial - IMEC F - (nm) 26 Nov A "conventional" answer: the thermally assisted writing in TAS-MRAM From a "0".. to a "1" Word line MTJ OFF ON ON OFF OFF addressing transistor "0" state Heat Switch Field cool "1" state Exchange biased storage layer is SAF/AF multilayer low T B barrier Altis Semicoductors, Quimonda: demo at IEDM Dec 2006 with 2 bits/cell high T B WIND/IMST - Memory tutorial - IMEC - 26 Nov

19 CMOS integration of TAS-MRAM analytical model for 2ns pulse and 140K temperature rise power (µw) required writing power for bit dia.=(4/3)f available power with Wt=(4/3)F available power with Wt= 3 F required switching current for MTJ width W MTJ = 4/3 F available current for 2 transistor widths: W T = 3 F W T = 4/3 F F (nm) becomes more favorable when F decreases condition much relaxed by using bipolar transistor (cf PC RAM) issues remaining: - match thermal stability with heat sensitivity in the cell - still needed: a magnetic field from a conducting line WIND/IMST - Memory tutorial - IMEC - 26 Nov Outlook - the basics of magnetic recording - the basics of spin electronics - the magnetic tunnel junction - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov

20 The Spin Transfer Torque mechanism e - transverse component ~1 nm ferromagnetic layer F 2 J. C. Slonczewski, JMMM 159, L1 (1996) L. Berger, PRB 54, 9353 (1996) in the ferromagnetic layer: exchange interaction between e - spin and M the incoming electrons loose their transverse spin angular momentum to the magnetization M of the ferromagnetic layer conservation of total angular momentum torque applied on M switching beyond a threshold J c in current density : scalable WIND/IMST - Memory tutorial - IMEC - 26 Nov Writing: Spin Transfer Torque switching F 1 thick layer F 2 thin layer J. C. Slonczewski, JMMM 159, L1 (1996) e - sd exchange interaction Writing 0 e - Writing 1 Writing by a bipolar current density with J c and J c - WIND/IMST - Memory tutorial - IMEC - 26 Nov

21 Magnetization switching by spin transfer in MgO tunnel junctions J. Hayakawa et al., Jap.JAP 44, L1267 (2005) ex. of good compromise: TMR ~ 80% for T anneal ~ 300 C <J C > ~ A/cm 2 WIND/IMST - Memory tutorial - IMEC - 26 Nov spin torque MRAM by SONY SONY, IEDM Conference, Dec A way towards very high density, fast MRAM, with potential for downscaling down to 20nm or less! A true "solid state" integration of R/W and magnetic media! WIND/IMST - Memory tutorial - IMEC - 26 Nov

22 From conventional MRAM to "spin transfer" MRAM Freescales s MRAM (2006) Demo chips of «Spin»-RAM: SONY, IEDM Dec HITACHI, ISSCC March 2007) simple integrated architecture, above CMOS technology, high density ( <16 F 2 ), potential for downscaling down to 20nm fast ( ns) M-RAM: main advantage of M-RAM versus other NVM RAM.) can we reach high operation speed? will it be reliable? WIND/IMST - Memory tutorial - IMEC - 26 Nov Precession of the magnetization and spin transfer the Landau-Lifshitz-Gilbert (LLG) equation r dm dt = γ μ0 r r α ( ) M H M dm eff r M dt H eff r friction torque (damping) r the "spin transfer torque" r G j M r r ( M p) 0 only if M and p are non colinear M "negative friction" torque induced by spin transfer p f 0 ~ 2.8 GHz / koe switching threshold J c : ~ when negative friction overcomes damping WIND/IMST - Memory tutorial - IMEC - 26 Nov

23 Macrospin dynamics of spin transfer writing The case of a platelet magnetized in plane: J.Sun, PRB 62, 570 (2000) film plane M p thermal excitation spreads the initial orientation m Z r G j M r r ( M p) = 0 if M and p are colinear m Y wide distribution of switching time Devolder et al., PRB75, (2007) WIND/IMST - Memory tutorial - IMEC - 26 Nov Switching by spin-transfer torque vs field «negative» friction enhanced friction Spin-Transfer Torque (friction-gradient driven switching) Field (Energy-gradient driven switching) WIND/IMST - Memory tutorial - IMEC - 26 Nov

24 Routes towards fast spin transfer writing Thermally assisted spin transfer switching : J ~ J c t pulse ~ ns (cf demos) «negative» friction enhanced friction Precessional spin transfer switching : J > J c t pulse 1 ns control thermal fluctuations non zero initial torque M p - T. Devolder et al., APL 88, (2006) PRB 75, ,5 (2007) PRB 75, ,10 (2007) PRL100, (2008) - Ito et al., APL89, (2006) - Serrano-Guisan et al., PRL101 (2008) ; Garzon et al., PRB78, R (2008) -etc.. WIND/IMST - Memory tutorial - IMEC - 26 Nov STT MRAM main configurations spin polarizing fixed layer 2 nd tunnel barrier free layer tunnel barrier fixed layer (reference) film plane M m X p (a) (b) (c) m Z m Y Y. Suzuki WIND/IMST - Memory tutorial - IMEC - 26 Nov

25 CMOS integration of spin RAM: writing compatibility with ITRS roadmap LOW POWER-NMOS Nominal voltage (V n ) Node (F in nm) Max current (µa) at 25 C for transistor width W t =F R n = V n /I d,sat for W t =F (kω) Year bipolar use of the NMOS transistor V DD GND R MTJ (MTJ) R MTJ I d I d V d V s V g GND V s (NMOS transistor) V g V d V DD WIND/IMST - Memory tutorial - IMEC - 26 Nov CMOS integration of STT MRAM in plane magn. requires a "bipolar" use of the NMOS transistor large variation of resistance during the write process (Sony) V DD GND R MTJ (MTJ) R MTJ I d I d V d V s V g GND V s (NMOS transistor) V g V d V DD within ITRS 2003 roadmap WIND/IMST - Memory tutorial - IMEC - 26 Nov

26 CMOS integration of STT MRAM in plane magn. approximate switching current density for in plane magnetization j 2e α tf M = h η μ0m 2 μ H S S jsw ( a) ON // 0 in plane shape anisotropy >> K thermal stability factor current density should not depend much on size!!!! WIND/IMST - Memory tutorial - IMEC - 26 Nov Scalability of Spin-RAM : writing in plane magn. spin transfer writing magnetic element: (4/3) F (min) 2 nm writing speed: ~ ns tunnel junction : R ~ R transistor / 2 transistor width: (4/3) F for high density memory I WR (SONY, IEDM 2005) I WR (lab's best, 2006) transistor's limit RA ~ 1-20 Ω.µm 2, within reach also good for reading WIND/IMST - Memory tutorial - IMEC - 26 Nov

27 CMOS integration of STT MRAM out of plane magn. current I (µa) approximate switching current density for out of plane magnetization Isw - alpha=0.01 Isw - alpha=0.1 It,max for Wt= 4/3 F It,max for Wt= 3 F 2e α t M = h η jsw ( b) jon F (nm) α = 0.1 α = 0.01 eff ( μ H ) thermal stability factor available current for 2 transistor widths: W T = 3 F W T = 4/3 F more favorable than in plane case, if similar values of α/η are obtained A required switching current for MTJ width W MTJ = 4/3 F WIND/IMST - Memory tutorial - IMEC - 26 Nov Perpendicular STT RAM Toshiba Develops MRAM Device, Opening Way to Gb Capacity Nikkei Electronics Asia, November 7, 2007 TbCo alloy (?) with TMR ~ 100% and j C ~ A/cm 2 WIND/IMST - Memory tutorial - IMEC - 26 Nov

28 Summary: Spin - RAM specifications Products / Demos Predicted Position vs CMOS Cell size F 2 < 16 F 2 >> NAND << SRAM Technology Speed Endurance Non volatility Above CMOS ~ 40 ns (2.7 ns) ~ ns ~ infinite > 10 years embedded RAM ~SRAM >> NAND Logic circuits? Scalability 130 nm 20 nm? WIND/IMST - Memory tutorial - IMEC - 26 Nov Outlook - the basics of magnetic recording - the basics of spin electronics - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov

29 CMOS logic circuits: every where and problems CMOS Logic Circuits Low power (near zero static power) High density (45nm, 2007) High Speed (>Some GHz) ASIC Application-Specific Integrated Circuit High mask cost 90nm) Long delay to correct a bug Long time to market LEAKAGE CURRENTS Telecom Automobile Military/Aerospace Audio/video Medical smart cards: no internal power, cheap, robust WIND/IMST - Memory tutorial - IMEC - 26 Nov Programmable logic devices ASIC Programmable Logic LUT: Look Up Table a b s a b s a=adr 0 b=adr SRAM s config.: EEPROM, Flash WIND/IMST - Memory tutorial - IMEC - 26 Nov

30 Low standby Power Programmable logic devices Non volatile, multi-core logic: are powered only the core that need to operate others preserve state and start «instantly» when powered on Active Inactive 100% 61% 14% 0% Towards a magnetic FPGA CLB CLB switches and logic blocs (CLB) are made: non volatile programmable by Spin- MRAM elements CLB CLB WIND/IMST - Memory tutorial - IMEC - 26 Nov FPGA Logic Circuits SRAM I/O I/O FPGA I/O Configuration High speed transceiver Flash Static RAM based FPGA High computing speed Infinite programming endurance I/O SRAM Look Up Table Flip-Flop CMOS intrinsic memorizing constraint: Data Volatility Long latency at each start or restart High standby power (>30% for 90nm) Data loss in case of power failure Uneasy dynamical reconfiguration Input Clk Output Configurable logic block (CLB) WIND/IMST - Memory tutorial - IMEC - 26 Nov

31 Non volatile FPGA Logic Circuits I/O Configuration replace Flash and SRAM by a non volatile memory (NVM) directly embedded inside the look up table NVM I/O FPGA I/O High speed transceiver Flash I/O SRAM Black & Das, JAP87, 6674(2000) Look Up Table Flip-Flop Input Clk Output Configurable logic block (CLB) NVM WIND/IMST - Memory tutorial - IMEC - 26 Nov Non volatile FPGA Logic Circuits I/O I/O FPGA I/O Configuration High speed transceiver Flash replace Flash and SRAM by a non volatile memory (NVM) directly embedded inside the look up table NVM I/O SRAM Look Up Table Flip-Flop replace the standard Flip-Flop by a non volatile one Input Clk Output Configurable logic block (CLB) NVM NVM WIND/IMST - Memory tutorial - IMEC - 26 Nov

32 Spin-RAM based Non-volatile Flip Flop master slave flip-flop based on spin transfer switching non volatile, instant on/off record all intermediate calc. steps if : - CMOS compatible I WR - writing speed at processor's rate (~3 GHz) e-mram could enter the CPU!!! STREP MAGLOG W. Zhao, E. Belhaire (IEF), V. Javerliac, B. Dieny (SPINTEC) P. Mazoyer, F. Jacquet WIND/IMST (ST - Microelectronics) Memory tutorial - IMEC - 26 Nov Fast sensing of MRAM status for logic circuits Sense Amplifier Black & Das, JAP87, 6674(2000) Electrical simulation W. Zhao, IEF, PhD March 2008 MTJ model (V.Javerliac et al.,mmm,2006) STMicroelectronics 90nm design kit Out Wp=0.12um Wn=0.12um R AP R P TMR=80% R(0)=8.9KΩ ~ non volatile SRAM fast reading possible writing? <100ps WIND/IMST - Memory tutorial - IMEC - 26 Nov

33 Mixed CMOS-Tunnel junctions logic WIND/IMST - Memory tutorial - IMEC - 26 Nov Outlook - the basics of magnetic recording - the basics of spin electronics - the magnetic tunnel junction - the principle of the magnetic random access memory or MRAM - spin angular momentum transfer and the Spin-RAM - towards magnetic logic chips - beyond MRAM and Spin-RAM in solid state magnetic mass storage - beyond MRAM and Spin-RAM in spin logic WIND/IMST - Memory tutorial - IMEC - 26 Nov

34 Another promising scientific breakthrough: current induced domain wall motion thick wall transfer of spin angular momentum electrons DW v r (Grollier, APL 2004 Vernier, EuroPhys Thiaville, cond-mat , ) thin wall transfer of momentum electrons DW v r Berger ( 84, 92) Tatara & Kohno (2004) WIND/IMST - Memory tutorial - IMEC - 26 Nov Current induced domain wall propagation: downscaling prospect to ensure required non volatility (Neel's model) energy barrier KV > x k B T, if V as F 2, then K ~ 1/F 2 F current induced writing of a domain wall based M-RAM : R Tunnel barrier R e - e - writing current : Ex: w = F = 90 nm, t = 10 nm, j C = 10 6 A/cm 2 I WR ~ 9 µa (standard F= 90 nm : I MAX ~ 0.5 ma/µm ) (?) scaling of the writing current density vs non volatile DW trapping??? WIND/IMST - Memory tutorial - IMEC - 26 Nov

35 One proposition of "Solid State Hard Disk" Shiftable magnetic shift register and method of using the same S.S.P. Parkin US patent 6,834,005B1 of Dec. 21, 2004 same data organization as in HD, but no moving part fast access time! domain wall speed: up to ~100m.s high data rates! WIND/IMST - Memory tutorial - IMEC - 26 Nov A new approach to magnetic storage Shiftable magnetic shift register and method of using the same S.S.P. Parkin - US patent 6,834,005B1 pub. Dec. 21, 2004 Submicrometer Ferromagnetic NOT Gate and Shift Register. Allwood, D. A. et al. Science 296, 2003 (2002) Multiple layer magnetic logic memory device Cowburn, R.P. & Allwood, D.A.. UK patent GB A (2007) magnetic stripe DW propagation wafer write head read head Information is stored in a magnetic strip, as contiguous magnetization domains. Domains are made to migrate synchronously from programming head to reading head with either an external magnetic field or a current injected in the strip (spin transfer effect). WIND/IMST - Memory tutorial - IMEC - 26 Nov

36 Russel Cowburn et al. D. Allwood et al., Science 309 (2005) 1688 storage ring (shift register with one input) 3D storage WIND/IMST - Memory tutorial - IMEC - 26 Nov Spin electronics today: a giant move towards integration Size ~ 100µm, separate R/W heads and media but first spin electronics device! size < 100nm full «integration» Longitudinal Hard Disk recording With spin valve head (1997) Spin-RAM, SONY, IEEE 2005 WIND/IMST - Memory tutorial - IMEC - 26 Nov

37 in a short span of time 1988: GMR discovered 1991: "spin valve" 1995: "practical" TMR 1997: product, SV HD readhead (IBM) years 10 years 2005: product, TMR HD read head (Seagate) 2006: product, MRAM (Freescale) : "spin transfer" predicted/observed? ) 2010: spin-ram product??? (RENESAS, NEC, SONY, Samsung, CROCUS, ) WIND/IMST - Memory tutorial - IMEC - 26 Nov Perspective: a new paradigm for spintronics electron: charge spin phase cohérence spin dependent transport in multilayers M controlling magnetization by currents (w or w/o charges) spin dependant quantum transport coherence and Quantum Information? magnetization mesoscopic spintronics from uniformly magnetized nanostructures to non colinear magnetization structures (vortex, domain walls, ) a wide field for research! materials, hybrid stacks nanotechnologies, devices nano architectures, device integration WIND/IMST - Memory tutorial - IMEC - 26 Nov