Kaushik Roy Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Transcription

1 Beyond Charge-Based Computing: STT- MRAMs Kaushik Roy Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 1

2 Failure probability Power Density (W/cm 2 ) Device Dimension Why Beyond Charge based Computing? 10µm 1µm 100nm 10nm 1nm 0.1nm 1960 Increased Process Variations, Leakage, Power Density; Less Reliability and Yield Fundamental Limit Device 1 Device 2 Channel length Process Variations Tech. generation Defects Time Life time degradation Reliability Power Density

3 Technology Trend 2003 More Moore Beyond CMOS 2020 Bulk-CMOS V G V S Gate V D Source Floating Body Drain Buried Oxide (BOX) Substrate PD/SOI Fully-depleted body V S V G Gate V D Source Drain Buried Oxide (BOX) Substrate V back FD/SOI Single gate device DGMOS FinFET Trigate Multi-gate devices Carbon nanotube Graphene TFETs III-V devices Spintronics?? Design methods to exploit the advantages of technology innovations

4 Nucleus Electron SPIN Electron is a magnet Magnetic moment m N rotation (spin) Orbital electrons Classical representation of atom S Electrons with uni-directional electron spin moments results in magnet with non-zero moment (ferro-magnets) Fe (4), Co (3) and Ni (2) : unpaired electrons per atom 5

5 Sources of Magnetic Moments in Ferromagnetic Materials Direction Characteristics in s-, p- and d- orbital's Iron Lattice Structure (body central cubic) Cobalt Lattice Structure (Hexagonal Close Pack) Incomplete 3d orbitals is the principle source of magnetic moments in transition metals

6 State Variable: Charge & Spin Spin: magnetism Charge: semiconductor electronics SPINTRONICS LARGE SCALE SYSTEMS

7 Recent Inventions Giant Magneto Resistance (GMR) 1988: Peter Grunberg, Germany Albert Fert, France 2007: Nobel Prize (a) MgO Spin Transfer Switching (STS) 1996: Slonczewski, US MgO MgO Lateral Spin Valves (Local & Non-Local) 2008: Yang, Kimura, Otani 2009: Sun MgO Free Memories: high density, stability, low read/write current, access time, zero leakage.. Logic (Boolean & Non-Boolean): Ultra low voltage switch, Neuromorphic computing, (all-spin logic no spin-charge conversion), i/p o/p isolation, zero leakage, Interconnects: Spin channel (short), Ultra low voltage swing for charge based int.

8 MOS vs. Magnets Switching Energy MOS Gate Dissipated Energy = 0.5CV 2 N*Eb N 10,000, x=40 1e-15 J / switch E b x k T B Magnet ( Collective Entity ) Dissipated Energy Eb equivalent N =1 x=40 1e-19 J / switch Life-time = 7 years Non-volatile E b x k T Theoretical switching energy of magnet is 0.1aJ << 1fJ (MOSFET) B

9 Energy Barrier Modulation: MOSFETs vs. Magnets Conventional Charge-based MOSFET (Bulk/SOI/FinFETS) Nano-Magnets with Electron Spin as State Variable The energy barrier in the active channel region can be modulated using: Doping Uniform Channel Doping Symmetric/Asymmetric Halo Doping Source Drain Doping Work Function and Material Engineering Gate Dielectric and Thickness (T OX ) Modulation t The energy barrier in magnets is defined as the product of anisotropy and volume (E B = K u2.v) The energy barrier in magnets can be modulated using: Shape and Interfacial magnetic Anisotropy (K u2 ) Volume of the nano-magnet (thickness (t) and cross-sectional area (A)) Saturation Magnetization (M SAT ) a b H Ku =4πM 2 SAT (n y-n x ) b b For =2,n x =0.32 and a n =0.90 y t

10 Changing the State of a Magnet External Magnetic Field» Current carrying wires, coils, etc.» Dipolar coupling».. Current Induced Spin-Transfer Torque (1996) 12

11 Spin-Torque Transfer Magnetic Embedded Memory

12 Current (ma) Magnetic Tunneling Junctions (MTJ) Anti-parallel orientation of magnets (AP) MgO FIXED LAYER FREE LAYER High resistance state (R AP ) Basics: Read Operation Parallel orientation of magnets (P) MgO FIXED FREE LAYER LAYER Low resistance state (R P ) R -R R P AP P TMR= 100 % Memory state is detected through difference in resistance using Sense Amplifier Electrical Characteristics of MTJ Current(P) Current(AP) slope=1/r AP Voltage (V) slope=1/r P R P =1kΩ R AP =2kΩ TMR=100 %

13 T 1 MTJ Basics: Spin-transfer torque induced write operation e e e e e e e e Electrical Current T 1 Electrical Current CoFe/Ru /CoFeB Pinned Ferromagnetic Layer (η~90%) CoFe/Ru /CoFeB MgO e e e e CoFe Tunneling Oxide Free Layer (η~50%) MgO CoFe T 2 T 2 AP P P AP e e e e e e e e P AP magnetization switching is relatively difficult than AP P due to lower spin injection efficiency of the free layer

14 1-T, 1 R STT-MRAM bit line (BL) I read read I ref bias generator word line (WL) P-> AP AP-> P write source line (SL) Key Advantages: Limitations High Write Density asymmetry (just 1 transistor per bit cell) Non-Volatility Reliability-limited write speed No Read leakage Write power optimization in un-accessed conflict cells

15 EMBEDDED MRAM PROCESS : Integrated Magnetic Process Cross-Section Single MRAM bit cell Magnetic Stack Protection Layer Back-end MRAM module Front-end CMOS module Word line Transistor common Contact to MTJ Metal 4 contact stud in via stack Magnetic Pinning Layer Reference Layer Tunneling Barrier Free Layer Source: Everspin Technologies The multilayer of an MTJ stacking is prepared using sputtering and plasma oxidation

16 Switching Current (ma) Comparison of STT MRAM and Field Based MRAM Spin Torque Switching is superior compared to Field Based Switching in scaled geometries STT: J C =1e6 A/cm2 STT: J C =5e6 A/cm2 External Field Magnet Width (nm) Spin-torque MRAM need much lower switching current at isodelay for scaled geometries

17 Bit-Cell Design using STT- MTJ

18 # of occurrences # of occurrences Normalized MTJ Resistance Current (ma) Design Challenge 1: Read and Write Failures in 1T-1R Bit-cell Structures I>I HL R P Write Failure I > I LH Applied voltage (V) Insufficient current to switch MTJ I WRITE < min (I LH, I HL ) I HL I LH READ Read Failure Current(P) Current(AP) slope=1/r AP slope=1/r P R P =1kΩ R AP =2kΩ TMR=100 % Voltage (V) Insufficient TMR to distinguish between R AP and R P Write 0 failure 0 to 1 threshold current Write 0 to 1 Write 1 to 0 Write 1 failure 1 to 0 threshold current Write current ( Χ10-3 A ) Process variations reduce memory yield σ/μ=5% in MTJ Area and MgO thickness 0 Read 1 current Read 0 current Reference current Read 1 Read 0 decision decision failure failure Read current ( Χ10-4 A )

19 # of occurrences Design Challenge 2: Read-Write Conflict MTJ Resistance (normalized) BL 2.5 WRITE 1 BL R MTJ Current (I LH ) 2 I > I HL R AP R WL Current (I HL ) R P I > I LH WL Current (I READ ) SL WRITE Applied voltage (V) Read Disturb Failure (under process variations) SL READ 400 Read 1 current Read 0 current to 0 threshold current Read 1 disturbance failure I READ and I HL have same polarity Read operation can cause unintended write (Read Disturb) Read current ( Χ10-4 A ) σ/μ=5% in MTJ Area and MgO thickness

20 Normalized Delay Design Challenge3: Stray Fields and its Impacts on MTJ Stack Aggressor MTJ Free Layer MgO MgO Aggressor MTJ Victim MTJ Aggressor MTJ Fixed Layer MgO MgO H K =75 Oe H K =100 Oe H K =150 Oe H STRAY 1.4 MgO Aggressor MTJ P to AP switching is opposed by stray magnetic field (H STRAY ) H stray (Oe) WRITE time increases for higher stray fields write failures

21 Design Challenge 4: Stochastic Switching Behavior due to Thermal Fluctuations Life-time (in years) Angular precession with different T Life-time decreases exponentially with temperature Temperature (K) Thermally induced initial magnetic oscillations are stochastic in nature (white noise) STT switching delay distribution has a longer tail, degrading memory yield Higher temperature helps in squeezing the switching delay distribution but degrades thermal stability

22 STT-MTJ Stacks: Stability, Read/Write Conflicts, Write power,..

23 STT-MRAM Design Issues WL I WR ( 1 ) Shared Source Read/Write Degeneration Current Paths SL BL V X > 0 V GS < V DD WL SL BL I WR ( 0 ) WL BL WL I WR ( 0 ) WL I RD SL BL BL SL BL SL May require access transistors to be upsized to meet I C requirements at fixed V DD Conflicting read and write current requirements Leads to excessive I WRITE for writing the opposite Limited design direction space WL SL

24 Dual Pillar MTJ Structure: Spatial and electrical isolation of MTJ read and write V DD VGND DD V DD GND T OXIDE, 1 < T OXIDE, 2 Advantages: Built-in read and write stabilities without any mutual conflict (relaxed memory design space) Lower WRITE, DISTURB and DECISION failures (Robust operation) 1T-1MTJ STT-MRAM Single transistor based data access (Uncompromised memory density) Single supply voltage READ/WRITE operation (Simplified bit-cell design) Single ended voltage sensing for data read-out (Fast and reliable sensing scheme) 29

25 Multi-terminal STT-MRAM Structures Dual-pillar Spin-Transfer Torque MRAM (DPSTT) Complementary Polarizers STT-MRAM (CPSTT) WL SL RBL Read Port Pinned Layer Tunneling Oxide BL Free Layer Tunneling Oxide Free Layer WL Pinned Layers ATxL ATxR Write Port Pinned Layer WBL Tunneling Oxide SLL SLR [1] N. N. Mojumder, K. Roy, TED vol. 59, no. 11, pp , 2012 [2] X. Fong, K. Roy, EDL vol. 34, no. 2, pp , 2013

26 Write Operations WL SL I WR ( 0 ) RBL BL I WR ( 0 ) I WR ( 1 ) T OX2 WL T OX1 I WR ( 1 ) WBL SLL SLR T OX2 > T OX1 I WR ( 0 ): V SL =0, V WL =V WBL =V RBL =V DD I WR ( 1 ): V SL =V DD, V WL =V WBL =V RBL =0 I WR ( 0 ): V SLL =0, V WL =V BL =V SLR =V DD I WR ( 1 ): V SLR =0, V WL =V BL =V SLL =V DD

27 Read / Sensing Operations WL SL I RD RBL I RDL BL I RDR WL WBL I REF = 0.5 {I RD ( 0 )+I RD ( 1 )} V WL =V DD, V SL =V WBL =0, V RBL =V READ 0 : I RD ( 0 ) > I REF 1 : I RD ( 1 ) < I REF SLL V BL =0, V WL =V DD, V SLL =V SLR =V READ 0 : I RDL > I RDR 1 : I RDL < I RDR Differential sensing Self-referencing SLR

28 Peripheral Circuitry for CPSTT Array WrData Write Driver SLL SLR SEL V DD M2 M10 V Pre REN M3 M4 M5 I READ,R M1 M7 I READ,L Sense Amplifier RCLK M6 M11 M8 V Pre M9 D D Q CLK Q Data DataB Differential sensing using latch based sense amplifier M2-M3 and M6-M7 act as cross-coupled inverters with M4-M5 and M8-M9 along their respective pulldown paths Each pull-down path goes through a different pinned layer RDEN CLK CLK Since the free layer is only parallel to one of the pinned layers, the resistance path through each pinned layer will be different SPICE simulations show >1.5GHz read speeds are possible with realistic parasitics

29 Normalized Latency Norm. Active Energy Normalized Power Comparison of 1T-1R with SRAM Last Level Caches with Similar Cache Area (2MB SRAM, 8MB STT MRAM) T 2MB SRAM 6T SRAM 1 STT: Conv. 0.8 STT:TMA 6T SRAM 18MB STT MRAM STT: (Standard) Conv. 6T SRAM 1 STT: Conv. 8MB STT MRAM (Tilted 0.8 STT:TMA Magnetic Anisotropy) 0.8 STT:TMA Leakage Leakage 0.8 Leakage Read Write Read Write Leakage Higher Latency Higher Active Energy Lower Leakage 4X higher capacity [1] S. P. Park et al, DAC

30 Instructions per Cycle System Level Implication of STT MRAM Last Level Caches Total Energy Consumption (J) T SRAM (2MB) STT: Conv. Std (8MB) STT: TMA (8MB) T SRAM (2MB) STT: Std Conv. (8MB) STT: TMA (8MB) 10 9 Cycles Avg. CU = 2.2% Max. CU = 13% Integer Floating Point SPEC 2000 Benchmarks 0 Leakage Only 2% 10% Cache Utilization (CU) Compared to SRAM cache STT MRAM caches offer Higher throughput due to larger integration density and lower cache miss rate Lower Energy due to low leakage and low utilization [1] S. P. Park et al, DAC

31 Charge Current Spin Current Charge Current NiFe Magnet1 NiFe Lateral Spin Valve Spin Current Charge Current local spin torque Spin Valves NiFe Magnet2 NiFe Vertical spin valve structure Local Spin torque Vsupply Fixed Layer Cu Free Layer Magnet1 Cu Spin Current Magnet2 Spin Non-local potential spin gradient torque μ+ μ- Free Layer switches under the influence of local spin torque injection-efficiency is determined by interface polarization, can be ~90% for injector polarity ~ 0.9

32 Non-Local STT-MRAM (Separate R/W Paths) device structure: compensate for low spininjection efficiency for non-local STT write?? θ tilt dual injectors with tilted axis anisotropy metal channel free layer MgO fixed layer use of dual injector write current enhances spin injection read non-local current efficiency by ~2X spin absorption tilted anisotropy for injectors further reduces the switching current by ~3X M. Sharad et al., DRC, 2012

33 R MTJ (k ) R MTJ (k ) RA ( - m 2 ) RA MTJ ( - m 2 ) RA MTJ ( - m 2 ) RA MTJ ( - m 2 ) Simulation Framework 30 (a) E F =2.25eV, E B =0.865eV, =0.315eV, m FM =0.748, m OX =0.462, a=3e-10, T=20K, V20 MTJ =10mV 15 Anti-parallel Parallel t MgO (nm) V MTJ (V) 0.8 V MTJ (V) (b) NEGF (AP) NEGF (P) Data 20 (AP) Data (P) NEGF (AP) NEGF (P) Data (AP) Data (P) V MTJ (V) SPICE MTJ Model (c) 30 Standard Reversed 30 Standard Reversed Time (ns) a) S. Yuasa et al., Nature Materials vol. 3, no. 12, pp , Dec b) C. J. Lin et al., IEDM, Dec. 2009, pp c) T. Kishi et al., IEDM, Dec. 2008, pp Time (ns) Device level simulation results may be calibrated to experimental data Device parameters are imported into SPICE model for circuit level simulations

34 Bit-Cell Configuration

35 Design Solutions: Circuit and Architecture Optimization Wordline (WL) Bitline (BL) Read-Wordline Write-Wordline (WL_r) (WL_w) BL Wordline (WL) Bitline (BL) R MTJ R MTJ driver transistor Sizing of driver transistor Sourceline (SL) Read- NMOS R MTJ SL Write-NMOS Sizing of read and write transistors Sourceline (SL) Stretched Write Cycle (SWC) based Architecture Optimize bit-cell for read Read : One cycle Write : Two cycle Circuit Optimization Circuit and Architecture Optimization

36 Bit Cell Write Energy (Normalized wrt 1T-1R without variations) Bit-Cell Design: Summary T-1R worst case design (under variations) 1T-1R optimized (under variations) area overhead (5.4%) area overhead (9%) 2T-1R optimized (under variations) T-1R (w/o variations) throughput reduction (3%) 1T-1R with SWC (under variations) SWC provide lowest energy for iso-failure probability with minor throughput degradation

37 Acknowledgement Swarup Bhunia, Case Western U. Anand Raghunathan, Purdue Niladri Mojumder, GF Charles Augustine, Intel Mrigank Sharad, Purdue Delian Fang, Purdue Xuanyao Fong, Purdue Sumeet Gupta, Purdue Harsha Choday, Purdue Sang-Phill Park, Intel Prof. Supriyo Datta StarNet, NRI, INDEX, SRC, Intel, NSF, Qualcomm 46