BEYOND CHARGE-BASED COMPUTING

Transcription

1 BEYOND CHARGE-BASED COMPUTING KAUSHIK ROY MRIGANK SHARAD, DELIANG FAN, KARTHIK YOGENDRA, CHARLES AUGUSTINE, GEORGE PANAGOPOULOS, XUANYAO FONG ELECTRICAL & COMPUTER ENGINEERING PURDUE UNIVERSITY WEST LAFAYETTE, IN 47906, USA

2 Why Beyond Charge based Computing? 10µm Device Dimension 1µm 100nm 10nm 1nm 0.1nm 1960 Increased Process Variations, Leakage, Power Density; Less Reliability and Yield Fundamental Limit Device 1 Device 2 Channel length Process Variations Failure probability Defects Tech. generation Time Life time degradation Reliability Power Density (W/cm 2 ) Power Density

3 Why Beyond Charge Based Computing? Traditional computing models (Boolean logic, von Neumann architectures) are highly inefficient at performing tasks that humans routinely perform, such as visual recognition, semantic analysis, and reasoning. Bio-inspired computation can outperform Von-Neumann designs in many such data processing applications if the computing model matches device architecture and the devices operated at very low voltage 3

4 Technology Trend 2003 More Moore Beyond CMOS 2020 Bulk-CMOS V G V S Gate V D Source Floating Body Drain Buried Oxide (BOX) Substrate PD/SOI Fully-depleted body V S V G Gate V D Source Drain Buried Oxide (BOX) Substrate V back FD/SOI Single gate device DGMOS FinFET Trigate Multi-gate devices Carbon nanotube Graphene TFETs III-V devices Spintronics?? Design methods to exploit the advantages of technology innovations

5 Electron SPIN Nucleus Electron is a magnet Magnetic moment m N rotation (spin) Orbital electrons Classical representation of atom S Electrons with uni-directional electron spin moments results in magnet with non-zero moment (ferro-magnets) Fe (4), Co (3) and Ni (2) : unpaired electrons per atom 5

6 Sources of Magnetic Moments in Ferromagnetic Materials Direction Characteristics in s-, p- and d- orbital's Iron Lattice Structure (body central cubic) Cobalt Lattice Structure (Hexagonal Close Pack) Incomplete 3d orbitals is the principle source of magnetic moments in transition metals

7 State Variable: Charge & Spin Spin: magnetism Charge: semiconductor electronics SPINTRONICS LARGE SCALE SYSTEMS

8 Recent Inventions Giant Magneto Resistance (GMR) 1988: Peter Grunberg, Germany Albert Fert, France 2007: Nobel Prize (a) Spin Transfer Switching (STS) 1996: Slonczewski, US MgO Lateral Spin Valves (Local & Non-Local) 2008: Yang, Kimura, Otani 2009: Sun Memories: high density, stability, low read/write current, access time, zero leakage.. Logic (Boolean & Non-Boolean): Ultra low voltage switch, Neuromorphic computing, (all-spin logic no spin-charge conversion), i/p o/p isolation, zero leakage, Interconnects: Spin channel (short), Ultra low voltage swing for charge based int.

9 MOS vs. Magnets Switching Energy MOS Gate Dissipated Energy = 0.5CV 2 N*Eb N 10,000, x=40 1e-15 J / switch E b xk T B Magnet ( Collective Entity ) Dissipated Energy Eb equivalent N =1 x=40 1e-19 J / switch Life-time = 7 years Non-volatile E b xk T Theoretical switching energy of magnet is 0.1aJ << 1fJ (MOSFET) B

10 All-Spin Based Systems 10

11 Energy Barrier Modulation: MOSFETs vs. Magnets Conventional Charge-based MOSFET (Bulk/SOI/FinFETS) Nano-Magnets with Electron Spin as State Variable The energy barrier in the active channel region can be modulated using: Doping Uniform Channel Doping Symmetric/Asymmetric Halo Doping Source Drain Doping Work Function and Material Engineering Gate Dielectric and Thickness (T OX ) Modulation t The energy barrier in magnets is defined as the product of anisotropy and volume (E B = K u2.v) The energy barrier in magnets can be modulated using: Shape and Interfacial magnetic Anisotropy (K u2 ) Volume of the nano-magnet (thickness (t) and cross-sectional area (A)) Saturation Magnetization (M SAT ) a b H Ku =4πM 2 SAT (ny -n x ) b b For =2,n x =0.32 and a n =0.90 y t

12 Changing the State of a Magnet External Magnetic Field» Current carrying wires, coils, etc.» Dipolar coupling».. Current Induced Spin-Transfer Torque (1996) 12

13 Magnetic Tunneling Junctions (MTJ) Anti-parallel orientation of magnets (AP) MgO FIXED LAYER FREE LAYER High resistance state (R AP ) Basics: Read Operation Parallel orientation of magnets (P) MgO FIXED FREE LAYER LAYER Low resistance state (R P ) R -R AP P TMR= 100 % R P Memory state is detected through difference in resistance using Sense Amplifier Current (ma) Electrical Characteristics of MTJ Current(P) Current(AP) slope=1/r AP Voltage (V) slope=1/r P R P =1kΩ R AP =2kΩ TMR=100 %

14 T 1 MTJ Basics: Spin-transfer torque induced write operation e e e e e e e e Electrical Current T 1 Electrical Current CoFe/Ru /CoFeB Pinned Ferromagnetic Layer (η~90%) CoFe/Ru /CoFeB MgO e e e e CoFe Tunneling Oxide Free Layer (η~50%) MgO CoFe T 2 T 2 AP P P AP e e e e e e e e P AP magnetization switching is relatively difficult than AP P due to lower spin injection efficiency of the free layer

15 Bit-Cell Design using STT- MTJ

16 1-T, 1 R STT-MRAM bit line (BL) I read read I ref bias generator word line (WL) P-> AP AP-> P write source line (SL) Key Advantages: Limitations High Write Density asymmetry (just 1 transistor per bit cell) Non-Volatility Reliability-limited write speed No Read leakage Write power optimization in un-accessed conflict cells

17 Design Challenge 1: Read and Write Failures in 1T-1R Bit-cell Structures Normalized MTJ Resistance I>I HL R P Write Failure I > I LH Applied voltage (V) Insufficient current to switch MTJ I WRITE < min (I LH, I HL ) Current (ma) I HL I LH READ Read Failure Current(P) Current(AP) 0.2 slope=1/r P R P =1kΩ -0.4 slope=1/r AP R AP =2kΩ -0.6 TMR=100 % Voltage (V) Insufficient TMR to distinguish between R AP and R P # of occurrences Write 0 failure Write 0 to 1 Write 1 to 0 0 to 1 threshold current 1 to 0 threshold current Write 1 failure Write current ( Χ10-3 A ) Process variations reduce memory yield # of occurrences σ/μ=5% in MTJ Area and MgO thickness 0 Read 1 current Read 0 current Reference current Read 1 Read 0 decision decision failure failure Read current ( Χ10-4 A )

18 Design Challenge 2: Read-Write Conflict WL BL R MTJ WRITE 1 Current (I LH ) Current (I HL ) MTJ Resistance (normalized) I>I HL R AP R P I>I LH WL BL R Current (I READ ) SL WRITE Applied voltage (V) Read Disturb Failure (under process variations) SL READ # of occurrences Read 1 current Read 0 current 1 to 0 threshold current Read 1 disturbance failure I READ and I HL have same polarity Read operation can cause unintended write (Read Disturb) Read current ( Χ10-4 A ) σ/μ=5% in MTJ Area and MgO thickness

19 Design Challenge3: Stray Fields and its Impacts on MTJ Stack Aggressor MTJ Free Layer Aggressor MTJ MgO H STRAY MgO Victim MTJ MgO Aggressor MTJ MgO Aggressor MTJ P to AP switching is opposed by stray magnetic field (H STRAY ) Normalized Delay MgO Fixed Layer H K =75 Oe H K =100 Oe H K =150 Oe H stray (Oe) WRITE time increases for higher stray fields write failures

20 Design Challenge 4: Stochastic Switching Behavior due to Thermal Fluctuations Angular precession with different T Life-time (in years) Life-time decreases exponentially with temperature Temperature (K) Thermally induced initial magnetic oscillations are stochastic in nature (white noise) STT switching delay distribution has a longer tail, degrading memory yield Higher temperature helps in squeezing the switching delay distribution but degrades thermal stability

21 STT-MTJ Stacks: Stability, Read/Write Conflicts, Write power,..

22 Alternative Device Structures MgO Free Layer Fixed Layer Ru MgO MgO MgO MgO MgO MgO MgO Single Barrier Ferromagneti c Free Layer (SBFF) MTJ with Tilted Magnetic Anisotropy (TMA) Single Barrier Synthetic AntiFerromagnetic Free Layer (SBSAFF) Dual Barrier Dual Barrier Ferromagnetic Synthetic Free Layer (DBFF) AntiFerromagnetic Free Layer (DBSAFF) Perpendicul ar Anisotropy Materials Dual Pillar MTJ Dual Pillar MTJ with Tilted Magnetic Anisotropy Domain Wall Memory Alternative Device designs may alleviate some of the problems related to scaling 11/20/2013 ICCAD

23 Differential Spin Hall MRAM READ MTJ1 WRITE 0 β W m1 m2 m1 and m2 are anti parallel WRITE 1 Energy efficient write Spin injection efficiency > 100 % Low resistance in write current path No tunneling barrier reliability 10X lower write energy compared to 1T1R STT MRAM MTJ1 SHM MTJ2 MgO PL FL MgO FL PL READ MTJ2 High speed differential read No need for a reference cell 2X signal margin 1.6X faster read speed compared to single ended reading Y Kim, SH Choday, K Roy, EDL 2013

24 Charge Current NiFe Magnet1 NiFe Magnet1 Lateral Spin Valve Spin Current Charge Current local spin torque Cu Spin Current Spin Valves NiFe Magnet2 NiFe Magnet2 Spin Non-local potential spin gradient torque μ+ μ Vertical spin valve structure Local Spin torque Spin Current Vsupply Fixed Layer Cu Free Layer Charge Current Free Layer switches under the influence of local spin torque injection-efficiency is determined by interface polarization, can be ~90% for injector polarity ~ 0.9

25 Non-Local STT-MRAM (Separate R/W Paths) device structure: compensate for low spininjection efficiency for non-local STT write?? θ tilt dual injectors with tilted axis anisotropy metal channel free layer MgO fixed layer use of dual injector write current enhances spin injection read non-local current efficiency by ~2X spin absorption tilted anisotropy for injectors further reduces the switching current by ~3X M. Sharad et al., DRC, 2012

26 Simulation Framework (a) RA ( - m 2 ) E F =2.25eV, E B =0.865eV, =0.315eV, m FM =0.748, m OX =0.462, a=3e-10, T=20K, V MTJ =10mV Anti-parallel Parallel t MgO (nm) (b) RA MTJ ( - m 2 ) NEGF (AP) NEGF (P) Data (AP) Data (P) V MTJ (V) SPICE MTJ Model (c) R MTJ (k ) Standard Reversed R MTJ (k ) Standard Reversed Time (ns) Time (ns) a) S. Yuasa et al., Nature Materials vol. 3, no. 12, pp , Dec b) C. J. Lin et al., IEDM, Dec. 2009, pp c) T. Kishi et al., IEDM, Dec. 2008, pp Device level simulation results may be calibrated to experimental data Device parameters are imported into SPICE model for circuit level simulations

27 Differential Spin Hall MRAM (Roy) Y Kim, SH Choday, K Roy, EDL 2013 READ MTJ1 m1 WRITE 0 WRITE 1 β W m2 m1 and m2 are anti parallel MTJ1 SHM MTJ2 MgO PL FL MgO FL PL READ MTJ2 Energy-efficient write: Spin injection efficiency > 100%. Low-resistance in write current path. No tunneling barrier reliability issue. 10X lower write energy compared to 1T1R STT MRAM High-speed differential read: No need for a reference cell. 2X signal margin. 1.6X faster read speed compared to single ended reading

28 Read Only Memory Embedded MRAM (Roy) Cell Area = max(0.5w N +4λ, 14λ) 16λ Via for ROM Programming MTJ Active Row (i-1) Poly Row (i) M1 M2 I READ1 I READ0 ROM Data BL0 BL1 Row (i+1) Pre-charge circuit Col (i-1) Col (i)col (i+1) M3 SL M1 BL0 M3 BL1 M3 WL - Poly WL1 WL2 WL3 SL SA1 V REF1 - A + - A + V OUT1 Lee, Fong, Roy, Rom Embedded MRAM, EDL 2013 V REF0 V OUT0 SA0 Read-Only Memory (ROM) may be embedded with little area overhead. Embedded ROM can be used to accelerate function evaluations (e.g.math.) No performance penalty to Random Access Memory (RAM) mode.

29 STT MRAM: Last Level Cache (Roy) Drop in replacement of SRAM with STT MRAM for LLC leads to improvement in capacity and leakage, but higher latency and active energy. Park, Raghunathan Roy; DAC 12 Normalized Latency Norm. Active Energy Higher Latency Read Higher Active Energy Read Write Write SRAM STT-MRAM Circuit and architectural techniques can greatly improve the efficiency of spin based caches. Normalized Power MB 6T SRAM Leakage Lower Leakage 8MB STT MRAM 8MB STT MRAM (Tilted Magnetic Anisotropy)

30 STT-MRAM: LAST LEVEL CACHE Drop-in replacement of SRAM with STT- MRAM for LLC leads to improvement in capacity and leakage, but higher latency and active energy Circuit and architectural techniques can greatly improve the efficiency of spinbased caches Normalized Latency Norm. Active Energy Higher Latency Read Higher Active Energy Read Write Write Normalized Power Leakage Lower Leakage SRAM Park, Raghunathan, Roy; DAC 12 STT-MRAM Annual Review, Sept 26, MB 6T SRAM 8MB STT MRAM 8MB STT MRAM (Tilted Magnetic Anisotropy)

31 Normalized Latency Comparison of 1T-1R with SRAM Last Level Caches with Similar Cache Area (2MB SRAM, 8MB STT MRAM) Read 2MB 6T SRAM Write Norm. Active Energy 8MB STT MRAM (Standard) Read 0 Write 8MB STT MRAM (Tilted Magnetic Anisotropy) Normalized Power Leakage Higher Latency Higher Active Energy Lower Leakage 4X higher capacity [1] S. P. Park et al, DAC

32 System Level Implication of STT MRAM Last Level Caches Instructions per Cycle T SRAM (2MB) STT: Conv. Std (8MB) STT: TMA (8MB) Integer Floating Point SPEC 2000 Benchmarks Total Energy Consumption (J) T SRAM (2MB) STT: Std Conv. (8MB) STT: TMA (8MB) 10 9 Cycles Avg. CU = 2.2% Max. CU = 13% 0 Leakage Only 2% 10% Cache Utilization (CU) Compared to SRAM cache STT MRAM caches offer Higher throughput due to larger integration density and lower cache miss rate Lower Energy due to low leakage and low utilization [1] S. P. Park et al, DAC

33 Boolean/Non-Boolean Computing with Spin Torque Transfer Devices

34 Spin-Torque Experiments m1 m2 Nano-magnets in a Lateral Spin Valves (LSV) can interact and switch through spin-torque Non-local STT switching in LSV can be employed to realize All Spin Logic Device (ASLD) metal channel LSV with local spin torque switching m1 m2 Low-current, high-speed domain-wall motion can be achieved in scaled ferromagnetic nano-strips with perpendicular magnetic anisotropy (PMA) LSV with non local spin torque switching domain 1 metal channel domain wall domain 2 Such low energy DW motion can be employed in logic computation Spin torque induced domain wall motion

35 Spin Majority Gates using ASL (C) (A) Non local spin current (OUT) (B) Spin majority gate with odd number of inputs can be realized using ASL 35

36 Compact Full Adder: Non Boolean Logic Option1: with standard NAND logic (44 magnets) Option2: functionality enhanced NB logic (5 magnets) Inputs: A, B and C Outputs: Sum and Cout Sum A B C C out =AB+AC+BC=M (A,B,C) C out A B C Sum Truth Table for SUM C. Augustine et al., NanoArch,

37 Boolean Logic Using Spin Torque Devices low voltage, spin-torque switching in spin valves can possibly achieve lower switching energy than CMOS Compact All Spin Logic gates can achieve higher area density Full-Adder based on All Spin Logic CMOS inverter E STT 1mV spin-torque inverter m1 (10x10x1 nm 3 ) Majority Gate A B C OUT m2 10µA X 1mV X 1ns = ~ 1/25 E CMOS 50µA X 1V X 5ps

38 Switching Energy vs. Speed Iswitch~ 1/ Tswitch Eswitch = Tswitch x Iswitch x Vswitch E STT 30µA X 1mV X 0.5ns = = 1/25 E CMOS 50µA X 1V X 5p E STT 300µA X 10mV X 50ps = = 4 E CMOS 50µA X 1V X 5p low speed STT switching high-speed STT switching For an isolated logic gate switching energy increases linearly with switching speed

39 2-Phase Pipelining for Enhanced Performance Non-volatile nanomagnets facilitate pipelining simply by the use of clocked power supply No extra latches needed! M. Sharad, K. Roy, ISQED, 2013

40 2-Phase Pipelining for Enhanced Performance For a logic block with N-magnets in series : Eswitch = Tswitch x Iswitch x Vswitch Eswitch = N(Tswitch x Iswitch x Vswitch) Where T logic =N T switch For fine-grained pipelining: T logic_pl = T switch_pl Hence, T switch_pl = T switch /N E switch_pl = E switch /N Reduction in switching energy proportional to the number of logic stages in a pipeline can be achieved

41 2-Phase Pipe-lined 8-bit Multiplier (Carry-save) V ds Clocked power supply requires transistors which increase the required voltage supply

42 2-Phase Pipelining: Design Optimization Supply voltage needed for pipelined spin-logic reduces with Area_Tx, vds Higher transistor width and lower supply voltage leads to reduction in static power but the dynamic clocking power increases.

43 2-Phase Pipe-lining: Design Optimization Area benefit of pipelining over 15nm CMOS design reduces with increasing Tx area for spin logic. Power consumption of pipelined design reduces with increasing Tx area It reaches a saturation point due to increase in dynamic power

44 2-Phase Pipelining: Design Trade-off Minimum size clocking transistors require large V ds and hence overall power consumption can be high Area of spin logic block can be traded off (by using larger clocking transistors) to achieve larger power saving.

45 3-D FOR HIGH DENSITY AND LOW POWER COMPUTATION BLOCKS 3-D spin logic can be constructed by stacking 2-D layers along the vertical direction. All the layers in the vertical direction are supplied current using the same CMOS transistors. Vss Vds ~Vss M. Sharad, K. Roy, ISQED, 2013

46 3-D FOR HIGH DENSITY AND LOW POWER COMPUTATION BLOCKS Vds Vds Due to low resistance of the metallic vias, the current injection per magnet remains almost the same for a given transistor width and supply voltage, even when multiple layers are stacked.

47 3-D FOR HIGH DENSITY AND LOW POWER COMPUTATION BLOCKS Staking N layers reduces the effective power consumption by a factor of N For a given number of stacks, larger size of clocking transistors can be used to lower the supply voltage and hence the static power

48 Non-Boolean/Neuromorphic Computing with Spin Devices M. Sharad, K. Roy; TNANO 2011, DAC 2012, DRC 2012, IEDM 2012

49 Non-Boolean & Neuromorphic Computing Traditional computing models (Boolean logic, von Neumann architectures) are highly inefficient at performing tasks that humans routinely perform, such as visual recognition, semantic analysis, and reasoning. Bio-inspired computation can outperform Von-Neumann designs in many such data processing applications 49

50 Hardware Implementation of Neural Networks Artificial Neural Network Unit Conventional mapping of ANN functional units I 1 Thresholding (comparator) w 1 I 2 I n w 2 w n Integrate & Fire Neuron Integration ( integrator/ accumulator) Multiplication ( digital/ analog multiplier) Digital designs consume large area whereas analog designs provide power hungry solutions. Hence, there is need to match the characteristics of the devices to the computing models to 50 provide drastic improvements in efficiency.

51 synapses mathematical model for neuron-synapse Artificial Neural Networks V 2 V 1 w 2 w 1 low-impedance, fixed-voltage node V 3 w 3 - V opamp ref Analog-CMOS implementation of Neuron V supply ~ 1V, bias current ~10-100µA switching-speed > ns + ~10mV V 1 V 2 V 3 w 1 w 2 w 3 Spin Neuron V supply ~ 10mV switching-speed ~ 1ns free-layer: 20x20x2 critical current : few µa spin-polarizer, MTJ, linear MOS, memristor synapses Sharad, Roy; TNANO 12; Sharad, Roy, DAC, 2012 Sharad, Roy, IEDM, 2012 Sharad, Roy, IJCNN, 2012 Low-impedance, current-mode STT-switches can provide compact and energyefficient mapping for analog thresholding operation of a neuron. Spin neurons with spin/charge based synapses can facilitate the design of ultra low power neuromorphic hardware for non-boolean data processing.

52 Lateral Spin Valve with Decoupled Read-Write Path : Non-local Spin Injection input magnet (I) MTJ m 3 m 1 m 2 (D) channel lead (L) Read-write decoupling in LSV s facilitates ultra low voltage switching MTJ interface allows dynamic read operation with ~zero static power dissipation

53 Lateral Spin Valve with Decoupled Read- Write Path: Local Spin Injection input magnet (I) lead (L) (D) m 3 m 1 m 2 channel This structure employs local spin injection, can achieve higher injection efficiency apart from read-write decoupling An extended read-port is used for sensing, while write -current is injected into the output lead through the magnet Small dimension of m 2 insures mono-domain behavior, despite the read extension

54 Bipolar Spin Neuron Using Lateral Spin Valve Device Structure Device operation The neuron device essentially acts as an ultra low voltage current comparator and can be employed to perform analog-mode computation

55 Neuron Models Using Domain Wall Magnets 3x20nm 2 Properties of DWM favorable for high-speed, low current switching: Scaling (DW width as well as thickness) reduces the critical current for DW-motion [2, 4] PMA device achieve significantly lower critical current density ~10 6 A/cm 2 [4] Lower saturation magnetization and higher coercive field can achieve faster switching [1] Non-volatility can be sacrificed for high speed computing to further reduce the switching current [1] Duc-The Ngo et al.," arxiv preprint arxiv: (2011). [2] K. Ikeda et al., " Applied physics express 4.9 (2011): [3] C. K. Lim et al." Applied physics letters (2004): [4] S. Fukami,, et al IEEE Symp. on VLSI Tech., 2009.

56 Unipolar Domain Wall Neuron D d1 d2 I read current d3 free-domain L= 40nm A=3x20nm 2 write current G A thin and short PMA DWM free-layer can be switched with a small current ~1 µa within 1ns Such a magneto-metallic device can be used to perform ultra low voltage and low energy current-mode summation and thresholding, like a neuron

57 Bipolar Domain Wall Neuron fixed-domains junction free-domain 1-D multi-domain model BDWN can compare the input currents received through the two input domains The resolution is determined by the critical switching current density for DW nano-strip

58 Communication between Neurons Reference MTJ latch o/p (a) receiving neuron (b) CMOS latch detects the state of neuron-mtj without static current injection Deep-triode current source (DTCS) transistor driven by an output latch transmits current mode signal to receiving neurons Computation current flows across a terminal voltage of V

59 Communicating Neurons Neurons can be interconnected using weighted DTCS (Deep Triode Current Source) transistors. latch V ~20mV Depending upon the polarity of inter-neuron weight, output of a source neuron connects to one of the inputs of the receiving neuron. Current-mode, inter-neuron signaling takes place through DTCS transistors operating at ~20mV drain-to-source voltage resulting in low computation power

60 Programmable Synapses: Memristors/PCM input S+ S S+ S synapse V ~20mV gnd Memristors/PCM/DWM/ can be used for realizing low power neuromorphic computation array using bipolar spin neuron The magneto-metallic neurons facilitate input voltage levels of ~20mV resulting in low computation power

61 Synapse: Domain Wall Magnet A DWM consists of opposite polarity domains separated by a Non-magnetic region call the domain wall which can be moved by charge injection/ magnetic field

62 Device level Programmability using Domain Wall Magnet as Synapse Neuron with small number of programmable DWM inputs can be employed to realize configurable data processing array of cellular neurons

63 Drawing Analogy with Biological Neural Network!

64 DWM Based Neuron SynapseUnit: Modeling Relative spin potential in the 2 D channel for neuron with 24 input synapses and charge current ~10µA per synapse channel spin potential Neuron is simulated using self consistent solution of 2 D spin transport in channel and LLG for magnets 64

65 Application Examples

66 Example : Ultra Low Power SAR-ADC logic Vin V+ V V+ V binary weighted transistors DAC) DAC SAR I in V in I in MTJ SAR logic analog input comparator V SAR ADC employs recursive evaluation akin to CNN equation and hence can be implemented using the bipolar spin neuron

67 Ultra low energy Analog signal acquisition and processing A u ij B cell state equation for Discrete-Time CNN x ( n) kl ij Ai (, j; k, l). y ( n) ( k, l) N ( i, j) ( k, l ) N ( i, j) B(, i j; k, l). u ( n) (, i j) kl 1 if xij ( n 1) 0 0 if xij ( n 1) 0 X(n) : cell state at n th time step A: 3x3 feedback template B: 3x3 input template U(n) :3x3 neighborhood input at T= n Z : cell bias; y(n): cell output at T=n Hardware based on Cellular neural networks can be employed in several image processing applications y ( n) f '( x ( n 1)) ij ij z

68 Example : Ultra Low Power SAR-ADC logic SAR x ( n) kl ij Ai (, j; k, l). y ( n) ( k, l) N ( i, j) =0 for k i, l j Bi (, j; k, l). u ( n) (, i j) ( k, l) N ( i, j) kl z =0 for k i, l j DAC analog input comparator SAR ADC employs recursive evaluation akin to CNN equation and hence can be implemented using the bipolar spin neuron

69 Ultra low energy Analog Signal Acquisition and Processing: Performance

70 Spin Based Neuron for Cross-Bar Neural Network I 1 I 2 w 1 w 2 I n w n Integrate & Fire Neuron???? CMOS Neurons?

71 Neural Computing With Spin Neurons and Resistive Crossbar Memory The spin based neuron unit achieves ~100x improvement in power consumption for cross bar ANN architecture Based on memristor/pcm

72 Interconnects

73 STT based Energy-Efficient Global Interconnects Motivation: Global Interconnects like data-buses and memory bit-lines can account for more than 90% power for on-chip memory Emerging CMPs may dissipate ~50% power for global communication among memory and multiple processors Technology/circuit solutions: On-chip transmission line CMOS Current-mode interconnects Low voltage swing Optical, plasmonic, graphene, CNT Our goals and approaches: Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to highspeed, low-voltage current-mode switches based on nano-scale magnets. NRI Annual Review, Nov, 8, 2012 We propose and analyze spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show up to two order of magnitude higher energy-efficiency 73

74 Unipolar Domain Wall Switch for Interconnect clk V spin I read Ref. MTJ charge V out I in UDWS (charge spin) Unipolar Domain-Wall Switch DWS as a trans-impedance converter DWM motion (with SHE assist can be used to realize a two-terminal current mode STT switch Such a switch can convert an ultra-low voltage current-mode input signal into full swing output voltage in two steps: charge to spin conversion through DW-motion, followed by spin-to charge conversion through MTJ Annual Review, Sept 26,

75 m3 oxide Interconnects Using Spin-Torque Switches 3nm d3 d2 DW 60nm data data V+ V M1 M2 I in Cu-interconnect spin-switch reference MTJ gnd DW V- V 20nm d1 d2 d3 d1 transmitter receiver (a) (b) signaling-current Interconnect design using domain wall switch Global interconnects may account for large portions of total power in future processors. Emerging STT phenomena may facilitate highspeed (100fs), low-voltage current-mode magnetswitching along with efficient transimpedance conversion. V o V d V For 2Gbps signaling over a 10mm on chip interconnect: Conventional CMOS: Voltage mode: 0.5CV 2 = 2.5pfx = 150fJ Current-mode: 90fJ S. Lee et al., ISSCC 2013 Spintronic Current-mode: E signaling = I switch T bit V + I MTJ V MTJ T bit + T bit (P inverter+ P driver) = (20µA x 0.5ns x 100mV ) +(0.7µA x 0.6V x 0.5ns) + (0.5ns x 0.7µW) ~1fJ Sharad, Roy, EDL., 2013 Sharad, Roy, IEDM, 2013 STT switches can be employed for ultra-low energy and compact current mode global interconnects Annual Review, Sept 26,

76 Device Circuit Co Simulation Framework cellular neural network feed forward network cross bar network We employ Device Circuit Architecture Co Simulation Framework to evaluate the performance of spin based heterogeneous neuromorphic architectures

77 MODELING, SIMULATION, AND EVALUATION FRAMEWORK Boolean Computing Architecture-level Models Memory Arrays, Logic-in-memory, Cores, Interconnect network Non Boolean Computing Memory Cell libraries Performance, Energy, Reliability Models SPICE level Circuit Models for Primitives Logic Primitives, Memory Bit cells, Non Boolean Primitives, Interconnects Atomistic / Device Simulations NRI Annual Review, Nov, 8, 2012 MTJ w R Lateral Spin Valve DWM Dual-pillar MTJ Predictive modeling infrastructure will be co-developed with theme 4 2/17/2014 C-SPIN Kickoff Meeting 77

78 Summary Spin torque memories for on chip applications are becoming a reality Spin torque devices such as LSVs and DWMs show potential for class of applications that CMOS is not efficient at implementing such as neuromorphic designs, associative computing, semantic analysis, etc. Potential for large improvement in energy consumption

79 References (mostly our work) [1] M. Sharad, G. Panagopoulos and K. Roy, Spin Neuron for Ultra Low Power Computational Hardware, DRC, [2] M. Sharad, Spin-Based Neuron Model with Domain Wall Magnet as Synapse, IEEE Transaction on Nanotechnology, 2012 [3] M. Sharad, C. Augustine, G. Panagopoulos and K. Roy, Cognitive Computing with Spin Based Neural Networks, DAC [4] M. Sharad, C. Augustine, G. Panagopoulos and K. Roy, Spin Based Neuron-Synapse Unit for Ultra Low Power programmable Computational Networks, IJCNN [5] M. Sharad, C. Augustine, G. Panagopoulos and K. Roy, Ultra Low Energy Analog Signal Processing Using Spin-Based Neurons, Nanoarch, [6] M. Sharad et. al, Spin-Based Neuron Model with Domain Wall Magnet as Synapse, IEEE Transaction on Nanotechnology, 2012, arxiv.org. [7] M. Sharad et. al, Ultra Low Energy Analog Signal Processing Using Spin Neurons Based on Nano Magnets, 2012, arxiv.org. [8] M. Sharad et. al, Proposal for Neuromorphic Hardware Using Spin Devices, 2012, arxiv.org [9] Behin-Ain et. al., "Proposal for an all-spin logic device with built-in memory", Nature Nanotechnology 2010 [10] C. Augustine et al, Low-Power Functionality Enhanced Computation Architecture Using Spin-Based Devices, NanoArch, 2011 [11] C. Augustine et al., A Self-Consistent Simulation Framework for Spin-Torque Induced Domain Wall Propagation, IEDM, 2011 [12] Kimura et. al., "Switching magnetization of a nanoscale ferromagnetic particle using nonlocal spin injection. Phys. Rev. Lett. 2006

80 Acknowledgement Niladri Mojumder, GF Charles Augustine, Intel Mrigank Sharad, Purdue Delian Fang, Purdue Xuanyao Fong, Purdue Sumeet Gupta, Purdue Harsha Choday, Purdue Sang-Phill Park, Intel Prof. Supriyo Datta Prof. Swarup Bhunia, Case Western U. Prof. Anand Raghunathan, Purdue StarNet, NRI, INDEX, SRC, Intel, NSF, Qualcomm 80