BEYOND CHARGE-BASED COMPUTING: STT-MRAMS

Transcription

1 BEYOND CHARGE-BASED COMPUTING: STT-MRAMS KAUSHIK ROY XUANYAO FONG, CHARLES AUGUSTINE, GEORGE PANAGOPOULOS, YUSUNG KIM, KONWOO KWON, HARSHA CHODAY, MRIGANK SHARAD, ANAND RAGHUNATHAN ELECTRICAL & COMPUTER ENGINEERING PURDUE UNIVERSITY WEST LAFAYETTE, IN 47906, USA

2 Why Beyond Charge based Computing? 10µm Device Dimension 1µm 100nm 10nm 1nm 0.1nm 1960 Increased Process Variations, Leakage, Power Density; Less Reliability and Yield Fundamental Limit Device 1 Device 2 Channel length Process Variations Failure probability Defects Tech. generation Time Life time degradation Reliability Power Density (W/cm 2 ) Power Density

3 Why Beyond Charge Based Computing? Traditional computing models (Boolean logic, von Neumann architectures) are highly inefficient at performing tasks that humans routinely perform, such as visual recognition, semantic analysis, and reasoning. Bio-inspired computation can outperform Von-Neumann designs in many such data processing applications if the computing model matches device architecture and the devices operated at very low voltage 4

4 2003 Technology Trend More Moore Beyond CMOS 2020 Bulk-CMOS V G V S Gate V D Source Floating Body Drain Buried Oxide (BOX) Substrate PD/SOI Fully-depleted body V S V G Gate V D Source Drain Buried Oxide (BOX) Substrate V back FD/SOI Single gate device DGMOS FinFET Trigate Multi-gate devices Carbon nanotube Graphene TFETs III-V devices Spintronics?? Design methods to exploit the advantages of technology innovations

5 Sources of Magnetic Moments in Ferromagnetic Materials Direction Characteristics in s-, p- and d- orbital's Iron Lattice Structure (body central cubic) Cobalt Lattice Structure (Hexagonal Close Pack) Incomplete 3d orbitals is the principle source of magnetic moments in transition metals

6 State Variable: Charge & Spin Spin: magnetism Charge: semiconductor electronics SPINTRONICS LARGE SCALE SYSTEMS

7 STT-Devices Giant Magneto Resistance (GMR) 1988: Peter Grunberg, Germany Albert Fert, France 2007: Nobel Prize (a) Spin Transfer Switching (STS) 1996: Slonczewski, US MgO Lateral Spin Valves (Local & Non-Local) 2008: Yang, Kimura, Otani Memories: high density, stability, low read/write current, access time, zero leakage.. Logic (Boolean & Non-Boolean): Ultra low voltage switch, Neuromorphic computing, (all-spin logic no spin-charge conversion), i/p o/p isolation, zero leakage, Interconnects: Spin channel (short), Ultra low voltage swing for charge based int.

8 MEMORIES Prof. Kaushik Purdue Univ.

9 The Memory Hierarchy 11

10 Memory Speed Storage type Access time Relative access time L1 cache 0.5 ns Blink of an eye L2 cache 7 ns 4 seconds 1MB from RAM 0.25 ms 5 days 1MB from SSD 1 ms 23 days HDD seek 10 ms 231 days 1MB from HDD 20 ms 1.25 years 12

11 THE CASE FOR SPINTRONIC ON-CHIP MEMORIES The combination of endurance, speed, non-volatility and density make spintronic memories suitable for on-chip applications Source: Toshiba Corp., IEDM 2012

12 CACHE MEMORIES: CMOS Prof. Kaushik Purdue Univ.

13 6-transistor CMOS SRAM Cell WL V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL

14 CMOS SRAM Analysis (Read) WL BL V DD M 4 Q = 0 Q = 1 M 6 M 5 BL V DD M 1 V DD V DD C bit C bit

15 CMOS SRAM Analysis (Write) V DD WL M 4 Q = 0 M 6 M 5 Q = 1 M 1 V DD BL = 1 BL = 0

16 Memory Array

17 COLUMN SELECTION IN MEMORY WLx MC HS HS HS MC HS HS HS MC HS HS HS (a) Half selection during read/write operation in an SRAM array MC HS CELLS TO READ or WRITE HALF SELECTED CELLS (PSEUDO READ) WLx MC MC MC (b) No half selection problem in an STT-MRAM array Applicable to read and write operations in cache Identification of column address is important

18 Leakage Power in Cache Cache Utilization 30% of 30% L1 of Cache L1 Power 80% of L2 Cache 0.13µm process Cache is large leakage power consuming block in a high performance processor Source: Intel Solution : Put idle part of the cache in low leakage mode Prof. Kaushik Purdue Univ.

19 CACHE MEMORIES: NOISE MARGIN Prof. Kaushik Purdue Univ.

20 Transistor Leakage Across Different Dies Number of dies (150nm CMOS Measurements, 110 C) nominal corner worst-case corner 0 Source: Intel Normalized IOFF Substantial variation in leakage across dies 4X variation between nominal and worst-case leakage Performance determined at nominal leakage Robustness determined at worst-case leakage Prof. Kaushik Purdue Univ.

21 Random Dopant Fluctuation Global and Local Variations V t LOCAL LOCAL intra-die Vt GLOBAL GLOBAL Source: Intel inter-die V V V t t GLOBAL t LOCAL Prof. Kaushik Purdue Univ.

22 Parametric Failures: Read V TRIPRD V L = 1 NL NR BL BR Source: Intel + AXL PL - WL V R = 0 PR P P V V - + RF READ TRIPRD V READ WL V R =V READ AXR Time -> Read failure => Flipping of Cell Data while Reading Voltage Voltage WL V L Time -> V R V L Prof. Kaushik Purdue Univ.

23 Parametric Failures in SRAM WL AXL PL PR 1 0 NL NR AXR BL Source: Intel High-Vt Low-Vt Parametric failures Read Failures Write Failures Access Failures Hold Failures BR Read SNM (6T vs. 10T) Hold Noise Margin Read Noise Margin Write Margin Parametric failures can degrade SRAM yield Prof. Kaushik Purdue Univ.

24 Other SRAM Bit-Cells: Separating Read/Write WL WL WL BL 5T I. Calson et. al., ESSCIRC05 BL 6T BR BL BR W 7T K. Takeda et. al., ISSCC05 RWL RWL WWL WWL WBL WBR 8T (Register File) L. Chang et. al., VLSI Tech. 05 RBR WBL WBR 10T B. Calhoun et. al., ISSCC06 5T, 8T, 10T cells single ended. 8T/10T decoupled read and write operation. No in built process variation tolerance RBR Prof. Kaushik Purdue Univ.

25 STT MRAM: ON CHIP MEMORY Prof. Kaushik Purdue Univ.

26 Recent Inventions Giant Magneto Resistance (GMR) 1988: Peter Grunberg, Germany Albert Fert, France 2007: Nobel Prize (a) Spin Transfer Switching (STS) 1996: Slonczewski, US MgO Lateral Spin Valves (Local & Non-Local) 2008: Yang, Kimura, Otani 2009: Sun Memories: high density, stability, low read/write current, access time, zero leakage.. Logic (Boolean & Non-Boolean): Ultra low voltage switch, Neuromorphic computing, (all-spin logic no spin-charge conversion), i/p o/p isolation, zero leakage, Interconnects: Spin channel (short), Ultra low voltage swing for charge based int.

27 Energy Barrier Modulation: MOSFETs vs. Magnets Conventional Charge-based MOSFET (Bulk/SOI/FinFETS) Nano-Magnets with Electron Spin as State Variable The energy barrier in the active channel region can be modulated using: Doping Uniform Channel Doping Symmetric/Asymmetric Halo Doping Source Drain Doping Work Function and Material Engineering Gate Dielectric and Thickness (T OX ) Modulation t The energy barrier in magnets is defined as the product of anisotropy and volume (E B = K u2.v) The energy barrier in magnets can be modulated using: Shape and Interfacial magnetic Anisotropy (K u2 ) Volume of the nano-magnet (thickness (t) and cross-sectional area (A)) Saturation Magnetization (M SAT ) a b H Ku =4πM 2 SAT (ny -n x ) b b For =2,n x =0.32 and a n =0.90 y t

28 Changing the State of a Magnet External Magnetic Field» Current carrying wires, coils, etc.» Dipolar coupling».. Current Induced Spin-Transfer Torque (1996) 35

29 Magnetic Tunneling Junctions (MTJ) Anti-parallel orientation of magnets (AP) MgO FIXED LAYER FREE LAYER High resistance state (R AP ) Basics: Read Operation Parallel orientation of magnets (P) MgO FIXED FREE LAYER LAYER Low resistance state (R P ) R -R AP P TMR= 100 % R P Memory state is detected through difference in resistance using Sense Amplifier Current (ma) Electrical Characteristics of MTJ Current(P) Current(AP) slope=1/r AP Voltage (V) slope=1/r P R P =1kΩ R AP =2kΩ TMR=100 %

30 T 1 MTJ Basics: Spin-transfer torque induced write operation e e e e e e e e Electrical Current T 1 Electrical Current CoFe/Ru /CoFeB Pinned Ferromagnetic Layer (η~90%) CoFe/Ru /CoFeB MgO e e e e CoFe Tunneling Oxide Free Layer (η~50%) MgO CoFe T 2 T 2 AP P P AP e e e e e e e P AP magnetization switching is relatively difficult than AP P due to lower spin injection efficiency of the free layer

31 1-T, 1 R STT-MRAM bit line (BL) I read read I ref bias generator word line (WL) P-> AP AP-> P write source line (SL) Key Advantages: High Density (just 1 transistor per bit cell) Non-Volatility No leakage power in un-accessed cells No half-select problem Limitations: Write asymmetry Reliability limited write speed Write power Read/write conflict

32 EMBEDDED MRAM PROCESS : Integrated Magnetic Process Cross-Section Single MRAM bit cell Magnetic Stack Protection Layer Back-end MRAM module Front-end CMOS module Word line Transistor common Contact to MTJ Metal 4 contact stud in via stack Magnetic Pinning Layer Reference Layer Tunneling Barrier Free Layer Source: Everspin Technologies The multilayer of an MTJ stacking is prepared using sputtering and plasma oxidation

33 Bit-Cell Design using STT- MTJ

34 Design Challenge 1: Read and Write Failures in 1T-1R Bit-cell Structures Normalized MTJ Resistance I>I HL R P Write Failure I > I LH Applied voltage (V) Insufficient current to switch MTJ I WRITE < min (I LH, I HL ) Current (ma) I HL I LH READ Read Failure Current(P) Current(AP) 0.2 slope=1/r P R P =1kΩ -0.4 slope=1/r AP R AP =2kΩ -0.6 TMR=100 % Voltage (V) Insufficient TMR to distinguish between R AP and R P # of occurrences Write 0 failure Write 0 to 1 Write 1 to 0 0 to 1 threshold current 1 to 0 threshold current Write 1 failure Write current ( Χ10-3 A ) Process variations reduce memory yield # of occurrences σ/μ=5% in MTJ Area and MgO thickness 0 Read 1 current Read 0 current Reference current Read 1 Read 0 decision decision failure failure Read current ( Χ10-4 A )

35 Design Challenge 2: Read-Write Conflict WL BL R MTJ WRITE 1 Current (I LH ) Current (I HL ) MTJ Resistance (normalized) I>I HL R AP R P I>I LH WL BL R Current (I READ ) SL WRITE Applied voltage (V) Read Disturb Failure (under process variations) SL READ # of occurrences Read 1 current Read 0 current 1 to 0 threshold current Read 1 disturbance failure I READ and I HL have same polarity Read operation can cause unintended write (Read Disturb) Read current ( Χ10-4 A ) σ/μ=5% in MTJ Area and MgO thickness

36 Design Challenge3: Stray Fields and its Impacts on MTJ Stack Aggressor MTJ Free Layer Aggressor MTJ MgO H STRAY MgO Victim MTJ MgO Aggressor MTJ MgO Aggressor MTJ P to AP switching is opposed by stray magnetic field (H STRAY ) Normalized Delay MgO Fixed Layer H K =75 Oe H K =100 Oe H K =150 Oe H stray (Oe) WRITE time increases for higher stray fields write failures

37 Design Challenge 4: Stochastic Switching Behavior due to Thermal Fluctuations Angular precession with different T Life-time (in years) Life-time decreases exponentially with temperature Temperature (K) Thermally induced initial magnetic oscillations are stochastic in nature (white noise) STT switching delay distribution has a longer tail, degrading memory yield Higher temperature helps in squeezing the switching delay distribution but degrades thermal stability

38 STT-MTJ Stacks: Stability, Read/Write Conflicts, Write power,..

39 STT-MRAM Design Issues WL I WR ( 1 ) Shared Source Read/Write Degeneration Current Paths SL BL V X > 0 V GS < V DD WL SL BL I WR ( 0 ) WL BL WL I WR ( 0 ) WL I RD SL BL BL SL BL SL May require access transistors to be upsized to meet I C requirements at fixed V DD Conflicting read and write current requirements Leads to excessive I WRITE for writing the opposite Limited design direction space WL SL

40 Four Types of STT-MTJ Stacks Memory performance metrics: Writability, Readability and Stability (a) MgO Free Layer Fixed Layer Ru MgO (b) (c) MgO (d) MgO MgO MgO MgO Single Barrier Ferromagnetic Free Layer (SBFF) Dual Barrier Single Barrier Ferromagnetic Synthetic Free Layer (DBFF) AntiFerromagnetic Free Layer (SBSAFF) Dual Barrier Synthetic AntiFerromagnetic Free Layer (DBSAFF) Writability Readability Stability Augustine et al., TED 58, 12,

41 Bit-Cell Configuration

42 Design Solutions: Circuit and Architecture Optimization Wordline (WL) Bitline (BL) Read-Wordline (WL_r) Write-Wordline (WL_w) BL Wordline (WL) Bitline (BL) R MTJ R MTJ driver transistor Sourceline (SL) Sizing of driver transistor Read- NMOS R MTJ SL Write-NMOS Sizing of read and write transistors Sourceline (SL) Stretched Write Cycle (SWC) based Architecture Optimize bit-cell for read Read : One cycle Write : Two cycle Circuit Optimization Circuit and Architecture Optimization

43 Bit-Cell Design: Summary Bit Cell Write Energy (Normalized wrt 1T-1R without variations) T-1R worst case design (under variations) 1T-1R (w/o variations) 1T-1R optimized (under variations) area overhead (5.4%) area overhead (9%) 2T-1R optimized (under variations) throughput reduction (3%) 1T-1R with SWC (under variations) SWC provide lowest energy for iso-failure probability with minor throughput degradation Augustine et al., IEEE Sensors J. 12, 4, 2012

44 Other MTJ Configurations: Multi-Terminal

45 Multi-terminal STT-MRAM Structures Dual-pillar Spin-Transfer Torque MRAM (DPSTT) Complementary Polarizers STT-MRAM (CPSTT) WL SL RBL Read Port Pinned Layer Tunneling Oxide BL Free Layer Tunneling Oxide Free Layer WL Pinned Layers ATxL ATxR Write Port Pinned Layer WBL Tunneling Oxide SLL SLR [1] N. N. Mojumder, K. Roy, TED vol. 59, no. 11, pp , 2012 [2] X. Fong, K. Roy, EDL vol. 34, no. 2, pp , 2013

46 Write Operations WL SL I WR ( 0 ) RBL BL I WR ( 0 ) I WR ( 1 ) T OX2 WL T OX1 I WR ( 1 ) WBL SLL SLR T OX2 > T OX1 I WR ( 0 ): V SL =0, V WL =V WBL =V RBL =V DD I WR ( 1 ): V SL =V DD, V WL =V WBL =V RBL =0 I WR ( 0 ): V SLL =0, V WL =V BL =V SLR =V DD I WR ( 1 ): V SLR =0, V WL =V BL =V SLL =V DD

47 Read / Sensing Operations WL SL I RD RBL I RDL BL I RDR WL WBL I REF = 0.5 {I RD ( 0 )+I RD ( 1 )} V WL =V DD,V SL =V WBL =0, V RBL =V READ 0 : I RD ( 0 ) > I REF 1 : I RD ( 1 ) < I REF SLL V BL =0, V WL =V DD,V SLL =V SLR =V READ 0 : I RDL > I RDR 1 : I RDL < I RDR Differential sensing Self-referencing SLR

48 Simulation Framework (a) RA ( - m 2 ) E F =2.25eV, E B =0.865eV, =0.315eV, m FM =0.748, m OX =0.462, a=3e-10, T=20K, V MTJ =10mV Anti-parallel Parallel t MgO (nm) (b) RA MTJ ( - m 2 ) NEGF (AP) NEGF (P) Data (AP) Data (P) V MTJ (V) SPICE MTJ Model (c) R MTJ (k ) Standard Reversed R MTJ (k ) Standard Reversed Time (ns) Time (ns) a) S. Yuasa et al., Nature Materials vol. 3, no. 12, pp , Dec b) C. J. Lin et al., IEDM, Dec. 2009, pp c) T. Kishi et al., IEDM, Dec. 2008, pp Device level simulation results may be calibrated to experimental data Device parameters are imported into SPICE model for circuit level simulations NEGF: D. Datta et al., TNANO 11, 2, 2012 LLG: J. Z. Sun, PRB 62, 1, 2000

49 NanoHub.org SPICE Model for MTJ 60

50 STT-MRAM: LAST LEVEL CACHE Drop-in replacement of SRAM with STT- MRAM for LLC leads to improvement in capacity and leakage, but higher latency and active energy Circuit and architectural techniques can greatly improve the efficiency of spinbased caches Normalized Latency Norm. Active Energy Higher Latency Read Higher Active Energy Read Write Write Normalized Power Leakage Lower Leakage SRAM Park, Raghunathan, Roy; DAC 12 STT-MRAM Annual Review, Sept 26, MB 6T SRAM 8MB STT MRAM 8MB STT MRAM (Tilted Magnetic Anisotropy)

51 System Level Implication of STT MRAM Last Level Caches Instructions per Cycle T SRAM (2MB) STT: Conv. Std (8MB) STT: TMA (8MB) Integer Floating Point SPEC 2000 Benchmarks Total Energy Consumption (J) T SRAM (2MB) STT: Std Conv. (8MB) STT: TMA (8MB) 10 9 Cycles Avg. CU = 2.2% Max. CU = 13% 0 Leakage Only 2% 10% Cache Utilization (CU) Compared to SRAM cache STT MRAM caches offer Higher throughput due to larger integration density and lower cache miss rate Lower Energy due to low leakage and low utilization S. P. Park et al, DAC

52 ROM-Embedded MRAM

53 Read Only Memory Embedded MRAM Cell Area = max(0.5w N +4λ, 14λ) 16λ Via for ROM Programming MTJ Active Row (i-1) Poly Row (i) M1 M2 I READ1 I READ0 ROM Data BL0 BL1 Row (i+1) Pre-charge circuit Col (i-1) Col (i)col (i+1) M3 SL M1 BL0 M3 BL1 M3 WL - Poly WL1 WL2 WL3 SL SA1 V REF1 - A + - A + V OUT1 Lee, Fong, Roy, Rom Embedded MRAM, EDL 2013 V REF0 V OUT0 SA0 Read-Only Memory (ROM) may be embedded with little area overhead. Embedded ROM can be used to accelerate function evaluations (e.g.math.) No performance penalty to Random Access Memory (RAM) mode.

54 Application of ROM Embedded MRAM Transcendental Function Evaluation For evaluating log (x) For 200 Function Calls SRAM R-MRAM 1 Normalized Execution time No. of Function calls Normalized Execution Time Log Sin SRAM R-MRAM Emulation of a Neural Network (NN) shows 15% faster runtime Fong et. al, under preparation

55 Other MTJ Configurations

56 Differential Spin Hall MRAM READ MTJ1 WRITE 0 β W m1 m2 m1 and m2 are anti parallel WRITE 1 Energy efficient write Spin injection efficiency > 100 % Low resistance in write current path No tunneling barrier reliability 10X lower write energy compared to 1T1R STT MRAM MTJ1 SHM MTJ2 MgO PL FL MgO FL PL READ MTJ2 High speed differential read No need for a reference cell 2X signal margin 1.6X faster read speed compared to single ended reading Y Kim, SH Choday, K Roy, EDL 2013 Annual Review, Sept 26,

57 Multi-Level/Multi-Bit Memories

58 Domain-wall Magnet bit-cell WWL T1 RWL Fixed Free T2 GND Fixed BLB BL 1-bit DWM bit-cell with DW shift based write Write Current (ua) Low-current and fast switching of PMA DWM can facilitate low energy and high speed bit-cell design DWM: T=3nm DWM: T=6nm DWM: T=9nm MTJ: P >AP MTJ: AP >P Write Time (ns) The proposed DWM bit cell can be employed in even L1 caches, where the higher write latency and energy requirements have precluded the use of spin-based memories. Multi-bit DWM tape with DW-shift write Fukami et al., VLSIT, 2009 M. Sharad et al., ISLPED, PMA DW shift based write can also achieve low energy and fast write operation for multibit memory.

59 Multi-Level Bit-Cells Device structures with decoupled read-write paths facilitate parallel combination of free layers for multi-level read 4-level bit-cell using NL-STT 4-level bit-cell using DWM Multiple write thresholds come from varying free layer thickness, & read levels form different T ox values Multi-level bit-cells can compensate for the area penalty resulting from two access transistors as compared to just one in 1-T, 1R STT-MRAM 4-level, 8 level DMB bit cell vs 1T,1R STT-MRAM

60 Interconnects

61 STT based Energy Efficient Global Interconnects Motivation: Global Interconnects like data-buses and memory bit-lines can account for more than 90% power for on-chip memory Emerging CMPs may dissipate ~50% power for global communication among memory and multiple processors Technology/circuit solutions: On-chip transmission line CMOS Current-mode interconnects Low voltage swing Optical, plasmonic, graphene, CNT Our goals and approaches: Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to highspeed, low-voltage current-mode switches based on nano-scale magnets. We propose and analyze spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show up to two order of magnitude higher energy-efficiency 76

62 m3 oxide 3nm d3 d2 Interconnects Using Spin Torque Switches DW 60nm data data V+ V M1 M2 I in Cu-interconnect spin-switch reference MTJ gnd DW V- V 20nm d1 d2 d3 d1 transmitter receiver (a) (b) signaling-current Interconnect design using domain wall switch Global interconnects may account for large portions of total power in future processors. Emerging STT phenomena may facilitate high speed (100fs), low voltage current mode magnet switching along with efficient transimpedance conversion. V o V d V For 2Gbps signaling over a 10mm on chip interconnect: Conventional CMOS: Voltage mode: 0.5CV 2 = 2.5pfx = 150fJ Current mode: 90fJ S. Lee et al., ISSCC 2013 Spintronic Current mode: E signaling = I switch T bit V + I MTJ V MTJ T bit + T bit (P inverter + P driver ) = (20µA x 0.5ns x 100mV ) +(0.7µA x 0.6V x 0.5ns) + (0.5ns x 0.7µW) ~1fJ Sharad, Roy, EDL., 2013 Sharad, Roy, IEDM, 2013 STT switches can be employed for ultra low energy and compact current mode global interconnects

63 Spin Transfer Torque MRAM (Our work) 1. J. Li, P. Ndai, A. Goel, S. Salahuddin, and K. Roy, "Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) from Circuit /Architecture Perspective," IEEE TVLSI, N. Mojumder, S. Gupta, S. H. Choday, D. Nikonov, and K. Roy, "A Three Terminal Dual Pillar Spin-Transfer Torque (STT) MRAM for High Performance, Robust Memory Applications," IEEE TED, C. Augustine, A. Raychowdhury, D. Somsekhar, J. Tschanz, V. De and K. Roy, Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances, IEEE TED, X. Fong, S.H. Choday, and K. Roy, "Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching," IEEE TNANO, 2012,. 5. S. K. Gupta, S-P. Park, N. N. Mojumder and K. Roy, "Layout-Aware Optimization of STT MRAMs," in Proc. DATE, G. Panagopoulos, C. Augustine, X. Fong, and K. Roy, "Exploring Variability and Reliability of Multi-Level STT- MRAM Cells," DRC, Y. Kim, S. Gupta, S. Park, G. Panagopoulos, and K. Roy, "Write-Optimized Reliable Design of STT MRAM," ACM/IEEE ISLPED, R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, "TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory," ACM/IEEE ISLPED, Y. Kim, S. H. Choday, and K. Roy, "DSH-MRAM: Differential spin Hall MRAM for on-chip memories," IEEE EDL, X. Fong, S. Gupta, N. Mojumder, S H. Choday, and K. Roy, "KNACK: A Hybrid Spin-Charge Mixed-Mode Simulator for Evaluating Different Genres of STT-MRAMs," IEEE SISPAD, G. Panagopoulos, C. Augustine, and K. Roy, "A Framework for Simulating Hybrid MTJ/CMOS circuits: Atoms to System Approach," IEEE DATE, 2012.