Improved Write Margin for 90nm SOI-7T-SRAM by Look-Ahead Dynamic Threshold Voltage Control

Transcription

1 [MWSCAS2007] Aug. 7, 2007 Improved Write Margin for 90nm SOI-7T-SRAM by Look-Ahead Dynamic Threshold Voltage Control Masaaki Iijima, Kayoko Seto, Masahiro Numa, *Akira Tada, *Takashi Ipposhi Kobe University, Kobe, Japan *Renesas Technology, Hyogo, Japan

2 ABC * : Active Body-biasing Controlled 2 Outline 1. Introduction 2. ABC * -SOI and Body-Biasing Control 3. 7T-SRAM Using Look-Ahead Body-biasing with Word/Bit Line Signals 4. Simulation Results 5. Summary

3 1. Introduction Process scaling for SRAM Scaling 65nm 90nm Challenges in sub-100nm era - V th variation - V DD scaling (due to deteriorated write /read margins) 6T-SRAM survives? Good old days - Higher performance - Larger memory capacity - Lower power (lowered V DD ) Achieved simultaneously, so far 3

4 1. Introduction 8T/7T-SRAM cells for improved read margin 6T-SRAM: WBL RWL WWL - Lack of read margin as V DD goes down - Large β-ratio obstructs cell area reduction 8T/7T-SRAM: Read margin free, β-ratio can be 1 WBLB RBL WBL RWL WWL RBL 8T-SRAM Additional read port VSSM(L) VSSM(R) 7T-SRAM - Separated write/read ports - 13 % smaller than 8T-SRAM 4 L. Chang, 2005 Symposium on VLSI Technology T. Suzuki, 2006 Symposium on VLSI Circuits

5 1. Introduction Increase in read margin High High WL= High WBL RWL WWL Low High RBL High Q V DD 6T-SRAM Low QB High Q V DD 7T-SRAM Low QB High V DD V DD 5

6 1. Introduction Issue of 7T-SRAM cell Write in from WBL WBL RWL WWL VSSM(L) VDDM P1 N1 N5 VSSM(R) N4 RBL Read out to RBL Write operation using single bit-line alone deteriorates especially 1 -write margin Solution Look-ahead body-biasing (V th control) for improving write margin 6

7 2. ABC-SOI and Body-Biasing Control Direct body contact X-X N + P - Gate N + P + N - Gate Body Hybrid Trench Isolation SOI MOSFET Y-Y Buried oxide Si substrate Y. Hirano et al., IEDM Control V th individually - Enhance I on w/o increase in leakage (Improve I on /I off ) - Short transition time of body voltage -No area penalty Lower V th for same I off Y. Hirano et al., VLSI Technology

8 3. 7T-SRAM Using Look-Ahead Body-biasing with Word/Bit Line Signals Features: (i) Write bit-line (WBL) for INV(R): (N1, P1) (ii) Write/read word-line (WWL/RWL) for access and driver nmoss (, N4, and N5) Expand write margin and shorten access time WBL RWL WWL V th control based on data to be written V1 VSSM(L) INV(L) P1 N1 N4 N5 V2 RBL VSSM(R) INV(R) Proposed 7T-SRAM cell Enhanced oncurrent only when accessed 8

9 3. 7T-SRAM Using Look-Ahead Body-biasing with Word/Bit Line Signals Layout of Memory cell - No area penalty - Embedded body contacts for -5 - Shared body contacts for N1, P1-2 : GND fixed GND WBL VDD GND WBL RWL WWL RBL V1 P1 N1 N4 N5 V2 RBL N4 RWL WWL P1 N1 N5 N4,N5: Biased by RWL : Biased by WWL :Full Trench Isolation : Body contact : M1 : M2 Area: 0.86 x 2.56 µm 2 9

10 3. 7T-SRAM Using Look-Ahead Body-biasing with Word/Bit Line Signals Memory Array with Body Contact Cell (Ex. 4 word x 2 bit ) N4 N4 :Shared body region P1 N1 N5 N5 N1 P1 N5 N1 P1 P1 N1 N5 N / 2 cells N4 N4 Body contact for N cells N4 N4 Body contact cell P1 N1 N5 N5 N1 P1 N5 N1 P1 P1 N1 N5 N / 2 cells Memory cell N4 N4 10

11 4. シミュレーションによる評価 Simulation Results Simulation setup -Process: 90nm - Supply voltage: V DD = 0.6V - Threshold voltage: V tn / V tp = 0.39 / 0.44V - Tr. size for memory cell: L / W = 0.10 / 0.16µm - SRAM configuration: 8K-bit (256word x 32bit) List of evaluation (1) Write margin (2) Access time (3) Timing slack of body voltage (4) Impact of V th variation Compared with: -Body-tied (Zero body-bias) 11

12 4. Simulation Results (1) Write margin VTCs shift owing to forward body-biased strong pmos/nmos V VTC for INV(L) VTC for INV(R) Body-tied(conv.) Body-bias(prop.) V1 conv.: 171mV prop.: 182mV 0 -write mode V WBL RWL WWL Body-tied(conv.) Body-bias(prop.) V1 VTC for INV(L) conv.: 0.9mV prop.: 51mV VTC for INV(R) V1 1 -write mode INV(L) P1 N1 INV(R) N4 N5 V2 RBL 12

13 4. Simulation Results (2) Access time V body (N1) WWL V1(prop.) RBL(prop.) RBL(conv.) 3.05ns CLK WBL V1(conv.) 4.80ns V2(conv.) VSSM(L) V2(prop.) CLK 8.19ns 4.69ns BL out (conv.) RWL BL out (prop.) 1 -write mode read mode 0.64x 0.57x 13

14 4. Simulation Results (3) Timing slack of body voltage Trade-off between # of shared MCs and area overhead / timing slack of body voltage Area overhead (prop./conv.) word 128word 256word N : # of shared memory cells (MCs) (Assuming N =32 for conv. layout) Timing slack (t WWL - body t ) [ns] N < 8: V body Reg./Cap. of body : R(Nwell): 111kΩ/µm R(Pwell): 222kΩ/µm Cap: ff/µm V WWL time Completely charged body before writing N > 8: V WWL V body time Partially charged body 14

15 4. Simulation Results (4) Impact of V th variation (1/2) Target: Write margin Monte-carlo simulation: - Vth variation assuming 3σ = 10% of V th (Fluctuating Vth0 in Tr. model parameter) - Global : local = 1 : 1-1,000 points analysis Occurrences µ = 0.7 mv σ = 7.7 mv Write margin [mv] -Mean (µ): Improved by 73x Body-tied (conv.) Body-bias (prop.) µ = 50.9 mv σ = 7.7 mv - Coefficient of variation (σ/µ): 11.0x (conv.) 0.15x (prop.) 15

16 4. Simulation Results (4) Impact of V th variation (2/2) Target: Access time 250 Body-tied (conv.) Body-bias (prop.) 250 Body-tied (conv.) Body-bias (prop.) Occurrences µ = 3.08 ns σ = 0.17 ns σ/µ = 5.6 % µ = 4.91 ns σ = 0.57 ns σ/µ = 11.5 % Occurrences µ = 0.80 ns σ = 0.10 ns σ/µ = 12.7 % µ = 2.63 ns σ = 0.55 ns σ/µ = 21.1 % write time [ns] Coefficient of variation (σ/µ): 11.5% (conv.) 5.6% (prop.) 21.1% (conv.) 12.7% (prop.) Delay time of memory cell [ns]

17 5. Summary Challenges of SRAM in deep sub-100nm era V th variation and lowered V DD degrade: - Write / Read margins - Access time 7T-SRAM cell seems alternative for improving SNM, but deteriorates write margin Look-ahead body-biasing with WL / BL signals expands write margin and shortens access time Effect of proposed body-biasing control - Improved write margin 1 -write) - Access time reduction - Mitigate impact of V th variation on write margin and access time 17

18 Thank you for your attention. 18