Split-gate charge trap memories: impact of scaling on performances and consumption for low-power embedded applications

Transcription

1 Split-gate charge trap memories: impact of scaling on performances and consumption for low-power embedded applications Lia Masoero

2 Outline Introduction Technological details Basics of split-gate charge trap memories Impact of charge trapping layer Program/Erase Retention Impact of the memory gate scaling HHI Erasing Programming windows Current consumption Conclusions 2

3 CONTEXT Increasing demand for embedded memories: embedding a NVM and a logic circuit on the same substrate (Industrial machine, home appliance, automotive) Charge trap Storage gate + 2T memory: Select gate Storage gate Combining charge trap memory with a 2T structure! Resistant to SILC Simple memory cell Easily embedded with a logic circuit Excellent program efficiency High-speed Low power supply Source Side Injection programming # patents Split-gate Charge trap Year [Celise 21] 3

4 State of the art CT Split-gate Freescale S. Kang et al., proc. of Int. Mem. Workshop 212, pp Renesas T. Tanaka et al., 23 Symp. on VLSI Circ., pp MG AG AG MG 32bits µcontroller products 9nm Si-ncs charge trapping layer SSI program, FN Erase Various investigated architectures, With TSMC «it will outsource manufacture of mcus at the 4nm node [ 5/212] Silicon nitride charge trapping layer SSI program, FN or HHI Erase Our approach 2 architectures CTL: SiN, NCS, SiN+NCS.. Impact of gatelengthscalingdown to 2nm on the memoryperformances, Understandingof physicalmechanismsbasedon experimentsand simulations Study on current consumption 4

5 Outline Introduction Technological details Basics of split-gate charge trap memories Impact of charge trapping layer Program/Erase Retention Impact of the memory gate scaling HHI Erasing Programming windows Current consumption Conclusions 5

6 Studied Devices Schematic Cross Section TEM IMAGE V Memory Gate (MG) W Cross section Select Gate Poly-Si (SG) TiN Drain (D) Si -ncs +SiN LSG MG Source Si-ncs Si3N4 Al O (S) SiOL2MG 3nmSG 3nm Spacer 3 Tunnel Oxide Charge Trap Layer SiN SiO2 (5nm) SiN (6nm) Si-nc Poly-Si SiO2 (5nm) (Φ~6nm) (1nm) SiO 2 MG W D Control Diel. Cont. Gate Poly-Si (1nm) SiO2 Si SEM18nm image 2 Technological details S 2nm SG Planar view AlO Si-nc SiO2 (Φ~6nm) (5nm) Poly-Si (5nm) SiN Si-nc SiO2 (3nm) TiN (Φ~6nm) (4nm) Al2O3 SiN (8nm) 6

7 Outline Introduction Technological details Basics of split-gate charge trap memories Impact of charge trapping layer Program/Erase Retention Impact of the memory gate scaling HHI Erasing Programming windows Current consumption Conclusions 7

8 Consumption Channel Current [µa] PGU Drain A + SG WGFMU1 Id MG PGU2 Source V WGFMU2 V SG =2.4V V SG =1.8V V SG =1.3V V SG =1V V SG =.7V Time [us] Dynamic current obtained by measuring the channel current measured during pulse programming Channel Current [A] setup verified comparing the I S (V SG ) with the current consumed during a prg pulse =8V V S =3.5V Control of I prog W=2nm t P =1µs V SG [V] 8 6 V T [V] 4 2 8

9 Outline Introduction Technological details Basics of split-gate charge trap memories Impact of charge trapping layer Program/Erase Retention Impact of the memory gate scaling HHI Erasing Programming windows Current consumption Conclusions 9

10 Programming-Source Side Injection SiN SiN+Si-nc SG SG SG V S V S V S Si-nc V T -V T erase [V] V S =3V =1V =8V =6V V T -V T erase [V] V S =3V =1V =8V =6V Best Memory Windowfor Si 3 N 4 (due to higherdensityof trappingsites) Good V t improvementwithsi-nc/sinwithrespect to Si-nc V T -V T erase [V] V S =3V =1V =8V =6V 1

11 SG SiN HHI Erasing-FN & HHI SG Si-nc FN Top Si-nc/SiN + high k SG AlO FN Down V T -V T prog [V] V S =3V V S =4V V S =6V =-8V V T -V T prog [V] =1V =12V =14V =16V SiN: HHI faster erasing but high current Consumption Si-nc: FN erase is achieved Faster erasing throught bottom oxyde with High-k interpoly dielectrics V T -V T prog [V] =-1V =-12V =-14V =-16V 11

12 V T [%] V T [%] Retention Stack comparison T=85 C T=15 C Low T SiN shows the best High T Si-nc memories smallest charge loss Memories with High-k control dielectric show faster decay V T 1 5 s V T 2*1 5 s SiN SiN SiN SiN/Si-nc Si-nc 12

13 Outline Introduction Technological details Basics of split-gate charge trap memories Impact of charge trapping layer Program/Erase Retention Impact of the memory gate scaling HHI Erasing Programming windows Current consumption Conclusions 13

14 Memory Gate scaling/hhi Erasing SG SSI V Erased / V written % MG e- hole HHI SG Write 5us Vd=3 =1 V SG =1 Erase 5us Vd=5 =-1 V SG = L MG [nm] MG e- hole SSI HHI L MG reduced Mismatch between electron and hole injection decreases small memories show better erase efficiency 14

15 Memory Gate scaling/simulations SG SG V T [V] e-trapped [C/cm 3 ] MG nm MG 2nm 2 (a) (b) V T [V] Data Sim. V s =3V V SG =1V =6V =8V Data =1V L MG [nm] Simulation 12 V 3 S =3 V =1V 2 V SG =1V L MG 4nm HCI simulated using Fiegna model As L MG is reduced memory window increases L MG 2nm 15

16 Memory Gate scaling/electric Field SELECT gate gap Memory gate Potential [V] SG MG ONO X [um] Programming condition =8V V SG =1 V S =3V High Electric Field in the gap: due to the difference between the memory gate and the access gate potentials channel / source junction: due to the high applied VS 16

17 Memory Gate scaling/electric Field SG MG ONO E local [MV/cm] (c) L MG Peak Gap Source L MG 5nm 1nm 15nm 35nm x [nm] Large L MG two peaks Small L MG the two peaks merge Higher electric field Higher programming window 17

18 Memory Gate scaling/consumption Measured programming characteristics and current consumption for various gate lenghts V T [V] Consumption [J] L MG [nm] W=2nm L SG =2nm V S =3.5V =8V V AG =1V L MG Energy= V S I S (t)dt Time Consumption [nj] V T =3.5V V S =3.5 V =8V V AG =1V L MG [nm] L MG reduced V T increased Reducedt prog and consumptionfor a given V T Scaled technologies suitable for low power applications 18

19 Outline Introduction Technological details Basics of split-gate charge trap memories Impact of charge trapping layer Program/Erase Retention Impact of the memory gate scaling HHI Erasing Programming windows Current consumption What next? Conclusions 19

20 SPACER architecture P2 ONO stack Poly - Si SEM image SG 5nm Si 3 N 4 SiO 2 Si V T -V T write [V] V D =3V V D =3.5V V D =4V V D = V T -V T erase [V] T T erase V D =5V V D =7V V D =9V =8V First test on SiN-SPACER architecture: good P/E behaviour 2

21 Conclusions 1/2 Split gate charge trap memories were processed with gate length down to 2nm with SiN and Si-ncs charge trapping layers Impact of charge trapping layers Nitride memories show a higher Vt during HCI programming Hybrid Si-nc/SiN memories allow to improve Si-nc windows Si-nc memories can be erased by FN without current consumption High-k interpoly dielectric increases the erasing speed Silicon nitride memories show a better low T Silicon nanocristal memories show a better 15 C 21

22 Conclusions 2/2 Impact of the memory gate scaling As L MG is reduced memory window increases, explained by TCAD simulations (higher electric field, higher charge injection) HHI erasing efficiency increases with the scaling of the memory dimension In short devices, as a shorter programming time is sufficient for a given V T, reduction of energy consumption (<1nJ) can be achieved suitable for low power embedded applications 22

23 Acknowledgements G. Molas, M. Gély, C. Charpin, V. Della Marca+, R. Kies, F. Brun, O. Cueto, J. P. Colonna, A. De Luca, P. Brianceau, D. Lafond, V. Delaye, F. Aussenac, C. Carabasse, S. Pauliac, C. Comboroure, P. Boivin+, G. Ghibaudo*, S. Deleonibus, B. De Salvo CEA Leti, Minatec Campus, France + IMEP LAHC, Grenoble, France * STMicroelectronics, Technology R&D, Rousset, France 23

24 Merci de votre attention