A Simulation Study of the Punch-Through-Assisted Hot Hole Injection Mechanism for Nonvolatile Memory Cells

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 5, MAY A Simulation Study of the Punch-Through-Assisted Hot Hole Injection Mechanism for Nonvolatile Memory Cells Matteo Iellina, Pierpaolo Palestri, Member, IEEE, Nader Akil, Michiel J. van Duuren, Francesco Driussi, David Esseni, and Luca Selmi Abstract In this paper, we investigate the operating principle and the injection efficiency of the punch-through-assisted hot hole injection mechanism for programming nonvolatile memory cells by means of full-band Monte Carlo transport simulations of realistic device structures. The effects of terminal bias and cell scaling on the injection efficiency and the uniformity of charge injection along the channel are analyzed in detail. Index Terms Hot carrier injection, Monte Carlo, nonvolatile memory, silicon-nitride. I. INTRODUCTION PUNCH-THROUGH-ASSISTED hot hole injection (PAHHI) has been proposed as a new programming mechanism in nonvolatile memory cells [1] [3]. This mechanism is particularly suited for embedded SONOS/TANOS nonvolatile memory arrays of a few megabits of cells in cost-driven consumer applications (such as ID and smart cards), where high-temperature operation is not requested, and performances below those of floating-gate (FG) cells can be tolerated. The main advantages over programming by Fowler Nordheim (FN) tunneling at negative gate voltages are the possibility to use thicker tunnel oxide and higher programming speed. APAHHI-basedcell(Fig.1)operatesatnegativegatevoltage. The shape of the source/drain junction is tailored to keep the electron flow far from the Si/SiO 2 interface (i.e., the shortest effective channel length is at a depth y P from the Si/SiO 2 interface). At the drain end of the channel, electrons generate electron hole pairs by impact ionization (II). Secondary holes are attracted toward the interface and partly injected in the SiN layer. The rest of them drift toward the source and are eventually collected by the substrate. Different from industrystandard FG cells, the array is selectively programmed by charging the storage node with the PAHHI mechanism (which Manuscript received September 21, 2009; revised January 5, First published March 18, 2010; current version published April 21, This work was supported by the Italian MIUR under FIRB Project RBIP06YSJJ. The review of this paper was arranged by Editor S. Deleonibus. M. Iellina, P. Palestri, F. Driussi, D. Esseni, and L. Selmi are with the Italian Universities Nano-Electronics Team, Dipartimento di Ingegneria Elettrica, Gestionale e Meccanica, University of Udine, Udine, Italy ( palestri@uniud.it). N. Akil is with Photovoltech, Tienen 3300, Belgium. M. J. van Duuren is with NXP Research, 3001 Leuven, Belgium. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED Fig. 1. Schematic representation of a PAHHI cell and corresponding injection mechanisms. Note that the minimum L EFF is at a distance Y P from the Si/SiO 2 interface. The storage electrode can be either an FG or a silicon-nitride (SiN) layer (SONOS/TANOS). In series to the cell (not shown), there is a selection gate [1], which in the simulations we assume to behave essentially as a short circuit. reduces the threshold voltage V T of the device), and it is erased by nonselective uniform electron tunneling under positive V G. An access transistor must be inserted in series to the cell to limit the current during programming since V T decreases during time and thus the drain current tends to increase. Detailed numerical analysis of PAHHI with state-of-the-art hot-carrier models is needed to optimize the performance of the injection mechanisms, to analyze the uniformity of the injection mechanism (which in SONOS cells influences the endurance), and to assess the potential for scaled embedded applications. However, to our knowledge, no simulation studies have been carried out so far to investigate this mechanism and its dependence on the cell design and bias. Modeling PAHHI is not trivial and must include various ingredients: accurate modeling of the spatial profile of the punch-through current, II of electrons, hot hole transport, and their injection in the dielectric. In this paper, we use full-band Monte Carlo (FBMC) simulations to investigate the bias dependence of the PAHHI mechanism and the possibility to use low drain voltages, the uniformity of the charge injection, and possible improvements related to the scaling of the cell. This paper proceeds as follows: The simulation model is presented and validated against experimental data for equivalent transistors in Section II. The bias dependence and the uniformity of the PAHHI mechanisms are analyzed in Section III considering equivalent transistors. The effects related to the /$ IEEE

2 1056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 5, MAY 2010 scaling of the cell are addressed in Section IV. Conclusions are drawn in Section V. II. SIMULATION MODEL AND DOPING PROFILES A. Description of the FBMC Simulator Simulations are run in a frozen-field configuration using the FBMC simulator described in [4] and [5]. The potential profile is taken from calibrated drift-diffusion simulations [6], where II is activated because secondary carriers influence the potential profile inside the device. The II scattering rate employed in the FBMC has been calibrated to reproduce measured II coefficients [7] and quantum-yield experiments [8]. Secondary carriers are generated according to an initial energy distribution consistent with the energy of the carrier that triggered the II event and with the physics of the II process [9], [10]. This is an important ingredient to properly simulate the energy distribution of the secondary holes and in particular its high-energy tail, which controls carrier injection in the storage node. The current injected in the storage node is computed by multiplying the energy distribution of particles impinging the Si/SiO 2 interface by the transmission probability to the storage node (FG or SiN layer), including image charge lowering [10]. Following [11], momentum at the Si/SiO 2 interface is not conserved. This means that what really matters for the injection of a particle in the storage node is its energy in the direction normal to the interface. This is not trivial to define in the fullband case. We define it as E = E tot k 2 k 2 tot (1) Fig. 2. Simulated (drift-diffusion model [6]) versus experimental transcharacteristics. (Plot A) L G = 192 nm. (Plot B) L G = 376 nm. The cell with L G = 192 nm features L EFF = 150 nm, whereas the one with L G = 376 nm features L EFF = 250 nm. In both cells, Y P = 70 nm, Y J = 300 nm, and T OX = 7 nm. Note the enhanced punch-through current in the shorter cell. Fig. 3. Simulated (FBMC) versus experimental bulk current normalized to the drain current. (Plot A) L G = 192 nm. (Plot B) L G = 376 nm. Experiments performed in channel hot electron (CHE) injection conditions (V G > 0). where k and k tot are the normal and total carrier momentum relative to the nearest conduction band minimum (valence band maximum). Carrier carrier scattering [10], [12] is not included in this paper. However, in all the simulated cases, the applied biases are large enough to produce a significant carrier population at energies close to the effective barrier for injection in the storage electrode. The inclusion of carrier carrier scattering is thus expected to slightly affect the absolute values of the results but not the overall trends. B. Extraction of Realistic Doping Profiles Equivalent transistors have been fabricated by slightly modifying the I/O transistors of NXP s commercially available embedded non-volatile memory process with a minimum CMOS feature size of approximately 0.14 µm. Compared with standard I/O transistors, the ones measured here feature a shorter gate length (192 nm instead of approximately 300-nm nominal length) but the same gate oxide thickness (7 nm) and doping profiles. Both standard and modified transistors have a single poly-silicon gate. Process simulations were used as a starting point to determine realistic doping profiles to be used in the simulations, and then slightly adjusted to improve the agreement with ex- Fig. 4. Simulated (FBMC) versus experimental gate current normalized to the drain current for an equivalent transistor biased in CHE injection conditions (V GS > 0). perimental drain (I D ), substrate (I B ),andgate(i G ) currents measured on the equivalent transistors. Data are not available for V GS < 0 due to the presence of a protection diode. The comparison between experiments and simulations is reported in Figs. 2 4 (I D, I B,andI G in channel hot electrons conditions, respectively) and in Fig. 5 (I B in PAHHI conditions), demonstrating that the model captures both the physical trends and the order of magnitude of the measured data.

3 IELLINA et al.: SIMULATIONSTUDYOFTHEPAHHIMECHANISM FOR NONVOLATILE MEMORY CELLS 1057 Fig. 5. Simulated (FBMC) versus experimental substrate current normalized to the drain current for an equivalent transistor approaching the PAHHI configuration (V GS 0). Fig. 7. (Open symbols) Energy distribution of the secondary holes as they are generated by the II of the primary channel hot electrons. (Filled symbols) Energy distribution of the holes impinging the Si/SiO 2 interface at the drain side. Notice that the former is a distribution in total energy, whereas the latter is in normal energy [see the definition in (1)]. Equivalent transistor with L G = 192 nm. Fig. 8. Voltage drop ( V ) experienced by the secondary holes when traveling from the position of maximum generation rate (X max,y max) to the Si/SiO 2 interface at the drain side. The sign of the voltage drop corresponds to an attractive force toward the interface for holes. Equivalent transistor with L G = 192 nm. The dashed line indicates the condition V = V DS. Fig. 6. Spatial distribution of the electron current density (upper plot) and of the generation rate of secondary holes (lower plot). Equivalent transistor with L G = 192 nm. The dashed lines indicate the position of the S/D junctions. V DS = 4V,andV GS = 4 V.Thecoordinates(X max,y max) denote the position of maximum II generation rate. Color scales are on the right. III. RESULTS: BIAS DEPENDENCE AND UNIFORMITY OF PAHHI We start considering a 192-nm equivalent transistor (essentially the one considered in Figs. 2 5) in PAHHI bias conditions (i.e., V GS < 0). Fig. 6 confirms that the source-to-drain electrons flow at about 70 nm below the Si/SiO 2 interface (upper plot) and points out that the generation of secondary holes (lower plot) at the drain end of the channel is maximum at a depth Y max,whichisclosetothedepthy P of the minimum channel length (see the sketch in Fig. 1). Fig. 7 reports the energy distribution of the secondary holes as they are generated (open symbols): The high energy tail moves toward higher energy with increasing V DS.However, V DS alone is not sufficient to deliver to holes enough energy for injection, i.e., to surmount the Si/SiO 2 energy barrier. Indeed, secondary holes gain a significant amount of energy while traveling toward the interface. As indicated in Fig. 8, the voltage drop from the position of maximum generation to the interface is close to V DS,since in PAHHI conditions (due to the hole accumulation layer), the source potential penetrates into the drain in the proximity of the Si/SiO 2 interface (see the potential map in Fig. 9). The hole accumulation layer screens the gate potential so that the effect of V GS on V is small. We have verified that V V DS also when the source-to-bulk voltage is not null. This means that in the two-transistor configuration (access gate transistor

4 1058 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 5, MAY 2010 Fig. 9. Example of potential profile for V DS = 4V,V GS = 4 V.Equivalent transistor with L G = 192 nm. Color scales are on the right. Fig. 11. Injection efficiency (upper plot) I G /I D and (lower plot) I G in PAHHI and BBT conditions (floating source). Working in the frozen field, the FBMC provides only current ratios, so I G is obtained by multiplying I G /I D from the FBMC by the I D from the drift diffusion. Fig. 10. Injected hole current density profile along the channel for a few V GS values. Equivalent transistor with L G = 192 nm: the gate electrode extends from x= µm tox= µm. connected to the source of the PAHHI cell), as the source potential raises, the effective V is reduced. As a result of the large additional energy gained by the holes when moving toward the interface, the energy distribution of the holes impinging the Si/SiO 2 interface (filled symbols in Fig. 7) features tails at much larger energy than the distribution of the as-generated carriers (open symbols in Fig. 7). The hole gate current density profile is shown in Fig. 10: It peaks at the drain end of the channel, consistent with the fact that secondary holes are generated close to the drain junction (see Fig. 6). We have verified that in moving backward from the point of maximum hole injection (X max,0)tothemiddle of the channel, the energy distribution of the holes impinging the interface slowly becomes colder compared with the one at (X max,0). The lateral extension of the profile of the hole gate current density is only slightly larger than that typically obtained with band-to-band tunneling (BBT) in NROM cells [13]. The electron current (not shown) is instead essentially zero compared with the hole one, consistent with the experimental findings in [1]. Fig. 11 (upper plot) reports the bias dependence of I G /I D in PAHHI conditions: We see that V DS modulates I G /I D remarkably, whereas the effect of V GS is weaker. In addition, the ratio I G /I D in BBT conditions is shown, which has been computed by taking the generation rate for BBT as obtained by drift-diffusion simulations [6] using the model in [14] and then by importing it into the FBMC, as explained in [13]. We see that I G /I D in BBT conditions is larger than in PAHHI. However, the absolute value of I G is much larger in PAHHI conditions (lower plot), consistent with [1, Fig. 6] that shows how the programming time in BBT conditions is more than six orders of magnitude longer than under PAHHI. The lower I G in BBT conditions w.r.t. the PAHHI ones in this cell also implies immunity against the drain disturb (as demonstrated by the experimental data in [1, Fig. 10]). Note that our comparison refers to a cell optimized for PAHHI; hence, it does not imply that PAHHI is always more efficient that BBT. Cells optimized for BBT could exhibit a BBT injection efficiency comparable with the one obtained in PAHHI cells. However, using PAHHI is advantageous over BBT mainly for two reasons: 1) In PAHHI cells, there is no need for steep junctions at the drain, and thus the cell is easier to integrate and does not require additional masks and process steps. 2) Since hole injection by BBT is more localized at the drain, in cells featuring a trapping layer, it works better when associated with electron injection by channel hot electrons, which is also localized at the drain; on the other hand, BBT gets less efficient when applied to cells where electrons are injected uniformly along the channel by FN.

5 IELLINA et al.: SIMULATIONSTUDYOFTHEPAHHIMECHANISM FOR NONVOLATILE MEMORY CELLS 1059 IV. RESULTS: EFFECT OF SCALING THE CELL We now consider the effect of reducing the lateral and vertical dimensions of the cell. To have a more accurate estimate of the programming performances, we consider SONOS cells with a t ox = 5nm/t N = 6nm/t top = 6nmONOstackandrealistic values of the control gate voltage. Different from the equivalent transistors considered in the previous section, in the SONOS cell, the injected charge changes the potential of the storage node and thus the potential profile in the channel. The correct evaluation of the programming transient requires a self-consistent solution of FBMC transport, device electrostatics, and transport in the nitride layer. To simplify the picture, in the following, we will compute the value of the current only at the beginning of program transient, assuming that the SiN layer is uniformly charged by uniform FN electron injection. We consider a uniform potential on the interface between the SiN layer and the bottom oxide. This approach neglects the random fluctuations of the potential due to the discrete nature of the trapping sites in SiN; hence, it is representative of the average cell behavior. Since the hole injection is mainly controlled by the drain potential and is only weakly sensitive to the potential at the gate, our assumption is not expected to significantly affect the results. The uniform potential assumed in the following corresponds to a voltage drop V SiN = 2.7 V over the bottom oxide at the source side of the cell. For the considered stack, the voltage drop on the whole stack without trapped charge is equal to Fig. 12. Effect of the procedure used to scale the gate length of PAHHI cells: To keep the same ratio between the read current of the programmed and erased cells, the scaling of L G must be followed by scaling in the vertical dimensions. The simulated structure is an equivalent transistor with a gate bias V EQ and an oxide thickness of 5 nm, which is equal to the bottom oxide thickness of the considered SONOS cells. The range of considered V EQ is sufficient to describe the SiN potential during the reading of a cell with a memory window of 4 V. In fact, for the considered stack, a memory window of 4 V corresponds to avariationof4(t ox/t ox + t N ɛ SiO2 /ɛ SiN + t top) 1.5 V of the potential drop across the bottom oxide, which in turn corresponds to a variation of 1.5 V of V EQ essentially centered around the threshold voltage of the neutral device. TABLE I PARAMETERS OF THE SCALEDDEVICES.THE GATE ONO STACK IS THE SAME IN ALL CASES:5nm/6nm/6nmOF SiO 2 /Si 3 N 4 /SiO 2 ɛ t ox + t SiO2 N ɛ V stack (0) =V SiN + t top SiN = 7.6 V. (2) t ox We should subtract V T from this number. We assume that the threshold voltage variation associated with FN injection is V T = 2 V, obtaining a voltage drop V stack ( V T )= 5.6 V. We have then verified that in the considered cell, the potential drop is approximately 0.4 V higher than the applied bias (due to the voltage drop in the silicon substrate and the different affinity of gate and substrate), giving V CG 6V. To analyze the effect of scaling, we start with a device featuring L G = 192 nm and the same doping profiles as in the previous sections. Then, other devices have been obtained by lateral and vertical scaling at a constant ratio between the read current of a programmed cell and an erased one. Fig. 12 reports an example of such a procedure: We first reduce L G without modifying Y P and Y J.Thisstronglydegradestheratiobetween the read current of programmed and erased cells. Y P and Y J are then scaled to recover the ratio between the read currents of the original cell. In principle, much lower read current ratios than the one of the original cell could be tolerated, but we have chosen to keep this number constant to compare the different cells on a common ground. We will then analyze later the effect of Y P and Y J on the injection efficiency for a given L G. Table I reports the main parameters of cells designed with the aforementioned methodology. The vertical and lateral scaling has been accompanied by a scaling of the steepness of the doping profiles: for scaling by a factor α in lateral or vertical direction, the variance of the Gaussian doping profiles has been reduced by α. Fig. 13. Injection efficiency for PAHHI for devices with different L G (see Table I). The dashed line indicates that for a given efficiency, scaling allows to reduce V DS. The simulated I G /I D is reported in Fig. 13. We see that scaling enhances I G /I D,openingthepossibilitytouselowV DS in scaled cells. In addition, the drain current (reported in Fig. 14), usually low in PAHHI cells, increases with scaling, further reducing the programming time. The profile of the injected current along the channel is reported in Fig. 15: the geometrical scaling results in a more

6 1060 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 5, MAY 2010 Fig. 14. Drain current for the same cases as in Fig. 13. Fig. 16. Experimental evidence of improved endurance for shorter L G in SONOS mini arrays (128 bits) with 4 nm/6 nm/6 nm ONO gate stack. The measured devices are 2T cells, which feature access gate transistors in series with the transistors in PAHHI. The V DS value indicated in the figure is the one applied to the series of two transistors. Fig. 15. Normalized gate current density profiles for the cells in Table I. uniform charge injection in the SiN layer. This can be explained as follows: Even in the long channel case, the spatial extension of the injection is a few tens of nanometers, which is related to the spatial extension of the region of large II generation and to the fact that the secondary holes are also moving toward the source end of the channel when traveling from the generation point toward the Si/SiO 2 interface. For shorter devices, the region of large II generation corresponds to a significant fraction of the channel and is wider than in the long devices in both relative terms (compared with the channel length) and absolute terms. We have verified that in the short cells, the almost uniform hole injection profile is related to the shape of the hole energy distribution at the Si/SiO 2 interface that is very similar at different positions along the channel. The more uniform injection for shorter cells may imply a better endurance of the cell. This is suggested by the experimental data in Fig. 16 for ONO devices fabricated in an experimental NMOS-only flow with 193-nm litho for poly and active. By means of resist trimming, the gate length was reduced below the nominal length in a controllable and reproducible way. Due to short channel effects (the gate length was scaled without modifying the doping profiles and the gate stack), the shorter device has a lower threshold voltage, which explains its lower V T after FN. Furthermore, the resist trimming used to reduce Fig. 17. Simulated injection efficiency as a function of the parameters Y J and Y P that define the junction profile. Cell with L G = 60 nm. The parameter Y J is effecting the efficiency only when large values are used, which degrades the ratio between the read current of programmed and erased cells. the gate length also affects the access gate transistor. As a result, even if the voltages applied to the two-transistor cell (access gate plus the transistor in PAHHI conditions) are the same, the voltage drops available for PAHHI are not equal in the 120- and 90-nm devices. This means that Fig. 16 cannot be used to assess the effect of scaling on PAHHI efficiency (i.e., the V T window). Indeed, in this case, the 90-nm cell has a smaller program/erase window than the 120-nm cell, in apparent contrast to the better PAHHI efficiency shown by our simulations in Fig. 13. However, we clearly see that the program/erase window remains almost constant up to more than 1 k cycles in the 90-nm device, whereas in the 120-nm device, the V T after FN starts increasing after approximately 100 cycles. This proves that the endurance improves for a smaller gate length. We finally analyze the effect of the junction parameters (Y J and Y P in Fig. 1) on I G /I D.TheresultsarereportedinFig.17. We notice that when Y P is too small, I G /I D is reduced, since the source potential is no longer able to penetrate into the drain end of the channel, thus reducing V.Areductionof about 0.5 V has been observed going from Y P = 60 nm to

7 IELLINA et al.: SIMULATIONSTUDYOFTHEPAHHIMECHANISM FOR NONVOLATILE MEMORY CELLS nm. For relatively large Y P values (from 60 nm down to approximately 30 nm), we do not see a reduction of I G /I D since we are reducing the distance between the generation point and the interface, then reducing the number of scattering events suffered by the secondary holes. Below a given Y P,however, the reduced scattering no longer compensates the reduced V and I G /I D starts decreasing. The dependence on Y J is less trivial to explain. It has however to be noticed that a clear improvement of I G /I D can be seen for Y J = 300 nm, but this corresponds to a significant degradation of the read characteristics (see Fig. 12). For smaller Y J values, the effect on I G /I D is weak. V. C ONCLUSION We have used FBMC simulations and realistic doping profiles, resulting from calibration against data for equivalent transistor, to analyze the PAHHI mechanisms. It has been found that, provided the gate voltage is negative enough, the carrier heating and the injection efficiency are mainly controlled by the drain voltage. PAHHI is demonstrated to be a scalable injection mechanism with expected efficiency above 10 5 and I D 100 µa/µm downtov DS = 3.3 V. The profile of the injected current is peaked at the drain side, but it gets more uniform when the gate length of the cell is scaled, so endurance is expected to improve in short devices. Cells optimized for PAHHI exhibit low BBT generation rates, which is promising to reduce the influence of disturbs. However, to fully exploit the scaling of the PAHHI cell, the access transistor also needs to be optimized, since the voltage drop on the access transistor reduces the effective drainto-source voltage of the PAHHI cell. Optimizing the access transistor is not just a matter of increasing its current driving capability: the voltage drop across the access gate is essential to prevent destruction of the cell due to current runaway during PAHHI. [5] P. Palestri, N. Akil, W. Stefanutti, M. Slotboom, and L. Selmi, Effect of the gap size on the source-side-injection efficiency of split-gate memory cells, IEEE Trans. Electron Devices, vol. 51, no. 3, pp , Mar [6] DESSIS 9.5 User Manual, ISE A.G., Zurich, Switzerland, [7] R. van Overstraeten and H. D. Man, Measurements of the ionization rates in diffused silicon p-n junctions, Solid State Electron., vol. 13, no. 5, pp , May [8] C. Chang, C. Hu, and R. Brodersen, Quantum yield of electron impact ionization in silicon, J. Appl. Phys., vol. 57, no. 2, pp , Jan [9] P. Palestri, L. Selmi, M. Pavesi, F. Widdershoven, and E. Sangiorgi, Coupled Monte Carlo simulation of Si and SiO 2 transport in MOS capacitors, in Proc. SISPAD, 2000,pp [10] M. V. Fischetti, S. Laux, and E. Crabbè, Understanding hot electron transport in silicon devices: Is there a shortcut? J. Appl. Phys., vol. 78, no. 2, pp , Jul [11] M. Städele, B. R. Tuttle, and K. Hess, Tunneling through ultrathin SiO 2 gate oxides from microscopic models, J. Appl. Phys., vol. 89, no. 1, pp , [12] A. Ghetti, Explanation for the temperature dependence of the gate current in metal oxide semiconductor transistors, Appl. Phys. Lett., vol. 80, no. 11, pp , Mar [13] G. Ingrosso, L. Selmi, and E. Sangiorgi, Monte Carlo simulation of program and erase charge distribution in NROM devices, in Proc. ESSDERC, 2002,pp [14] A. Schenk, Rigorous theory and simplified model of the band-to-band tunneling in silicon, Solid State Electron., vol. 36, no. 1, pp , Jan Matteo Iellina was born in Udine, Italy, in He received the B.S. and M.S. degrees in electronic engineering from the University of Udine, Udine, in 2006 and 2009, respectively. Since 2009, he has been with the Dipartimento di Ingegneria Elettrica, Gestionale e Meccanica, University of Udine, where he works on the simulation of hot carrier phenomena in nonvolatile memory cells. ACKNOWLEDGMENT The authors would like to thank the NXP colleagues in Leuven (B) and Nijmegen (NL) involved in the fabrication of devices measured here and A. Dalla Costa for help in the driftdiffusion simulations. REFERENCES [1] N. Akil, M. van Duuren, D. Golubovic, M. Boutchich, and R. van Schaijk, New punch-through assisted hot holes programming mechanism for reliable SONOS FLASH memories with thick tunnel oxide, in Proc. NVSMW,2007,pp [2] N. Akil, M. van Duuren, D. Golubović, and M. Boutchich, Low voltage and fast program and erase sonos with thick tunnel oxide for low cost embedded EEPROM-like memory applications, in Proc. NVSMW/ICMTD, 2008, pp [3] M. van Duuren, N. Akil, M. Boutchich, and D. Golubovic, New writing mechanism for reliable sonos embedded memories with thick tunnel oxide, in Proc. ICICDT, 2008,pp [4] W. Stefanutti, P. Palestri, N. Akil, and L. Selmi, Monte Carlo simulation of substrate enhanced electron injection in split-gate memory cells, IEEE Trans. Electron Devices,vol.51,no.1,pp.89 96,Jan Pierpaolo Palestri (M 05) received the Laurea degree (summa cum laude) in electronic engineering from the University of Bologna, Bologna, Italy, in 1998 and the Ph.D. degree in electronic engineering from the University of Udine, Udine, Italy, in In 1998, he was a Research Assistant in the field of device simulation with the Department of Electrical, Mechanical and Management Engineering, University of Udine. From July 2000 to September 2001, he held a Postdoctoral position with Bell Laboratories, Lucent Technologies (now Agere Systems), Murray Hill, NJ, where he worked on high-speed silicon germanium bipolar technologies. He became an Assistant Professor in October 2001 and an Associate Professor in November 2005 with the University of Udine. He coauthored more than 100 papers in refereed journals and conference proceedings. His research interests include the modeling of carrier transport in nanoscale devices and the simulation of hot carrier and tunneling phenomena in scaled MOSFETs and nonvolatile-memory cells. Dr. Palestri served as a Technical Program Committee Member for the International Electron Devices Meeting (IEDM) in 2008 and 2009.

8 1062 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 5, MAY 2010 Nader Akil received the degree in physics from Reims University, Reims, France, in 1995 and the Ph.D. degree from Metz University, Metz, France, in He spent the last year of his Ph.D. degree working on light emission from siliconbased devices with the Department of Electrical and Computer Engineering, Vanderbilt University, Nashville, TN. From 1999 to 2000, he was a Postdoctoral Associate with Twente University, Enschede, The Netherlands, where he worked on nanoscale siliconbased devices for applications in micro total analysis systems. In 2000, he was with Philips Research Laboratories, Eindhoven, The Netherlands. In 2001, he was with Philips Research Leuven, IMEC, Leuven, Belgium. From 2006 to 2009, he was with NXP Semiconductors, IMEC, Leuven. His work with Philips and NXP Semiconductors was focused on the modeling, design, and characterization of embedded FG and charge trapping memories, mainly lowcost multiple-time programmable memories. Since 2009, he has been with Photovoltech, Tienen, Belgium, where his current interest is in solar cells. Michiel J. van Duuren was born in Groenlo, The Netherlands, in He received the M.S. degree in applied physics and the Ph.D. degree from the University of Twente, Enschede, The Netherlands, in 1993 and 1996, respectively. In 1998, he was with Philips Research Laboratories, Eindhoven, The Netherlands, where he worked on reliability aspects, characterization methods, and device physics of floating gate and SONOS memories. Since 2001, he has been with Philips Research Leuven (now NXP Semiconductors), Leuven, Belgium, where he became project leader of the embedded memories technology research project, with activities on, for instance, charge trapping, floating gate, finfet, nanocrystal, and phase change memories. Francesco Driussi received the Laurea degree and the Ph.D. degree in electronic engineering from the University of Udine, Udine, Italy, in 2000 and 2004, respectively. In 2005, he was a Research Associate with the University of Udine. From October 2002 to September 2003, he held a student position with Philips Research Leuven, Leuven, Belgium. He is currently with Dipartimento di Ingegneria Elettrica, Gestionale e Meccanica, University of Udine. His research activities are mainly in the field of nonvolatile memory cell reliability, and in particular, his interests have been in the characterization of device degradation and gate dielectric reliability. In particular, he has worked on substrate-enhanced hot electron phenomena and investigated on their implications for Flash EEPROM devices. More recently, he worked on the development of physical and statistical models for the study of SILC in large FLASH memory arrays and of the oxide trap generation and distribution. At the moment, his main activity is on the characterization and the modeling of SONOS memory cells and on the in-depth investigation of the trapping properties of silicon nitride. Part of his activities now are also in the field of the experimental characterization and modeling of the carrier mobility in MOSFET devices featuring strained silicon and high-k gate stacks. David Esseni received the Laurea degree and the Ph.D. degree in electronic engineering from the University of Bologna, Bologna, Italy, in 1994 and 1998, respectively. In 2000, he was a Visiting Scientist with Bell Labs-Lucent Technologies, Murray Hill, NJ. Since 2005, he has been an Associate Professor with the University of Udine, Udine, Italy. His research interests are mainly focused on the characterization, modeling, and reliability of MOS transistors and nonvolatile memories (NVM). In the field of NVM, he has worked on the low-voltage and substrate-enhanced hot-electron phenomena and on several aspects of EEPROM memories, including innovative programming techniques and reliability issues related to the statistical distribution of stress-induced leakage current. Since 2000, he has been involved in the field of advanced or innovative CMOS devices. In particular, he has experimentally investigated low-field mobility in ultrathin SOI MOS transistors and then started an activity of semi-classical transport modeling in advanced n-mos and p-mos transistors. In this field, his research interests also include quantization models beyond the effective mass approximation as well as modeling and characterization of stress effects on the CMOS technologies. Dr. Esseni served as a member of the technical committee of the International Electron Devices Meeting (IEDM) in 2003 and 2004, is currently in the technical committee of the European Solid-State Device Research Conference (ESSDERC) and the International Reliability Physics (IRPS), and is a member of the Technology Computer Aided Design Committee of the Electron Devices Society (EDS). He is an Associate Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and has been one of the Guest Editors of a Special Issue of IEEE TED devoted to the simulation and modeling of nanoelectronic devices. Luca Selmi received the Ph.D. degree in electronic engineering from the University of Bologna, Bologna, Italy, in From April 1989 to June 1990, he was a Visiting Scientist with the Microwave Technology Division, Hewlett Packard, Santa Rosa, CA. Since 2000, he has been a Full Professor of electronics with the University of Udine, Udine, Italy, where he is currently responsible of a research group on nanoelectronic devices with the Dipartimento di Ingegneria Elettrica, Gestionale e Meccanica (DIEGM). He held technical and/or coordination responsibility in several EC research projects in the field of microelectronics and nanoelectronics. His research activities have been carried out in cooperation with many semiconductor research laboratories and companies worldwide, including Philips Research, NXP Semiconductors, Infineon Technologies, IMEC, LETI, IBM T. J. Watson Research Center, AT&T Bell Laboratories, and Hewlett Packard Company. He coauthored approximately 150 papers in refereed journals and conference proceedings, including more than 30 International Electron Devices Meeting (IEDM) papers. His research interests include electron device modeling and characterization, with emphasis on CMOS scaling, Monte Carlo simulation techniques, hot-carrier effects, quasi-ballistic transport, nonvolatile memories (floating gate, CHISEL-based, localized trapping, SONOS, and TANOS), and semiconductor device reliability. Dr. Selmi is currently an Associate Editor of the IEEE ELECTRON DEVICES LETTERS.HehasservedasaTechnicalProgramCommitteeMemberofseveral electron device conferences (IEDM, European Solid-State Device Research Conference (ESSDERC), INFOS, SISC, and ULIS) and a Coorganizer of the INFOS 2001 and ULIS 2003 and 2008 conferences.