1 Ionic Memory Technology

Transcription

1 j1 1 Ionic Memory Technology An Chen Ionic memory devices based on ion migration and electrochemical reactions have shown promising characteristics for next-generation memory technology. Both cations (e.g., Cu þ,ag þ ) and anions (e.g., O 2 ) may contribute to a bipolar resistive switching phenomenon that can be utilized to make nonvolatile memory devices. With simple two-terminal structures, these devices can be integrated into CMOS (complementary metal oxide semiconductor) architecture or fabricated with novel architectures (e.g., crossbar arrays or 3D stackable memory). Large memory arrays made with standard CMOS process have been demonstrated in industry R&D. Although ionic memory technology has seen significant progress recently, some challenges still exist in device reliability and controllability. Ionic memories may present a promising candidate for stand-alone and storage class memory applications. 1.1 Introduction With flash memories quickly approaching their scaling limit, numerous novel memory technologies have emerged as candidates for next-generation nonvolatile memories. Examples include phase change memory (PCM), magnetic random access memory (MRAM), ferroelectric RAM (FeRAM), resistive switching memory (also known as RRAM or resistive random access memory), polymer-based memory, molecular memory, and so on [1 3]. Figure 1.1 shows a classification of various memories presented by the International Technology Roadmap of Semiconductor (ITRS) [1]. Static random access memory (SRAM) and dynamic random access memory (DRAM) are called volatile memories because information stored in these memories cannot be retained when power is turned off. On the other hand, nonvolatile memories are able to retain information for a long period of time after power is turned off. A typical requirement of data retention is 10 years at room temperature. The mainstream nonvolatile memory in the market today is flash memory, which is divided into two categories, NAND and NOR, based on two Solid State Electrochemistry II: Electrodes, Interfaces and Ceramic Membranes. Edited by Vladislav V. Kharton. Ó 2011 Wiley-VCH Verlag GmbH & Co. KGaA. Published 2011 by Wiley-VCH Verlag GmbH & Co. KGaA.

2 2j 1 Ionic Memory Technology Memory Volatile Nonvolatile SRAM DRAM Mature Prototypical Emerging Flash Charge trapping RRAM NOR PCM Ionic NAND MRAM Electronic FeRAM Thermal Polymer Nano mechanical Molecular Figure 1.1 Classification of memory technologies based on information in ITRS roadmap. The abbreviations are explained in the text. different memory architectures. NOR flash memories are preferred for code storage because of their random access capability, while NAND flash memories are more suitable for data storage due to their sequential access in a block of data. These three types of mature memory technologies SRAM, DRAM, and flash memory are all based on Si complementary metal oxide semiconductor (CMOS) technology. Their development has followed the so-called Moores law; that is, the transistor density in the integrated circuits has doubled approximately every 2 years. This is achieved by shrinking the size of the Si CMOS transistors, a trend that has successfully continued for several decades. When transistor size is reduced, not only more bits of information can be stored on the same area but also better device/circuit performance can be achieved, for example, fast speed and lower power consumption. However, with the transistor size being reduced to 22 nm and below, Si CMOS technology today is facing some fundamental challenges. Although power consumed by each transistor has decreased with scaling, the overall power density of the wafers has increased because of growing transistor density. Increasing power density induces more Joule heating and raises wafer temperature, which degrades transistor performance. The wafer temperature today is reaching the limit of practical cooling techniques, constraining further scaling of transistor size. Although it is believed that Si CMOS technology can be scaled down to 22 nm, it is not clear how much further it can go. These mainstream memory technologies based on Si CMOS are facing the same obstacles. Therefore, it has become increasingly important to explore alternative nonvolatile memory technologies that may potentially replace Si-based memories when they reach their limits.

3 1.1 Introduction j3 Among these emerging memory devices, resistive switching memory (i.e., RRAM) is a broad category involving a large variety of materials and switching characteristics. These memory devices are usually made in a two-terminal metal insulator metal (MIM) structure. They can be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS), and both states can be nonvolatile. Commonly used terminology refers LRS as the on state and HRS as the off state. Binary digital data can be recorded in these resistance states, for example, LRS for logic 0 and HRS for logic 1. The HRS-to-LRS switching is called program (or write, set) and the LRS-to-HRS switching erase (or reset). Promising characteristics have been reported on these devices. However, in many reports of resistive switching memories the switching mechanisms are not clearly understood. Some hints of the switching mechanism may be found in switching characteristics, for example, current voltage (I V) relationships, the voltage polarity dependence of switching, the presence or absence of forming processes, the effect of the electrodes on the switching properties, device size dependence, temperature effect, variation in transport properties, cycling stability, and so on. Unfortunately, systematic study on all these aspects is still lacking for many resistive switching materials, and controversial interpretations of the switching mechanism are widely presented in the literature. A coarse-grained classification has been proposed to divide resistive switching memories into three types based on the nature of the dominating switching processes: electronic effect, thermal effect, and ionic effect. In electronic effect resistive switching memories, some electronic processes (e.g., charge trapping, Mott metal insulator transition, or ferroelectric polarization reversal) alter the band structure and transport properties in the bulk or at the interface and trigger resistance changes. Thermal effect resistive switching memories are related to electric power-induced Joule heating and often involve the formation and rupture of some localized conduction paths in an insulating material. The third type, ionic effect resistive switching memories, involves the transport and electrochemical reactions of cations (e.g., Ag þ,cu þ ) or anions (e.g., O 2 ). The switching is usually bipolar; that is, programming and erasing are in opposite voltage polarities. This is because the switching between LRS and HRS is realized by driving charged ions in opposite directions to induce different electrochemical reactions. The switching process related to the migration and reaction of cations is well understood, and the switching process can be captured in microscopic observations. However, resistive switching process involving anions is less well understood, with many open questions regarding the details of the anion transport and electrochemical redox reactions. The discussion of ionic memories in this chapter will mainly focus on these memory devices based on cation migration and reactions. The resistive switching mechanisms and materials involving anions, mainly oxygen ions or vacancies, will also be briefly discussed. This chapter is organized in the following sections. Section 1.2 discusses the ionic resistive switching mechanisms, followed by a review of materials used in these devices in Section 1.3. Electrical characteristics of ionic memories, including individual device properties and memory array statistics, are summarized in

4 4j 1 Ionic Memory Technology Section 1.4. Section 1.5 addresses issues in the architecture design of ionic memories. In Section 1.6, challenges of ionic memories are discussed. Section 1.7 provides some information of potential applications of ionic memories. Finally, the chapter ends with a brief summary in Section Ionic Memory Switching Mechanisms The switching mechanisms of cation-based devices and anion-based memories are different [3]. The resistance change in the cation-based devices is due to the electrochemical formation and dissolution of metallic filaments, which can be observed in sufficiently large devices in well-designed experiments [4 10]. For anion-based memories, the switching is generally believed to be triggered by the transport of oxygen ions/vacancies and some redox processes; however, the exact process is still not clear. In some cases, it is even unclear which ions are involved in the switching process and whether the device falls into the category of anion-based ionic memories Cation-Based Resistive Switching Mechanism In the MIM structure of cation-based ionic memories, one of the two electrodes is made of electrochemically active materials and the other electrode is inert (e.g., Au or Pt). In most reported cation-based ionic memory devices, the active electrode is either Ag or Cu. The two electrodes are separated by a solid-state electrolyte I layer, in which cations can transport with the mobility much higher than that in regular solidstate materials. These solid electrolytes are sometimes called superionic materials (see Chapters 2 and 7 of the first volume). A typical switching process is illustrated in Figure 1.2. The solid-state electrolytes normally have high resistance initially and are considered to be insulators (Figure 1.2a). When positive voltage is applied to the active electrode, as the active electrode (acting as anode in this voltage configuration) is made of electrochemically active materials, metal atoms of the anode are oxidized and dissolved into the solid electrolyte. These metal cations migrate toward the cathode under electrical field and are reduced there. Therefore, under electrical field, oxidation and reduction reactions take places at the anode and cathode, respectively: M þ þ e reduction! oxidation M. The reduced metal atoms form metal filaments that grow from the cathode toward the anode. When the anode and cathode are connected by complete metal filament(s), the MIM device switches from HRS to LRS (Figure 1.2b). When voltage polarity on the two electrodes is reversed, metal atoms dissolve at the edge of the metal filament(s) and eventually break the conductive filament(s) between the anode and the cathode. Current-induced Joule heating may also contribute to the rupture of the filament(s). Consequently, the MIM device is switched back to a high-resistance state (Figure 1.2c). Note that the metal filament(s)

5 1.2 Ionic Memory Switching Mechanisms j5 Inert electrode Active electrode (a) Initial state Inert electrode Active electrode (b) ON state Inert electrode Active electrode (c) OFF state Figure 1.2 Schematic illustration of cation-based ionic resistive switching process.

6 6j 1 Ionic Memory Technology need to be broken only partially to cause significant increase in resistance, and it is not necessary to completely annihilate the metal filament(s) from the I layer. As a result, the HRS off state during repeated switching processes may not be as insulating as the original state; however, sufficiently high on/off ratio between the LRS and the HRS can still be achieved. When the active electrode is positively biased again, the metal filament(s) can be repaired by the same cation migration and redox reactions. The HRS-to-LRS and LRS-to-HRS switching processes can be repeated continuously. Since the electrochemical reactions ideally do not cause significant damage to the MIM structure, the switching process may in principle work for many cycles. From the switching process described above, it is clear that cation-based ionic memories have to be bipolar; that is, programming and erasing processes have to be done with opposite voltage polarities. This bipolar switching is considered one of the signatures of ionic memories. Another key feature of ionic memories is the localized conduction path of metal filament(s), which has been suggested as an evidence of excellent scalability of ionic memories. In principle, ionic memory devices can be made as small as one atomic chain of metal atoms. It is also easy to understand that the formation of these filaments is a self-limiting process. As soon as one conductive filament is formed, resistance of the I layer reduces dramatically, which results in significant decrease in electric field and the chance of forming additional filaments. Different names have been given to the cation migration-based resistive switching devices, such as atomic switch [11], programmable metallization cell [7], nanobridge [8], solid-state electrolyte memory [12], conductive bridging RAM [13], and so on Anion-Based Resistive Switching Mechanism In many oxides, especially transition metal oxides, oxygen ions or vacancies are much more mobile than cations. The migration of oxygen ions and vacancies may introduce redox reaction at the electrode or doping effects in the metal oxides, which may alter the transport properties of the structure and cause resistance changes. Numerous models have been proposed to describe the details of the switching processes involving oxygen ions and vacancies; however, the exact microscopic processes are still not clear. The following are a few examples of resistive switching phenomena that have been suggested to be caused by oxygen ions or vacancies. A single crystal of 0.2 mol% Cr-doped SrTiO 3 is found to switch from an initially insulating state to a conductive state after it is exposed to an electrical field of 10 5 Vcm 1 for about 30 min, a process known as conditioning (or forming). High-temperature hot spots and high concentration of oxygen vacancies are both found close to the anode, by infrared thermal microscopy and laterally resolved micro-x-ray absorption spectroscopy, respectively. It is suggested that the conditioning process introduces a path of oxygen vacancies in the memory, which provides free carriers in the Ti 3d band and leads to metallic conduction. The Cr dopants play the

7 1.2 Ionic Memory Switching Mechanisms j7 role of a seed for oxygen vacancies. The resistive switching of the conditioned Cr SrTiO 3 is believed to involve a drift of oxygen vacancies along the applied electrical field. When the anode is negatively biased, positively charged oxygen vacancies are attracted to the anode and a low-resistance state is obtained. On the other hand, when a positive bias is applied on the anode, oxygen vacancies retract from the anode and the memory device switches back to a high-resistance state [14]. Another study of resistive switching in SrTiO 3 suggests that the switching phenomenon originates from local modulations of the oxygen content and is related to the self-doping capability of the transition metal oxide [15]. The I V characteristics of a Pt/TiO 2 /Pt structure can be made rectifying (i.e., current can pass in one direction but not in the opposite direction) by applying a programming voltage to one of the Pt electrodes. The polarity of the rectification can be reversed by applying the programming voltage in the opposite direction. The proposed mechanism of this field programmable rectification involves fieldinduced motion of oxygen vacancies. Initially, the two Pt electrodes form Schottky barriers at the TiO 2 interface, giving the device an insulating state. When a programming voltage is applied, oxygen vacancies are pushed toward the anode and the accumulation of oxygen vacancies increases the doping of TiO 2 near the anode, which gradually eliminates the Schottky barrier at this electrode. Consequently, the I V characteristics become rectifying, dominated by the Schottky barrier at the other electrode. The reversal of the programming voltage may push oxygen vacancies toward the other electrode and the direction of the rectification is eventually reversed. During their transit between electrodes, oxygen vacancies may not lie next to either electrode, which return the device to an insulating state. Therefore, resistive switching between insulating state and a rectifying conduction state can be achieved under well-controlled conditions. Since the motion of oxygen vacancies is thermally activated, it is also possible that the migration of oxygen vacancies is driven by current-induced Joule heating, in addition to the electrical field [16].In another study of TiO 2 -based resistive switching devices, a filament model is suggested for the switching mechanism. In this model, the switching between HRS and LRS is explained by the propagation of portions of the filaments close to the anode and cathode, accompanied by the transfer of O 2 along the filaments [17]. The resistive switching characteristics of NiO x are found to be highly sensitive to the oxygen flow ratio during the reactive ion beam sputtering deposition process used to prepare NiO x. The window of resistance change (or on/off ratio) increases with the increase in oxygen flow ratio, which also correlates with the increase in barrier height change between on and off states. It is expected that oxygen ions or vacancies are contributing to the control of the switching process, although their exact functions are not yet clear [18]. Oxygen content has also been found to play crucial role in the conduction and resistive switching of La 0.7 Ca 0.3 MnO 3 (LCMO) [19] and Pr 0.7 Ca 0.3 MnO 3 (PCMO) [20]. X-ray photoelectron spectroscopy measurement shows that excess oxygen in PCMO introduced by oxygen annealing causes an increase in Mn 4 þ content and hence a change in the Mn 4 þ /Mn 3 þ ratio at the PCMO surface. As a result, the on/off resistance ratio is increased by oxygen annealing of the PCMO

8 8j 1 Ionic Memory Technology thin film [21]. Similarly, the resistive switching characteristics of LCMO are also improved by oxygen annealing [19]. As shown by the examples above, there are different ways that oxygen ions or vacancies may introduce resistance changes in metal oxides. A generic picture of the switching process can be summarized as the following. Driven by electrical field or Joule heating, mobile anions may migrate from the negatively biased electrode to the positively biased electrode. The migration of the anions may introduce electrochemical reactions at the electrode, create doping effects to change carrier density or band structure, or simply alter the properties of some localized conduction paths (filaments). Consequently, resistive switching may take place when sufficient change in the transport properties is reached. Further study is required to elucidate the microscopic nature of the processes that causes the change in the transport properties of the metal oxides. 1.3 Materials for Ionic Memories Resistive switching materials involving anions (oxygen ions or vacancies) are usually metal oxides, especially transition metal oxides. Resistive switching phenomena explained by anion migration and reactions have been demonstrated in various oxides including NiO x,tio 2, SrTiO 3, LCMO, PCMO, and so on. Properties of these oxides are highly sensitive to composition; therefore, even slight change in oxygen content may trigger large change in conductivity. Since the exact resistive switching mechanisms of these transition metal oxides are not yet clear, it is possible that other physical processes may also contribute to the switching, for example, Joule heating, charge trapping, and so on. The discussion on ionic memory materials in this section will mainly focus on cation-based ionic memories that can be more clearly defined. In the MIM structure for cation-based ionic memory devices, the key components are the electrochemically active electrode and the solid-state electrolyte. The inert electrode typically uses Pt, Au, or W. The active electrode contributes the mobile ions for the formation of metallic filaments, and the solid electrolyte provides an environment where cations migrate and metal filaments grow. Most ionic memories use Ag or Cu as the active electrode because of the high mobility of Ag þ or Cu þ ions. The most commonly used solid-state electrolytes are the sulfides of these elements (i. e., Ag 2 S, Cu 2 S) and Ge-based chalcogenides (i.e., GeSe, GeS). It is also found that many oxides when combined with Ag or Cu electrodes can work as ionic switching devices. SiO x and Ta 2 O 5 are the two oxides frequently used. Figure 1.3 plots a matrix showing the combinations of these two active electrodes (Ag or Cu) with various solid-state electrolytes [6 11, 22 60]. Each dot in the figure represents an ionic memory device reported in the literature with reference numbers. In these ionic memories with superionic metal sulfides as the solid electrolyte (e.g., Ag 2 S), mobile ions (e.g., Ag þ ) already exist in the solid electrolyte. However, for the other solid electrolytes, the mobile ions are external to the electrolytes and usually a forming

9 1.3 Materials for Ionic Memories j9 Ag [6, 11, 22-25] [7, 26-28] [28-30] [31] [32-34] [10, 36] [38, 39] [41, 42] [35] [37] [40] Cu [8, 43-47] [49-53] [9, 54-56] [48] [30] [28, 57] [58] [59, 60] Ag 2 S Sulfides Cu 2 S GeSe GeS Ge-based halcogenides SiO x TiO x Ta 2 O 5 Oxides WO 3 MoO x -Si Si 3 N 4 As 2 S 3 ASP MSQ (AgI) 0.5 (AgPO 3 ) 0.5 ZnCdS CuC Note: ASP = Ag 30 S 2 P 14 O 42 ; MSQ = methyl silsesquioxane Others Figure 1.3 Materials for cation-based ionic resistive switching memories. process is performed to drive these ions into these materials, before stable resistive switching can be achieved Metal Sulfide Solid Electrolytes In a scanning tunneling microscope (STM) experiment using Ag 2 S as the tip, it was found that Ag protrusion grew on the top of Ag 2 S tip, which was explained by solid electrochemical reaction of Ag ions in Ag 2 S [23]. A filamentary shape Ag cluster with the length of 200 nm and the diameter of 70 nm could be clearly observed in scanning electron microscope (SEM) [6]. This field-driven growth and rupture of Ag filament inside Ag 2 S was then utilized to make a switching device [11, 24, 25]. In Ag/ Ag 2 S devices, the Ag 2 S layer is formed by sulfidization of Ag in a thermal process [11, 24] or an electrochemical process [25]. Similarly, Cu 2 S is a natural solid electrolyte for Cu þ to form Cu/Cu 2 S ionic memories. Cu 2 S can be made by electrochemically sulfidizing Cu films in Na 2 S solution [43] or pulsed laser deposition (PLD) [45, 47] Ge-Based Chalcogenide Solid Electrolytes Ag and Cu ions exhibit high mobility and good thermal stability in Ge-based chalcogenide glasses such as GeSe or GeS. For example, AgGeSe is shown to take the form of a continuous glassy Ge 2 Se 3 host and a dispersed nanoscale Ag 2 Se phase,

10 10j 1 Ionic Memory Technology which possesses superionic properties [7]. The metal-rich Ag 2 Se phase is a mixed ionic electronic conductor (MIEC), but the Ge 2 Se 3 host material that separates these conductive regions is a good insulator. The overall resistance of the material prior to ionic switching is high. Ag or Cu can be introduced to the base glass (GeSe or GeS) using a photodriven process (exposure to ultraviolet light) with or without high temperature. After this treatment, bipolar resistive switching can be achieved by applying appropriate voltages. A potential challenge with GeSe-based devices is their thermal stability. Ag-doped GeSe electrolytes cannot tolerate processing conditions beyond 200 C. It is found that devices made of GeS are more stable than GeSe-based devices. For example, Ag/GeS devices become functional after annealing at 300 C for 15 min in oxygen ambient [30]. Cu/GeS memory devices can be operated at 125 C [30] Oxide Solid Electrolytes Various oxides can also be used as solid electrolytes in ionic memories. Since deposited SiO x is a major component of back-end-of-line (BEOL) process in CMOS and Cu has also been widely used in CMOS process, the Cu/SiO x combination is a particularly desirable structure for ionic switching memories. The SiO x film can be prepared by physical vapor deposition [49], electron beam (e-beam) evaporation [50], or radio frequency (rf) sputtering [51]. Cu is then introduced into SiO x film by thermal diffusion at 610 C, and stable resistive switching can be achieved afterward. The photodiffusion forming technique used for Ge chalcogenide materials does not work for Cu/SiO x devices, which may be explained by the high rigidity of SiO x network that limits Cu photodiffusion [50]. Unlike e-beam evaporated SiO x, sputtered SiO x is found to require no intentional forming process and devices can be switched with very low current compliances (e.g., several tens of pa) [51]. Polycrystalline TiO 2 formed by thermal oxidation of Ti films can also act as a solid electrolyte for Ag þ ions, and no forming is needed for stable switching [31]. If tungsten oxide (WO 3 ) is sufficiently porous, Cu can be introduced into this WO 3 base glass through diffusion by ultraviolet illumination [28]. WO 3 can be grown by oxygen plasma treatment of a tungsten metal electrode or by high-vacuum thermal evaporation from high-purity tungsten oxide source [57]. Devices made of plasma oxidation WO 3 have variable switching voltage and poor retention, whereas devices based on deposited WO 3 show stable switching voltage and good retention, even at high temperature (>125 C). The difference may be explained by the observation that Cu electrode tends to oxidize in plasma oxidation WO 3 but is more stable in deposited WO 3. Cu/Ta 2 O 5 devices also demonstrate bipolar resistive switching. However, because Cu þ diffusion coefficient is relatively low in Ta 2 O 5, it is found that the threshold voltage of Cu/Ta 2 O 5 switching devices is higher than that of other switching devices and the data retention time is longer [9, 54]. By using transmission electron microscopy and energy dispersive X-ray spectrometry (EDX), it can be clearly identified that the conductive path consists of Cu metallic islands separated by

11 tunneling barriers [9]. Ta 2 O 5 can be prepared by PLD [9] or sputtering [56]. Another oxide electrolyte for Cu þ is MoO x, prepared by sputtering a 0.5% Cu-doped MoO 3 target on Cu substrate at 500 C [58]. The Cu concentration in the deposited MoO x film is measured to be more than 5% (10 times higher than the target concentration) because of Cu diffusion from the bottom electrode during high-temperature sputtering. This diffusion process helps to form a Cu-rich MoO x solid electrolyte for ionic switching Miscellaneous Other Solid Electrolytes 1.3 Materials for Ionic Memories j11 Numerous other materials are shown to be good ionic conductors for Ag þ or Cu þ, and they are also suitable for solid electrolytes in ionic memory devices. Some examples are discussed in this section. Ag electrode can be combined with hydrogenated amorphous Si (a-si) deposited by chemical vapor deposition (CVD) to form ionic memories [33]. In addition to planar device structures, a-si nanowires (NWs) are also used with Ag metal lines (perpendicular to the direction of the NWs) to form a cross-point array of ionic memories [34]. An interesting observation is the rectifying I V characteristics in LRS for both planar and NW Ag/a-Si devices, which is rarely found in other ionic memory devices. Si 3 N 4 is another material fully compatible with CMOS processing, and Si 3 N 4 films deposited by plasma enhanced CVD (PECVD) exhibit bipolar resistive switching with Ag electrode [35]. The growth of Ag filaments inside As 2 S 3 films and the polarity-dependent switching were observed more than 30 years ago [10]. In a more recent study, As 2 S 3 film was made by vacuum evaporation and Ag was dissolved into it through photoassisted and thermal-induced doping to make Ag/As 2 S 3 ionic switching devices [36]. Ag 2 S-doped AgPO 3 (ASP) has been studied for applications in solid-state batteries and electrochemical devices. A recent study reports bipolar resistive switching in Ag/ASP devices prepared by PLD, showing potential for memory applications [37]. A similar solid electrolyte is glassy (AgI) 0.5 (AgPO 3 ) 0.5 that can also be deposited by PLD and works as an ionic memory device with Ag electrode [40]. Spin-on glass methyl silsesquioxane (MSQ) is not only proven to be a functional solid electrolyte for Ag þ but also particularly useful in making nanocrossbar memory structures through UV nanoimprint lithography (UV NIL) [38, 39]. Devices with bit crossbar memory array and nm size Si/MSQ have been demonstrated. Resistive switching behavior of an Ag/Zn x Cd 1 x S device was first attributed to ferroelectric polarization reversal, but later it was suggested that the formation and annihilation of Ag-rich deposits were more likely to be the switching mechanism [42]. Different metals (Ag, Cu, Zn, Au, Ta, and Pt) have been experimentally tested as electrodes on Zn x Cd 1 x S, and only devices with electrochemical active metals (i.e., Ag, Cu, and Zn) demonstrated bipolar resistive switching behaviors consistent with the ionic switching model [41]. Cu-doped amorphous carbon (CuC) film is another potential candidate for solid electrolyte of Cu þ -based ionic memories because of its insulator properties and high Cu diffusivity. The CuC film can be deposited by rf magnetron reactive

12 12j 1 Ionic Memory Technology sputtering using a Cu target in Ar, CH 4, and O 2 at room temperature [59, 60]. Here, O 2 acts as a catalyst for the decomposition of CH 4 to provide a source of carbon. After a voltage stress forming process, Cu/CuC devices can be electrically switched repeatedly. 1.4 Electrical Characteristics of Ionic Memories Many ionic memory devices have been characterized on individual device level. Device-level characterization is relatively easy to implement and helps to understand the switching mechanisms. Large-scale memory arrays have also been fabricated and tested by several companies. Array-level characterization provides important statistics for the evaluation of ionic memory technologies and more accurate parameters of memory performance. For example, parasitics inevitably exist in individual device structures and the measurement setup, which limits the accuracy of switching speed measurement. High-quality memory arrays, especially those fabricated in standard CMOS, are more suitable for high-speed measurement Ionic Memory Device Characteristics The individual device characteristics of various Ag- and Cu-based ionic memories are summarized in Table 1.1. These switching parameters are collected from published papers, and reference numbers are given in the last column. Unless specified, all data in this table are measured at room temperature. It should be noted that many parameters are not accurately identified in these papers; therefore, their values are recorded as ranges or approximations rather than precise numbers. They may also vary in a large range depending on devices and measurement conditions. In addition, some values are not reported in these papers and are left as blank in Table 1.1. The thickness t se refers to the thickness of the solid-state electrolyte and the diameter D d is the diameter of the device (usually the size of the smaller electrode or vias where the device is located). Both parameters are given in nanometers. Switching time t sw is usually reported as the minimum pulse width that can successfully switch devices in alternating current (AC) measurements. This minimum switching pulse width may be limited by equipment capability or external parasitics, so many values are given as the upper limit of the switching time. The intrinsic switching speed may be much faster than the measured speed. The on/off ratio is the resistance ratio between HRS and LRS, measured at typical reading voltages. Retention has been measured on many devices, to demonstrate their feasibility for nonvolatile memory applications. A typical retention criterion for nonvolatile memory is 10 years at room temperature. Most retention data summarized in Table 1.1 are direct measurements of the device resistance state over a prolonged period of time. Retention of 10 5 s (28 h) or longer has been

13 1.4 Electrical Characteristics of Ionic Memories j13 Table 1.1 Device characteristics of Ag-based and Cu-based ionic memories. Solid electrolyte t se (nm) D d (nm) HRS! LRS LRS! HRS t sw (s) On/off ratio Retention (s) Cycle References Vsw (V) Isw (A) Vsw (V) Isw (A) Ag electrode Ag 2 S <0.4 <0.4 <10 6 >10 3 >10 5 [11, 24, 25] GeSe <0.5 <10 6 <0.2 <10 6 < >10 11 [7, 26 28] GeS < <10 5 < >10 5 [28 30] TiOx [31] a-si-nanowire >10 4 >2 weeks >10 4 [34] Si3N >10 2 >10 4 [35] As 2 S > [36] ASP >10 5 [37] MSQ >250 [38] (AgI)0.5(AgPO3) >10 5 [40] ZnCdS < [42] Cu electrode Cu2S < years >10 3 [8, 43] GeSe > >10 5 [48] GeS < [30] SiO x < > [50] Ta2O years 10 4 [9, 54] (Continued )

14 14j 1 Ionic Memory Technology Table 1.1 (Continued ) Solid electrolyte t se (nm) D d (nm) HRS! LRS LRS! HRS t sw (s) On/off ratio Retention (s) Cycle References Vsw (V) Isw (A) Vsw (V) Isw (A) WO >10 4 >10 4 >10 4 [28, 57] MoO x < >10 5 >10 6 [58] CuC < < >10 4 (85 C) >10 3 [59] Notes: 1) Symbols: t se, thickness of the solid electrolyte; D d, diameter of the devices; V sw, switching voltage; I sw, switching current; t sw, switching time. The HRS! LRS switching is known as programming or set and the LRS! HRS switching is known as erasing or reset. 2) The switching voltage listed in the table refers to the DC switching voltage; AC switching voltage can be much higher and may vary depending on pulse width. 3) The switching is bipolar; therefore, V sw values have opposite sign for HRS! LRS and LRS! HRS processes. V sw values in the table are absolute values. 4) Solid electrolytes: ASP ¼ Ag 30 S 2 P 14 O 42 ; MSQ ¼ methyl silsesquioxane. 5) The Cu/WO 3 device here is based on deposited WO 3. Devices based on WO 3 grown by plasma oxidation of W have different characteristics (less stable).

15 1.4 Electrical Characteristics of Ionic Memories j15 measured on many devices. To confirm 10-year retention in product-level measurements, tests under thermal or electrical stress are needed and 10-year retention can be extrapolated from measured data based on established retention models. Most ionic memory devices are reprogrammable and cycling endurance is an important parameter. Cycling endurance is a critical indicator of stability and reliability. Endurance of cycles has been observed in many devices. Ag/GeSe device has demonstrated the endurance as long as cycles. The switching voltage and current in Table 1.1 are measured in direct current (DC) operations. In a typical DC measurement, voltage applied to the electrodes is swept through a range, and current compliance is often applied to prevent device damage. Hysteretic loops exist in measured I V characteristics, indicating memory effects. Voltages required for AC operation are usually much higher than those for DC operation. Some studies have shown that the switching voltage and pulse width strongly depend on each other. For example, the switching time of Ag 2 S/Ag devices decreases exponentially with the increase in switching voltage [24]. Although devices canbe switched at0.2 V with 10 mswidepulses,switching voltage 0.4 Visrequired to operate them with 1 ms. Since the ionic switching process involves the drift of ions and electrochemical reactions, it is reasonable to expect that higher electrical field is needed to accomplish the same ionic switching process in shorter time. An important characteristic of ionic memories is the low operation voltage. Figure 1.4 plots the set switching voltage and current for Ag þ -based devices (a) and Cu þ -based devices (b), using the data in Table 1.1. The labels are the solid electrolytes of these devices. Most devices can be programmed with voltage below 0.5 V, which is significantly lower than the operation voltage of flash memory and also lower than many other emerging memories. Flash memory circuits require special design to provide high voltages, which not only creates an area/design overhead but also causes reliability concerns. Low-voltage operation is an advantage of ionic memories. On the other hand, devices that can be switched with very low voltage (e.g., 0.2 V) also need to be carefully designed and protected from unintentional electrical shock. Switching current of ionic memories distributes in a wide range, as shown in Figure 1.4. Low-power operation requires both low voltage and low current. Moreover, high switching current requires large transistors to provide sufficient drive current, diminishing the scalability advantages of ionic memories. It is desirable to control the switching current below 10 ma. It is found that by introducing a thin oxide layer within GeSe chalcogenide film, the switching current for an Ag/GeSe/Pt device (diameter of 2.5 mm) can be reduced to as low as 1 na [26]. Some studies even claim much lower switching current, for example, 10 pa for Cu/SiO x devices and 5 pa for Cu/Ta 2 O 5 devices [55, 56]. The feasibility of such low operation current needs to be further tested in large memory arrays and product-like operation conditions. In many ionic memories, the first switching cycle is different from the following cycles, which is also known as the electroforming cycle. Switching voltage of Cu/ SiO x devices in the electroforming cycle is found to scale linearly with the oxide thickness [53]. This thickness dependence can be explained by the fact that the formation of conductive path(s) requires the drift of ions through the whole thickness

16 16j 1 Ionic Memory Technology (a) 1.E+0 1.E-1 ASP As 2 S 3 Set switching current (A) 1.E-2 1.E-3 1.E-4 1.E-5 Si 3 N 4 ZnCdS TiO x GeS MSQ 1.E-6 GeSe 1.E Set switching voltage (V) 3.0 (b) 1.E+0 1.E-1 MoO x Set switching current (A) 1.E-2 1.E-3 1.E-4 1.E-5 Cu 2 S GeSe GeS CuC Ta 2 O 5 1.E-6 SiO x WO 3 1.E Set switching voltage (V) 3.0 Figure 1.4 Distribution of set switching current and voltage for Cu þ -based (a) and Ag þ -based (b) ionic memory devices. of the film. The switching voltages after the forming cycle are nearly independent of the film thickness. An intuitive explanation for this thickness independence is the incomplete dissolution of the Cu filament(s) after the forming process [45]. Another possible reason is that ion transport is no longer a rate-determining factor after the electroforming cycle [53]. As described in Section 1.2.1, the set switching process involves the following steps: (1) anodic dissolution of active electrode: M! M z þ þ ze ; (2) drift of the

17 1.4 Electrical Characteristics of Ionic Memories j17 cations M z þ across the solid electrolyte under electrical field; and (3) cathodic reaction at the inert electrode by the nucleation and growth of the metal M electrodeposits: M z þ þ ze! M. It is still controversial on which step dominates the switching process. A study on Cu/Cu 2 S devices shows that the migration of Cu þ (step 2) is the dominating step in the set switching process because measurements show that the electrochemical reaction rate is much higher than the Cu þ ion diffusion rate [45]. However, an exponential dependence of switching voltage on the switching rate is observed on Cu/SiO x devices. An estimation of the ion hopping distance in the ion migration step suggests that this step cannot explain this exponential dependence. Therefore, it is proposed that the set switching kinetics of Cu/SiO x devices is determined by the electrocrystallization process at the cathode (step 3) [53]. More studies are needed to further elucidate the dynamics of the ionic switching process, which may have a significant impact on the control of switching parameters and optimization of switching speed. Since both the diffusivity of ions and the rate of electrochemical reactions decrease with cooling, it is expected that the switching voltage of ionic memories will increase at lower temperature because the reduction of ion activity needs to be compensated by higher electrical field. In Cu/Cu 2 S devices, both set and reset switching voltages increase exponentially with the inverse of temperature (1/T ) [45]. This temperature dependence of switching voltages correlates well with the temperature dependence of the measured Cu þ diffusion coefficient [45]. Since the formation of one filament can significantly reduce the resistance of the solid electrolyte, both voltage drop on the device and the electrical field in the electrolyte may decrease abruptly. This makes it difficult for more filaments to form subsequently; that is, the filament formation in the ionic switching process is more or less self-limiting. Therefore, the on-state conduction of ionic memories is likely to be a few localized paths, rather than large amount of distributed paths. This prediction has been confirmed by the area dependence measurement of ionic memories. For example, the LRS resistance of Cu/CuC devices varies less than one order of magnitude over four orders of magnitude change of device size [60]. In other words, the LRS resistance is nearly area independent. The HRS resistance, on the other hand, shows much stronger area dependence. Since the HRS resistance increases with the decrease in device size and LRS resistance is nearly unchanged, the on/off ratio (¼ HRS resistance/lrs resistance) is expected to increase when device size is reduced. This enhanced signal strength at smaller device size is considered a unique scaling advantage of ionic memory devices. The ionic switching model also clearly identifies these localized conduction paths as metallic filaments. The metallic nature of these filaments has been confirmed by the linear I V characteristics and the negative temperature coefficient of LRS resistance. For example, measurements have shown that LRS conductance of Cu/ CuC [60] and Cu/Cu 2 S [43] decreases with the increase in temperature. On the other hand, HRS conductance shows positive temperature coefficient and the conduction mechanism can be explained by thermally active transport. The on resistance of many RRAM devices has shown dependence on the programming current, which may have different explanations based on various

18 18j 1 Ionic Memory Technology switching mechanisms. Ionic memories have also exhibited a similar dependence; for example, the on resistance of Cu/Ta 2 O 5 decreases with the increase in the programming current. An almost linear dependence exists between the on resistance and the programming current on a logarithm logarithm scale [55]. This dependence of ionic memories can be generally explained by the enhancement of conductive filaments (i.e., lower resistance) under higher programming current. The measured cycling endurance of ionic memories varies from several hundred cycles to cycles. The impressive endurance of cycles is reported on Ag/GeSe devices [28]. As discussed later, several factors may cause reliability issues in ionic memories and reduce the cycling endurance. If strong cycling endurance can be achieved uniformly on a large array of ionic memories, it will become a key advantage for ionic memories and may significantly expand their applications Ionic Memory Array Characteristics Several companies have participated in ionic memory R&D and developed CMOScompatible ionic memory processing and architectures. Some of them have reported array-level characteristics with more accurate device parameters and statistics. Table 1.2 summarizes the array characteristics measured on three ionic memories: Cu/Cu 2 S (NEC/JSTA) [8], Ag/GeSe or Ag/GeS (Qimonda) [13, 61, 62], and Cu Te/GdO x (Sony) [63]. They are all made with standard CMOS process flow and the Table 1.2 Array characteristics of ionic memories. Company NEC/JSTA a) Qimonda Sony Tested array size 1 kbit 2 Mbit 4 kbit Material system Cu/Cu 2 S Ag/GeSe or GeS Cu Te/GdO x Technology node 250 nm CMOS 90 nm CMOS 180 nm CMOS Minimum tested cell size D 30 nm D ¼ 20 nm D ¼ 20 nm Memory structure 1T1R 1T1R 1T1R Programming (HRS! LRS) Voltage 1.1 V 0.6 V 3 V Current 10 ma 110 ma Pulse width 5 32 ms 50 ns 5 ns Erasing (LRS! HRS) Voltage 1.1 V 0.2 V 1.7 V Current 20 ma 125 ma Pulse width 5 32 ms 50 ns 1 ns Retention Measured 10 3 s under 35 mv 10 5 s@70 C C Projected 3 months 10 years 10 years R on /R off 10 2 V/10 3 V 10 4 V/10 11 V 10 4 V/ V Endurance cycles 10 6 cycles 10 7 cycles Operating temperature 110 C 130 C References [8] [13, 61, 62] [63] a) JSTA: Japan Science and Technology Agency.

19 memory cell uses a 1-transistor 1-resistor structure (1T1R) structure. The access transistor not only provides selection function but also controls the switching current. Array characterization provides more accurate results on some parameters; for example, switching speed as fast as several nanoseconds is measured on Cu Te/ GdO x devices [63]. The switching voltage and current in Table 1.2 are measured in AC operation, and the switching voltages are generally higher than DC voltages in Table 1.1. Array statistics have shown reasonably good uniformity of device parameters (e.g., switching voltage and current, on and off resistance, etc.) across the array Comparing Ionic Memory with Other Memories 1.4 Electrical Characteristics of Ionic Memories j19 Figure 1.5 compares the performance of ionic memories with other mature and emerging memory technologies, based on switching speed, switching energy (per bit), and operation voltage. Data used in this figure are taken from ITRS Emerging Research Device (ERD) chapter [1]. The label of ionic effect resistive switching memory is highlighted in bold. In addition to the ionic effect, electronic effect and thermal effect are the other two types of resistive switching memories (i.e., RRAM). The X- and Y-axes in Figure 1.5 represent switching energy and switching speed, respectively. Size of the symbols is proportional to the typical operation voltage of each memory. Although SRAM and DRAM have the best switching characteristics represented by fast speed, low energy, and small operation voltage, they cannot retain information without power. Mainstream NOR and NAND flash memories require high operation voltage and switch slowly due to the tunneling-based programming/ erasing mechanism. Among the emerging memory technologies, ionic memories have demonstrated some promising switching characteristics, including low operation voltage, low switching power, and fast switching speed. 1.E+0 NOR Charge trapping Speed (s) 1.E-3 1.E-6 1.E-9 NAND Electronic effect Thermal effect Ionic effect DRAM PCM FeRAM MRAM SRAM 1.E-12 1.E-18 1.E-15 1.E-12 1.E-09 Write energy (J/bit) Figure 1.5 Comparison of ionic resistive switching devices with other memory technologies on switching speed (Y-axis), write energy (X-axis), and operation voltage (size of the symbols).

20 20j 1 Ionic Memory Technology 1.5 Architectures for Ionic Memories Ionic memory devices can be integrated into CMOS in the BEOL process. However, the density of CMOS-integrated ionic memory architecture is usually constrained by the access transistors, and the scaling advantage of ionic memories is not utilized. With simple two-terminal structure, ionic memories are suitable for crossbar architecture that can achieve high memory density. Some hybrid/cmos architectures are also proposed to take advantage of both the mature infrastructure of CMOS and the density advantages of crossbar arrays CMOS-Integrated Architecture Figure 1.6 illustrates a cross-sectional view of ionic memories integrated into CMOS, where the ionic memory elements are built at via locations. This architecture is particularly suitable for MIM devices where the I layer can be formed by some treatment of the bottom electrode (e.g., oxidation) because the CMOS process flow needs to be only slightly modified to incorporate these memory elements. For ionic memory elements formed by deposition or sputtering, additional steps for patterning are required. Building memory devices at via locations incurs no area penalty in CMOS layout. The access transistors not only provide selection functions but also control the switching conditions (e.g., current limit). It has been found that the current control during switching could significantly impact the uniformity of device characteristics. Almost all the functional ionic memory arrays demonstrated so far have been built in CMOS architecture. The CMOSintegrated architecture is particularly useful as testing vehicles in R&D stage. However, since CMOS-integrated architecture does not truly utilize the scalability of ionic memories, it may not make ionic memories much more competitive than conventional memories. Figure 1.6 Cross-sectional view of CMOS-integrated architecture for ionic memories.

21 1.5 Architectures for Ionic Memories j21 Word lines (top electrode) Bit lines (bottom electrode) Solid-state electrolyte Figure 1.7 Crossbar architecture for ionic memories Crossbar Array Architecture In crossbar architectures, the memory devices are built at the crossing points of orthogonally arranged horizontal and vertical access lines, as shown in Figure 1.7 [64, 65]. Obviously, higher memory density can be achieved in crossbar architectures than in CMOS architectures. If these crossbar memory arrays can be stacked in 3D structures, the memory density can be further increased. On the other hand, there are still severe challenges associated with the crossbar architecture, including the control of read/write disturbance, lack of signal gain, array size constraint determined by the asymmetry of device switching characteristics, and so on. Crossbar array also requires good uniformity of device switching parameters. In addition, asymmetric I V characteristics are desirable for crossbar architectures. In planar Ag/a-Si devices [33] and Ag/a-Si-nanowire devices [34], rectifying I V characteristics have been reported. However, most ionic memory devices have shown symmetric ohmic conduction in on state and may require diode-like selection devices. Since the crossbar itself is a passive array, external CMOS circuitry is required for programming, erasing, and readout. In order to have distinguishable states, the switching devices need to have high on/off ratio; otherwise, an advanced sensing scheme is required. Two-terminal selection devices (e.g., diodes) are desirable for crossbar architectures. Although some two-terminal selection devices have been proposed, there is still no proven solution of selection devices for truly functional crossbar memory arrays [66] CMOS/Hybrid Architecture In the so-called CMOL architecture, crossbar of two-terminal switching devices can be built on top of CMOS circuits and is connected to CMOS circuits through interface pins [67]. Each switching device plays the role of one-bit memory cell, while the CMOS subsystem may be used for coding/decoding, sensing, input/output functions, and so on. This hybrid architecture utilizes the advantages of both CMOS and crossbar architectures. Although it is believed that CMOL provides various