1. HP's memristor and applications 2. Models of resistance switching. 4. 3D circuit architectures 5. Proposal for evaluation framework

Transcription

1 OUTL LINE 1. HP's memristor and applications 2. Models of resistance switching 3. Volatility speed tradeo ffs 4. 3D circuit architectures 5. Proposal for evaluation framework

2 HP S MEMRISTOR memristor = memory + resistor October 29 HP s memristor = TiO 2 resistance change due to oxygen vacancy migration circuit theory + TiO 2 devices = HP s memristor L.Chua, S.Kang several groups, R.S.Williams T.W.Hickmott first L.Chua, IEEE Trans. Circuit Theory (1971); L.Chua et al. Proc. IEEE (1976) pure memristor vs. memristive small subset: T.W.Hickmott JAP (1962); R.Meyer et al. APL (25); B.J.Choi et al. JAP (25); C.Yoshida et al. APL (27); K.M.Kim et al. APL (27); K.Tsunoda et al. APL (27) v = R(w) i dw/dt = i unipolar/bipolar l RRAM, CBRAM, PCR RAM etc. are all memristive devices no simple dynamical model so far for experimental devices still okay for most applications (using feedback) applications: memories, FPGAs, electronic synapse, analog circuits (trimming) just a small biased subset (the&exp) for mem: Baek et al. IEDM (25); D.Strukov et al. J. Nanoscience&Nanotechnol (27); J.Green et al. Nature (27); S.H.Jo Nano Letters 9 87 (29); FPGAs: D.Strukov et al. Nanotechnol (25); D.Strukov et al. IEEE Tran.Nanotechnol (27); Q.Xia et al. Nano Letters (29); ANNs: K.Likharev et al. Ann. New York Acad. Sci (23); G.Snider Nanotechnology (27); analog: S.Shin et al. Proc. ICCCAS (29) starting point (t=) R 3 >> 2 >> 1 resistance change range R.S.Williams IEEE Spectrum (28); J.Yang et al. Nature Nano (28); D.Strukov et al. Nature (28) 3 v = R(w,i,t) i i= sin[ t] 2 dw/dt = f(w,i,t),, ) q 1 3 >> 2 >> 1 i-v collapses to straight line at high frequencies for pure memristors nonlinear i-v with no hysteresis (i.e. at small biases) & nonlinear ionic drift = not a pure memristor good starting point: M.Pickett et al. JAP (29) J.Borghetti (priv.comm.) i t v

3 BULK vs INTERFACE BIPOLAR RESIST TIVE SWITCHING Dopant N D (x)/n DO bulk theory semiconductor with N A fixed and N D (x) mobile ions w OFF: n + n p n n p n time t/t ON: n + n n + N A D.Strukov et al. Small (29) inte erface OFF ON October 29 ONOFF I. barrier height/leakage modulation TO CMO e.g. two system: R.Meyer et al. Proc. NVMTS (28) tial φ/(e G /e) Poten.2 Current v t Voltage Length x/l 1 1D model but initial conditions for 3D (i.e. after forming) are hard to simulate and experiment H.Yang et al. Nature Mat (29) IIa. barrier width/bridging due to radial ion motion Ag H 2 O Pt Ag H 2 O Pt e.g. in CBRAM: X.Guo et al. APL 91 1 (27) chalcogenide electrolytes: M.N.Kozicki et al. J Non-Crys. Solids (26) IIb. barrier width/bridging due to vertical ion motion Co oncentration (log sc cale) gap profile Barrier width grossly simplified picture, mix of all mechanisms in reality E=1,1,.1 MV/cm time, s D.Strukov et al. (preliminary data)

4 WRITE SPEED VS. RETENTION linear ionic transport store ~ write ( v ) ( v V ) I V D nonlinear effect due to temperature and/or electric field e.g. temperature only: U A store V k T write I V V T U k T B store B write ~ ( e e ) V T D.Strukov et al. Appl.Phys.A (29) A October 29 other sources of nonlinearity? Buttler Volmer reactions R.Waser et al. Adv.Mat (29) Electrochemical effects e/ write store L=1 nm 3 nm 1 nm 3 nm 1 1 ionic 1 A B conductor mobile.1.2 U B (ev).3.5 interacting ions D.Strukov (unpublished) Joule heating M.Janousch et al. Adv.Mat (27) XRF map infrared K K map voltage, V temperature on I-V curre ent, ma perform 3D coupled electrothermal simulations fit experimental data using equivalent circuit J.Borghetti et al.jap (29) to appear strong nonlinearity in ionic transport required for high retention, even more for half select 11 K TiO 2 (ρ I,κ I ) OFF state d OUT w OFF d C metallic channel (ρ C,κ C ) electrode (ρ E,κ E ) L v R C r R ON extract geometry from fitting ON state z d ON w ON D.Strukov et al. MRS (29) ) Temperature (K) Local ma) I ( K 14K 3K INTERMEDIATE ON OFF V (V) ON Domain fitted on data Extrapolation OFF 1 2 I (ma) SHORT 3

5 3D STACKING FOR CMOL CIRCUITS peripheral addr ess word address read/write drive word line decoder decoder predecoder October 29 d d hybrid stack of thin film crossbar arrays (m s) n wires main idea: area + peripheral interface word line decoder switching s 1 st 2 nd 3 rd decoder control lines decoder predecoder area distributed N 4 data lines 1 st 2 nd just few examples: M.-J.Lee IEDM 85 (28) M.Johnson IEEE J Solid State Circuits (23) crossbar s CMOS tilted crossbar area interface 2F 2F N N 2 theory: K.Likharev Interface (25); D.Strukov et al. PNAS (29) N 3 rd virtual crossbar xpoint in 1 st crossbar wire via drive/sense data xpoint in 2 nd address D.Strukov (unpublished) N 4 total.. but only (N) 2 per nanowire 2 switching nanowire 1 CMOS via bit line sense/driver CMOS xpoint element less semi-selected devices for read op. parallel write for current controlled devices less maximum current density but less dense D.Strukov (unpublished) CMOS only CMOS +xbar xbar and exp with just one xbar : Q.Xia et al. Nano Letters (29)

6 PROPOSAL FOR EVALUATION METRIC intrinsic circuit and device tradeoffs electromigration issues in wires, smaller blocks (less dense), and low throughput smaller readout margins etc potentially volatile device resistance low high switching speed slow fast e.g. reset current scaling thkw (K/W) V RESET (V) L=3 nm nm.1 c =2 K/W-m (e.g. Ti) R/L.1 1 RL 3 1 slow RC likely volatile and/or large switching voltages low endurance, bad repeatability e.g. due to higher electric field and temperatures axial radial =6 K/W-m (e.g. TiO 2 ) =1 K/W-m (e.g. SiO 2 ) 1 3 =6 K/W-m c =2 K/W-m ΔT=, c =.8-cm 1.3 L=3 nm.1.1 I RESET (ma) 1 D.Strukov (in preparation) proposa al for software framework electronic device characterization: (1) nonlinearity in I-V shape; (2) nonlinearity in switching; (3) nature of the switching compliance for reset and set; (4) polarity of switching; (5) asymmetry of switching threshold voltages; (6) switching speed; (7) retention; (8) nominal set/reset voltage/current values; (9) variations in I-V shape upon cycling (repeatability); (1) endurance; (11) device yield; (12) forming step, etc. design constrains: density, cost, speed, power power density, throughput fabrication consideration: design rules s, electromigration specs, electorode thermal and electrical resistivity, manufacturing cost main goals October 29 material device characterization published device data OPTIMAL CIRCUIT ARHCITECTURE via parametric search: circuit architecture, block size, sensing/ biasing scheme, voltage scaling, def. tolerance scheme etc. explore for more then drop-in replacement expose important missing device and circuit information help in focusing on the most important issues