The challenges of configurable hybrid Memristor-CMOS Integrated circuits fabrication: Physics and Materials Science
|
|
- Cecil Johnston
- 6 years ago
- Views:
Transcription
1 The challenges of configurable hybrid Memristor-CMOS Integrated circuits fabrication: Physics and Materials Science Gilberto Medeiros-Ribeiro HP Labs
2 Outline Context Memristor basics Memristor fabrication and incorporation in reconfigurable logic CMOS Final thoughts 2
3 Data Storage 170%/year Compound Growth rate ( ): 16x Moore s law density increase; 56x increase in storage exabytes of online data 1 Hard disks are cheap, but latency is the bottleneck Flash as a hard disk replacement is on course DRAM roadmap ends in 2015 Need for universal memory! Preferable Non-volatile 1 Physics of data, Marissa Myers, Google 3
4 Why DRAM and Flash are approaching scaling limits? DRAM Capacitors can t get small Transistors leak through the gate Short channel effects S-D leakage FLASH Tunnel oxide can t get thinner Faster degradation 4
5 Non-volatile storage options F=technology node Memory Element Cell size CMOS Integration Switch Mechanism Bipolar /Unipolar Power Scaling Ultimate Scaling Limit Setreset Times Maturity Metal Oxide * 0.5F 2 Excellent E-field Bipolar Good Good Conducting channel size (5nm) Good Lab-tofab PCM *4F 2 Demonstrated Temperature Unipolar Poor Fair Stable nanocrystal size (~10nm) Good Prototyp e Flash *4F 2 Excellent E-field N/A Good Fair Capacitor size Fair Product FeRAM *4F 2 Demonstrated E-field Bipolar Good Poor Domain size (20nm) Good Product MRAM *4F 2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty product 5
6 Non-volatile storage options F=technology node Memory Element Cell size CMOS Integration Switch Mechanism Bipolar /Unipolar Power Scaling Ultimate Scaling Limit Setreset Times Maturity Metal Oxide * 0.5F 2 Excellent E-field Bipolar Good Good Conducting channel size (5nm) Good Lab-tofab PCM *4F 2 Demonstrated Temperature Unipolar Poor Fair Stable nanocrystal size (~10nm) Good Prototyp e Flash *4F 2 Excellent E-field N/A Good Fair Capacitor size Fair Product FeRAM *4F 2 Demonstrated E-field Bipolar Good Poor Domain size (20nm) Good Product MRAM *4F 2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty product 6
7 Memristor x PCRAM: pro s and con s Parameter Memristor PCRAM Operation Bipolar Unipolar 1T/1R Yes Yes X-bar Yes Yes, if incorporates series diode CMOS compatible Yes, for both FEOL and BEOL Maturity Incipient Decades Not FEOL compatible bit size scalability Good (down to 5nm) Uncertain (ok down to 50nm) Retention Good Worsens with decreasing size 7 Copyright 2010 Hewlett-Packard Development Company, L.P.
8 The memristor as the fourth element RESISTOR v = R i CAPACITOR dq = C dv INDUCTOR dφ = L di MEMRISTOR dφ = M dq rigorous definition v ( t) = R[ w, i( t)] i( t) dw ( t) = dt f [ w, i( t)] L. O. Chua, IEEE Trans. Circuit Theory 18, 507 (1971) Quasi-static conduction eq.- R depends on state variable w Dynamical equation: Evolution of state in time
9 What makes the memristor fundamental? Current vs. Sinusoidal Voltage Resistor Time Capacitor Current Voltage Current dv = R di dq = C dv Inductor Memristor Current dφ = L di dφ = M dq Voltage Voltage
10 Simple Phenomenological Description V w Undoped: Doped: Doped D A Undoped R OFF Ionic drift: dw( t) dt = µ V R D ON i( t) Electronic current: w( t) v( t) = RON + ROFF 1 D i w 3 w 2 w 1 t w( t) i( t) D v = M(q(t)) i(t) 0 i = sin[wt] w 3 >>w 2 >>w 1 R ON R ON w/d R OFF (1-w/D) µ ( ) = 1 V M q ROFF R q 2 ON ( t ) D Strukov, Stewart, Snider & Williams, Nature (2008)
11 4 properties of memristive systems in 3 sweeps: a dynamical device 134 Memristive Properties Continuous states Zero-crossing Frequency dependent Bias dependent 2
12 How can one make such a device? Different materials choices, like TiOx, NiOx, CuOx, etc. Metal electrodes 12
13 TiOx: a switching material 3.0/3.2 ev semiconductor dielectric ε ~ 80, birefringent pigment, photocatalyst, O 2 sensors TiO 2 : 1x Ti x O 2- Relatively easy to reduce Vacancy diffusion ~1eV 13
14 MIM devices Metal/oxide/metal junction Metallic nanowire (bottom electrode) Metallic nanowire (top electrode) Switching materials (e.g. TiO 2 ) Typical device fabrication: sputtered deposited films of oxides; e-beam deposition of Pt TEM cross-section Pt top electrode TiO 2 TiO 2-x Pt bottom electrode Ti adhesion layer SiO x Si J. Yang et al., Adv. Mat, (2010)
15 How can one make a memory from this? 15
16 Cross bar concept 16
17 Cross bar concept V - + threshold 0 or 1 Sense amps 17
18 Cross bar concept V/2 -V/2 - + threshold 0 or 1 Sense amps 18
19 Cross bar concept V/2 -V/2 - + threshold 0 or 1 Sense amps 19
20 Cross bar concept V/2 -V/2 = Sense amps threshold 0 or 1 20
21 A memristor X-bar implementation Ability to scale to aggressive technology nodes 50 nm wire width 21
22 Nonlinear devices required! Since the resistance of each device can be a very non linear function of the voltage, this non-linearity and asymmetry can be used in adjacent devices to isolate bits. 10 Current (A) OFF -6 #1-999 cycle # 1000 cycle ON Current (A) Voltage (V) Voltage (V)
23 Putting devices onto a CMOS platform Develop simple models for realistic circuit design Known and well tested CMOS circuitry Match very different technologies Flexible voltage adjustments 23
24 Simple Spice Model for Circuit Verification State of the art model at time of design, a more detailed model exists now. Bench Data provided by HPL Junction IV Characteristics Ion Ioff , E-06 Current (A) , E Voltage (V) Simplified Model Ik = α sinh( β *Vk) State Alpha Beta Avg of RMS error OFF 2.29E E-08 ON 1.73E E-08 Actual device model used for CMOS verification Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp
25 Hard Coded Die Configuration half-adder A in S out start B Q FF D Tim e C in out LSB 0 1 time MSBB In order to mitigate design risk, and speed up test development, CMOS pre-configured 1 1 Q 1 1
26 SNIC Architecture
27 CMOS Integration Challenges Challenges: Unstable process for nanowires Design needed to enable process development Driver circuitry for a dynamical load Different operating voltages Implication: Design had to provide a flexible interface for fab and lab quality imprint tooling Larger than necessary alignment tree Risks Unknown Fab-Lab integration challenges
28 Quartz NIL Molds Bottom Electrode Top Electrode Holey Pad Structure Master mold patterned by EBL. Daughter molds duplicated on QZ using NIL. Nanowires:100 nm HP. Feature height: 60 nm. Pad size: 10 µm by 15 µm. 28
29 CMOS Substrate 3 metal layer CMOS circuits, [0, 3.3V] operation. Chip finished with TEOS and CMP. Fabricated with 0.5 µm technology at HP Corvallis fab in Oregon 29
30 Integrated Hybrid Circuits (c) 100 nm 12 nm Pt 36 nm TiO2 9 nm Pt 2 nm Ti 30
31 Wiring of Logic Gates Using Memristors 31
32 Logic Functions Successfully Implemented NOT gate A C AND gate A B C 1 OR gate A B C 1 32 Reading voltage: 1.7 V. CMOS: 3.3V
33 Logic Functions Successfully Implemented NAND gate A B C 1 NOR gate A B C 1 D Flip-flop D Clk Q Q 33
34 Reconfigurability Demonstrated ON OFF INPUT INPUT OUTPUT Reading voltage: 0.5 V OUTPUT Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp
35 Main points Scalability: 4F 2 feasible, stacking also feasible CMOS compatible process Low power (not discussed) Non-volatility Faster and more resilient than FLASH, with better scaling perspectives 35
36 Acknowledgements: Julien Borghetti John Paul Strachan Dmitri Strukov Feng Miao Wei Yi Matthew Pickett Douglas Ohlberg Qiangfei Xia Hans Cho Xuema Li Tan Ha Cuong Le Fred Perner Tsung-Wen Lee Mike Cumbie Phil Kuekes Warren Robinett Alexandre Bratkovski Dick Carter Rick Amerson Pascal Vontobel Erik Ordentlich Gadiel Seroussi Wei Wu Max Zhang Hisham Abdahla Shakeel Quresh Greg Snider Janice Nickel Stan Williams Information and quantum Systems Lab: Photonics, CeNSE & Nanoelectronics groups Lab Director: Stan Williams
37 The Questions People Ask Switching voltages/currents (volts/na-100µa) Write/Erase/Read speed and energy (<10ns, pj) ON/OFF ratio (>1000:1) Retention time (years even millennia) Scaling limits (5nm? - >4 terabits/sq cm) Endurance and failure mechanisms (heating) Nature of ON and OFF states (metal/insulator) Devices are evolving rapidly with understanding
Finding the Missing Memristor
February 11, 29 Finding the Missing Memristor 3 nm Stan Williams HP 26 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice Acknowledgments People
More informationFrom Spin Torque Random Access Memory to Spintronic Memristor. Xiaobin Wang Seagate Technology
From Spin Torque Random Access Memory to Spintronic Memristor Xiaobin Wang Seagate Technology Contents Spin Torque Random Access Memory: dynamics characterization, device scale down challenges and opportunities
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationThe switching location of a bipolar memristor: chemical, thermal and structural mapping
IOP PUBLISHING Nanotechnology 22 (2011) 254015 (6pp) The switching location of a bipolar memristor: chemical, thermal and structural mapping NANOTECHNOLOGY doi:10.1088/0957-4484/22/25/254015 John Paul
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationRRAM technology: From material physics to devices. Fabien ALIBART IEMN-CNRS, Lille
RRAM technology: From material physics to devices Fabien ALIBART IEMN-CNRS, Lille Outline Introduction: RRAM technology and applications Few examples: Ferroelectric tunnel junction memory Mott Insulator
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationResistive Random Access Memories (RRAMs)
Resistive Random Access Memories (RRAMs) J. Joshua Yang HP Labs, Palo Alto, CA, USA (currently) ECE Dept., Umass Amherst (Jan/2015 - ) 1 Copyright 2010 Hewlett-Packard Development Company, L.P. Resistive
More informationThin Film Transistors (TFT)
Thin Film Transistors (TFT) a-si TFT - α-si:h (Hydrogenated amorphous Si) deposited with a PECVD system (low temp. process) replaces the single crystal Si substrate. - Inverted staggered structure with
More informationNovel Devices and Circuits for Computing
Novel Devices and Circuits for Computing UCSB 594BB Winter 2013 Lecture 4: Resistive switching: Logic Class Outline Material Implication logic Stochastic computing Reconfigurable logic Material Implication
More informationTrends in Nanotechnology: Self-Assembly and Defect Tolerance
Trends in Nanotechnology: Self-Assembly and Defect Tolerance (Invited paper submitted to MSTNEWS 3 January 2001) T. I. Kamins and R. Stanley Williams Quantum Science Research, Hewlett-Packard Laboratories,
More informationResistive Memories Based on Amorphous Films
Resistive Memories Based on Amorphous Films Wei Lu University of Michigan Electrical Engineering and Computer Science Crossbar Inc 1 Introduction Hysteretic resistive switches and crossbar structures Simple
More informationN ano scale l S il ii lco i n B ased N o nvo lat l i atl ie l M em ory r Chungwoo Kim, Ph.D.
cw_kim@samsung.com Acknowledgements Collaboration Funding Outline Introduction Current research status Nano fabrication Process Nanoscale patterning SiN thin film Si Nanoparticle Nano devices Nanoscale
More informationMTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application
2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112 MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application Takahiro Hanyu 1,3, S. Matsunaga 1, D. Suzuki
More informationSemiconductor memories
Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor
More informationMechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices
Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices Rashmi Jha and Branden Long Dept. of Electrical Engineering and Computer Science University of Toledo Toledo,
More informationGold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications
Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications D. Tsoukalas, S. Kolliopoulou, P. Dimitrakis, P. Normand Institute of Microelectronics, NCSR Demokritos, Athens, Greece S. Paul,
More informationA short history of memristor development. R. Stanley Williams HP Labs
A short history of memristor development R. Stanley Williams HP Labs Historical Background During the 1960's, Prof. Leon Chua, who was then at Purdue University, established the mathematical foundation
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationWindow Function Analysis of Nonlinear Behaviour of Fourth Fundamental Passive Circuit Element: Memristor
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 12, Issue 3, Ver. III (May - June 217), PP 58-63 www.iosrjournals.org Window Function Analysis
More informationPinched hysteresis loops are a fingerprint of square law capacitors
Pinched hysteresis loops are a fingerprint of square law capacitors Blaise Mouttet Abstract It has been claimed that pinched hysteresis curves are the fingerprint of memristors. This paper demonstrates
More informationElectrical and Reliability Characteristics of RRAM for Cross-point Memory Applications. Hyunsang Hwang
Electrical and Reliability Characteristics of RRAM for Cross-point Memory Applications Hyunsang Hwang Dept. of Materials Science and Engineering Gwangju Institute of Science and Technology (GIST), KOREA
More informationNovel Devices and Circuits for Computing
Novel Devices and Circuits for Computing UCSB 594BB Winter 213 Lectures 5 and 6: VCM cell Class Outline VCM = Valence Change Memory General features Forming SET and RESET Heating Switching models Scaling
More information3/10/2013. Lecture #1. How small is Nano? (A movie) What is Nanotechnology? What is Nanoelectronics? What are Emerging Devices?
EECS 498/598: Nanocircuits and Nanoarchitectures Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5) Lectures 2: ITRS Nanoelectronics Road Map (Sept 7) Lecture 3: Nanodevices; Guest Lecture by
More informationMoores Law for DRAM. 2x increase in capacity every 18 months 2006: 4GB
MEMORY Moores Law for DRAM 2x increase in capacity every 18 months 2006: 4GB Corollary to Moores Law Cost / chip ~ constant (packaging) Cost / bit = 2X reduction / 18 months Current (2008) ~ 1 micro-cent
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationSupporting Information
Supporting Information Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits Yuanda Liu, and Kah-Wee Ang* Department of Electrical and Computer Engineering National University
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationECE321 Electronics I
ECE321 Electronics I Lecture 1: Introduction to Digital Electronics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Textbook
More informationEE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More informationAdvanced Flash and Nano-Floating Gate Memories
Advanced Flash and Nano-Floating Gate Memories Mater. Res. Soc. Symp. Proc. Vol. 1337 2011 Materials Research Society DOI: 10.1557/opl.2011.1028 Scaling Challenges for NAND and Replacement Memory Technology
More informationMathematical analysis of a third-order memristor-based Chua oscillators
Mathematical analysis of a third-order memristor-based Chua oscillators Vanessa Botta, Cristiane Néspoli, Marcelo Messias Depto de Matemática, Estatística e Computação, Faculdade de Ciências e Tecnologia,
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationCircuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive
More informationInfluence of electrode materials on CeO x based resistive switching
Influence of electrode materials on CeO x based resistive switching S. Kano a, C. Dou a, M. Hadi a, K. Kakushima b, P. Ahmet a, A. Nishiyama b, N. Sugii b, K. Tsutsui b, Y. Kataoka b, K. Natori a, E. Miranda
More information1. HP's memristor and applications 2. Models of resistance switching. 4. 3D circuit architectures 5. Proposal for evaluation framework
OUTL LINE 1. HP's memristor and applications 2. Models of resistance switching 3. Volatility speed tradeo ffs 4. 3D circuit architectures 5. Proposal for evaluation framework HP S MEMRISTOR memristor =
More information3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer
3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer Makoto Takamiya 1, Koichi Ishida 1, Koichi Takemura 2,3, and Takayasu Sakurai 1 1 University of Tokyo, Japan 2 NEC Corporation,
More informationMultiple Gate CMOS and Beyond
Multiple CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi Outline 1. Ultimate Scaling of MOSFETs - 3nm Nanowire FET - 8nm Non-Volatile Memory Device 2. Multiple Functions of MOSFETs 3. Summary 2 CMOS
More informationMemory Trend. Memory Architectures The Memory Core Periphery
Semiconductor Memories: an Introduction ti Talk Overview Memory Trend Memory Classification Memory Architectures The Memory Core Periphery Reliability Semiconductor Memory Trends (up to the 90 s) Memory
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationA 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology M. Kim 1, J. Kim 1, G. Park 1, L. Everson 1, H. Kim 1, S. Song 1,2,
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationNanoimprint Lithography
Nanoimprint Lithography Wei Wu Quantum Science Research Advanced Studies HP Labs, Hewlett-Packard Email: wei.wu@hp.com Outline Background Nanoimprint lithography Thermal based UV-based Applications based
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationLecture 6 NEW TYPES OF MEMORY
Lecture 6 NEW TYPES OF MEMORY Memory Logic needs memory to function (efficiently) Current memories Volatile memory SRAM DRAM Non-volatile memory (Flash) Emerging memories Phase-change memory STT-MRAM (Ferroelectric
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft
ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated
More informationAdministrative Stuff
EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN
More informationPerpendicular MTJ stack development for STT MRAM on Endura PVD platform
Perpendicular MTJ stack development for STT MRAM on Endura PVD platform Mahendra Pakala, Silicon Systems Group, AMAT Dec 16 th, 2014 AVS 2014 *All data in presentation is internal Applied generated data
More informationHw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationA final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).
A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans.» All of
More informationDesign for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
More informationDevice 3D. 3D Device Simulator. Nano Scale Devices. Fin FET
Device 3D 3D Device Simulator Device 3D is a physics based 3D device simulator for any device type and includes material properties for the commonly used semiconductor materials in use today. The physical
More informationAN ABSTRACT OF THE THESIS OF
AN ABSTRACT OF THE THESIS OF Santosh Murali for the degree of Master of Science in Electrical and Computer Engineering presented on December 20, 2011. Title: Investigation of Bipolar Resistive Switching
More informationWouldn t it be great if
IDEMA DISKCON Asia-Pacific 2009 Spin Torque MRAM with Perpendicular Magnetisation: A Scalable Path for Ultra-high Density Non-volatile Memory Dr. Randall Law Data Storage Institute Agency for Science Technology
More informationFerroelectric HfO 2 Thin Films
Ferroelectric HfO 2 Thin Films May 12 th, 2015 JACKSON ANDERSON ELECTRICAL AND MICROELECTRONIC ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY Outline Introduction Background Project Objectives Experimental
More informationNeuromorphic computing with Memristive devices. NCM group
Neuromorphic computing with Memristive devices NCM group Why neuromorphic? New needs for computing Recognition, Mining, Synthesis (Intel) Increase of Fault (nanoscale engineering) SEMICONDUCTOR TECHNOLOGY
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationSupplementary Information for. Non-volatile memory based on ferroelectric photovoltaic effect
Supplementary Information for Non-volatile memory based on ferroelectric photovoltaic effect Rui Guo 1, Lu You 1, Yang Zhou 1, Zhi Shiuh Lim 1, Xi Zou 1, Lang Chen 1, R. Ramesh 2, Junling Wang 1* 1 School
More informationDigital Electronics Part II - Circuits
Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The
More informationSemiconductor Memory Classification
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 12 VLSI II 2005-2-24 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: Ted Hong and David Marquardt www-inst.eecs.berkeley.edu/~cs152/ Last Time: Device
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationChapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory
SRAM Design Chapter Overview Classification Architectures The Core Periphery Reliability Semiconductor Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. References
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution
More informationChapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two
More informationCMOS compatible integrated ferroelectric tunnel junctions (FTJ)
CMOS compatible integrated ferroelectric tunnel junctions (FTJ) Mohammad Abuwasib 1*, Hyungwoo Lee 2, Chang-Beom Eom 2, Alexei Gruverman 3, Jonathan Bird 1 and Uttam Singisetti 1 1 Electrical Engineering,
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationQuantum Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors
Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors Shih-Ching Lo 1, Yiming Li 2,3, and Jyun-Hwei Tsai 1 1 National Center for High-Performance
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an n-channel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationAssessment of Soft Errors due to Alpha Emissions from Presolder on Flip Chip Devices Rick Wong, Shi-Jie Wen, Peng Su, Li Li 10/30/09
Assessment of Soft Errors due to Alpha Emissions from Presolder on Flip Chip Devices Rick Wong, Shi-Jie Wen, Peng Su, Li Li 10/30/09 1 Introduction Cause of Soft errors a. Ion creates electron hole pairs
More informationLecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics
Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance
More informationDKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction
DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction Saraju P. Mohanty Dept of Computer Science and Engineering University of North Texas smohanty@cs.unt.edu http://www.cs.unt.edu/~smohanty/
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationAdvanced Topics In Solid State Devices EE290B. Will a New Milli-Volt Switch Replace the Transistor for Digital Applications?
Advanced Topics In Solid State Devices EE290B Will a New Milli-Volt Switch Replace the Transistor for Digital Applications? August 28, 2007 Prof. Eli Yablonovitch Electrical Engineering & Computer Sciences
More informationSelf-study problems and questions Processing and Device Technology, FFF110/FYSD13
Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems
More informationUltralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches Presenter: Tulika Mitra Swarup Bhunia, Massood Tabib-Azar, and Daniel Saab Electrical Eng. And
More informationNonvolatile Multi-level Memory and Boolean Logic Gates Based on a Single Memtranstor
Nonvolatile Multi-level Memory and Boolean Logic Gates Based on a Single Memtranstor Jianxin Shen, Dashan Shang, Yisheng Chai, Yue Wang, Junzhuang Cong, Shipeng Shen, Liqin Yan, Wenhong Wang, and Young
More informationBipolar resistive switching in amorphous titanium oxide thin films
Bipolar resistive switching in amorphous titanium oxide thin films Hu Young Jeong and Jeong Yong Lee Department of Materials Science and Engineering, KAIST, Daejeon 305-701, Korea Min-Ki Ryu and Sung-Yool
More informationRandom Access Memory. DRAM & SRAM Design DRAM SRAM MS635. Dynamic Random Access Memory. Static Random Access Memory. Cell Structure. 6 Tr.
DRAM & SRAM Design Random Access Memory Volatile memory Random access is possible if you know the address DRAM DRAM Dynamic Random Access Memory SRAM Static Random Access Memory SRAM Cell Structure Power
More informationSemiconductor Memories. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Paolo Spirito
Semiconductor Memories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Paolo Spirito Memory Classification Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory
More informationElectrical Characterization with SPM Application Modules
Electrical Characterization with SPM Application Modules Metrology, Characterization, Failure Analysis: Data Storage Magnetoresistive (MR) read-write heads Semiconductor Transistors Interconnect Ferroelectric
More informationAn Autonomous Nonvolatile Memory Latch
Radiant Technologies, Inc. 2835D Pan American Freeway NE Albuquerque, NM 87107 Tel: 505-842-8007 Fax: 505-842-0366 e-mail: radiant@ferrodevices.com www.ferrodevices.com An Autonomous Nonvolatile Memory
More informationEE141. EE141-Spring 2006 Digital Integrated Circuits. Administrative Stuff. Class Material. Flash Memory. Read-Only Memory Cells MOS OR ROM
EE141-pring 2006 igital Integrated Circuits Lecture 29 Flash memory Administrative tuff reat job on projects and posters! Homework #10 due today Lab reports due this week Friday lab in 353 Final exam May
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationCHAPTER I. Introduction. 1.1 State of the art for non-volatile memory
CHAPTER I Introduction 1.1 State of the art for non-volatile memory 1.1.1 Basics of non-volatile memory devices In the last twenty years, microelectronics has been strongly developed, concerning higher
More informationLecture 15: Scaling & Economics
Lecture 15: Scaling & Economics Outline Scaling Transistors Interconnect Future Challenges Economics 2 Moore s Law Recall that Moore s Law has been driving CMOS [Moore65] Corollary: clock speeds have improved
More information