Finding the Missing Memristor

Transcription

1 February 11, 29 Finding the Missing Memristor 3 nm Stan Williams HP 26 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice Acknowledgments People who did the work: Over 6 current and former members of the QSR Research group and 4 members of other HP orgs esp. Greg Snider, Duncan Stewart, Dimitri Strukov, Matthew Pickett, Julien Borghetti, and Jianhua Yang Our partners at UCLA & Caltech, Our partners at LBNL and NIST Supported in part by DARPA & IARPA February 11,

2 February 11, 29 The nanotechnology dilemma We say that nanotech is different, but then we try to build familiar objects with nano dimensions... We say that nanotech is interdisciplinary, but do we just work with the usual suspects? We say that nano is new but have we forgotten old lessons? February 11, 29 3 Overview of Presentation What is a Memristor? How do you make them? What are they good for? Configurable rectifiers and switches Crosspoint Memories Sequential Implication Logic Synaptic computation February 11,

3 February 11, 29 3 fundamental passive linear circuit elements Resistor 1827 Georg Ohm RESISTOR v = R i CAPACITOR q = C v INDUCTOR φ = L i Capacitor Volta / von Kleist & van Musschenbroek Benjamin Franklin Inductor 1831 Michael Faraday Joseph Henry February 11, s Leon Chua generalizes circuit theory to nonlinear systems of equations v i RESISTOR dv = R di CAPACITOR dq = C dv q INDUCTOR dφ = L di And sees that there is a hole where an obvious relation seems to be missing February 11,

4 February 11, 29 Realm of nonlinear circuits Realm of linear circuits Danger! Chaos! February 11, 29 7 Realm of nonlinear circuits Nanoelectronics will be nonlinear Realm of linear circuits Opportunity! Danger! Chaos! February 11,

5 February 11, 29 In1971, Chua postulates the memristor, but states that there is no known example i RESISTOR dv = R,di v dφ/dt = v CAPACITOR dq = C dv dq /dt = i q v dw dt R( w) i f () i INDUCTOR dφ = L di MEMRISTOR dφ = M dq φ MEMRISTIVE SYSTEMS L. O. Chua, Memristor - the missing circuit element, IEEE Trans. Circuit Theory 18, (1971). L. O. Chua and S. M. Kang, "Memristive devices and systems," Proc. IEEE, 64 (2), (1976). February 11, 29 9 Four Fundamental Nonlinear Passive Circuit Elements Resistor Capacitor Current dv = R di dq = C dv Inductor Memristor Current dφ = L di dφ = M dq Voltage Voltage February 11,

6 February 11, 29 Current vs. Time for Sinusoidal Voltage Bias Voltage Capacitance Current Resistance Memristance Inductance Time February 11, Years of reserch looking for molecular switches switching with sharp thresholds 1. 6 Positive Switching Voltage 2 Negative Switching Current Current (ma) Counts (N) 3 15 Counts (N) Voltage (V) Current (ma) Voltage (V) February 11, 29 M1213A 12 6

7 February 11, 29 O vacancy drift model for TiO 2-x switch As fabricated 2 nm TiO 2 TiO 2-x 3 nm TiO 2 TiO 2-x Positive voltage drifts oxygen vacancies left to increase total conductivity reduced oxidized February 11, Simplified Theory of Memristance V w TiO 2-x TiO 2 A dw( t) RON V dt D i( t) TiO2: D wt () wt () vt () RON ROFF 1 it () D D : TiO2-x: R OFF R ON M ) 1 V RON q ROFF q ( t ) D ( 2 Two coupled equations of motion R ON R One for the charged vacancies OFF One for the electronic transport (both versions of Ohm s law) Nature 453 (28) February 11,

8 February 11, 29 Look at current-voltage plots of the model voltage time ( 1 3 ) current ( 1-3 ) voltage time ( 1 3 ) current ( 1-3 ) w/l.5 w/l.5 current ( 1-3 ) time ( 1 3 ) charge flux voltage current ( 1-3 ) charge flux.3 time ( 1 3 ) voltage.6 February 11, Comparison between Theory and Experiment: : TiO 2 : Memristor! voltage current time ( 1 3 ) RTheory OFF /R ON = 5 v = 4 V voltage w/l Current (ma) Expt TiO Voltage (V) February 11,

9 t IEEE CPMT Chapter, Santa Clara Valley February 11, 29 Ionic Memristive Device (Hard Boundary Conditions) Voltage Current R OFF /R ON = 125 v = 1 V.1. Time ( 1 3 ) Voltage w/l..4 x1 3 Voltage Current Time ( 1 3 ) R OFF /R ON = 5 v = 2 V Voltage w/l..8 x1 3 no window function but w is not changing beyond [, D] February 11, Metal Oxide Resistive Switches Memory effects in oxides have been known for a while: Just a few examples: 5.µ I lim set by transistor V g 4.µ G. Dearnaley et al., Rev. Prog. Phys. (197): a review with 15 references Just a few recent references: V TFL -1.µ 2 en L 2-2.µ metal: Voltage (V) S. Seo et al., APL (23) Ni A. Chen et al. (25) B. J. Choi et al., JAP (25) Ti H. Sim et al., Microel. Eng. (25) Nb With time, data are becoming more reproducible: D. Lee et al., EDL (25) Zr A. Chen et al., IEDM 5 Cu TE A. Chen et al. (IEDM 5) 97.7% M. Kund et al., IEDM 5 Ag D. C. Kim et al., APL (26) Nb 84.1% N. Banno et al., IEICE TE (26) Cu(S) OFF ON T.-N. Fang et al., ICMTD 7 Cu Cu 2 O 5.% L. Courtade et al., ICMTD 7 Ni Cu W. Guan et al., APL (27) Zr 15.9% S.-W. Kim & Y. Nishi, NVMTS 7 Cu(S) D. Stewart, NVMTS 7 Ti 2.28% K.-C. Liu et al., NVMTS 7 Hf D. Lee et al., APL (27) Mo B. J. Choi et al. (25) D. Lee et al. (27) February 11, 29 slide courtesy K. Likharev 18 Current (A) 3.µ 2.µ 1.µ Percentage. ON-state: SCLC with s hallow traps OFF-state V TFL Current (ua) 9

10 February 11, 29 Semiconductor memristance is coupled ion-electron motion V I electronic current mobile donors fixed acceptors February 11, Slightly More Advanced Theory - Ions J J J ION J drift ION J solute diffusion ION drift ION q E sinh E / solute diffusion ION D fa 2 N qd x exp[ U /( k N/t = -J ION /x A B E February 11, 29 2 T )]/(1 Na J ION (x = ) = JION (x = L) = 1 ED EF e N' N 1 1 exp g k BT 3 ) 1 1

11 February 11, 29 Slightly More Advanced Theory e - s J e ELECTRON EL n EL E F x ( x). n EL N F C 1/2 E F EC e kbt E E ef k T F C B EF N Cexp EC e kbt 2 ezn ' en EL February 11, ON to OFF (v = 12v ) w a) OFF to ON (v = -12v ) w Dopant N D (x)/n DO w / L.2 t / t time N A w / L 1 t / t.1 N A f) R ON (w/l) R OFF (1-w/L) R ON (w/l) R OFF (1-w/L).2 b) g).2 -f /(E G /e) time t/t time t/t c) h) 5 Field E/E -5 Length x/l 1 Length x/l 1 February 11,

12 February 11, 29 Drift-Diffusion Model: Memristance 4 2 Current J/J -2-4 Charge q/q ( Flux f/f Voltage v/v = 12 sin[2(t/t )/.1] ) February 11, Microndevices 1x1 Top electrode Ti dioxide V V The Workhorse System: 5 nm electrodes by NIL C Bottom electrode ~3-3 nm TiO 2 Micro 1x1 TiO 2 5 nm Nano 1x17 February 11,

13 February 11, 29 5 nanometer /TiOx/ devices a 2 c V turn OFF ~1 us 1 b 4 Current ( na ) 2 TiO 2 TiO x V - 5 nm hp Virgin I-V Voltage ( V ) Current ( ua ) -1 -V turn ON ~1 ns Voltage ( V ) Switch ON ~1 ns, state is stable for (1 6?) years February 11, Vacancy location controls switch polarity a Current (na) 2 1 TiO2 TiOx I Current (na) -5-1 II TiOx TiO2 b Voltage (V) Voltage (V) Current (ma) 1 I Diode Memristor Current (ma) 1-1 II Diode Memristor Voltage (V) -1 1 Voltage (V) 2 February 11,

14 February 11, 29 Conclusions on Memristors The switching mechanism for the devices is field induced drift of positively charged O vacancies in TiO 2 that controls the resistance of the film This is the first experimental realization and physical model for a memristor the fourth nonlinear passive circuit element that has been missing for nearly 4 years We see that memristance arises naturally in systems where atomic and electronic equations of motion are coupled this is far more likely to be observed at the nanoscale February 11, What might memristors be used for? Non-volatile RAM Config Bits New forms of logic Electronic Synapse But need hybrid circuits! February 11,

15 February 11, 29 CMOS FPGAs The good: Massive parallelism Defect tolerant Simple design The bad: 8%-9% area is wires/configuration High capacitance high power The ugly: Defect characterization Compilation February 11, SNIC Strategy Start with CMOS FPGA February 11,

16 February 11, 29 SNIC Strategy 1. Remove interconnect and configuration bits February 11, SNIC Strategy 1. Remove interconnect and configuration bits 2. Compress logic 3. Add nano interconnect and configuration February 11,

17 February 11, 29 SNIC Strategy 1. Remove interconnect and configuration bits 2. Compress logic 3. Add nano interconnect and configuration Inexpensive CMOS design Inexpensive process (nanoimprint) Nano redundancy defect tolerance Small size, high yield low cost Low energy February 11, SNIC: Chip Demo Nanowire layer 2 Switching layer Nanowire layer 1 via CMOS layer Courtesy Qiangfei Xia February 11,

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