Resistive Memories Based on Amorphous Films

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1 Resistive Memories Based on Amorphous Films Wei Lu University of Michigan Electrical Engineering and Computer Science Crossbar Inc 1

Introduction Hysteretic resistive switches and

two-terminal devices Not limited by transistor

size 4F 2 Terabit potential Large connectivity

2 Introduction Hysteretic resistive switches and crossbar structures Simple structure Formed by two-terminal devices Not limited by transistor scaling Ultra-high density NAND-like layout, cell size 4F 2 Terabit potential Large connectivity Memory, logic/neuromorphic applications crossbar Structure single-cell structure 2

3 Resistive Switching Memory ITRS_ERD workshop, April

RRAM ECM Cell ElectroChemical Metallization Cell Switching type: bipolar Electric field-driven redox chemical effect Metal filament formation Electrode plays active role (Ag or Cu)

4 RRAM ECM Cell ElectroChemical Metallization Cell Switching type: bipolar Electric field-driven redox chemical effect Metal filament formation Electrode plays active role (Ag or Cu) Materials: chalcogenides (e.g. GeS, GeSe, ), other amorphous films (e.g. oxides, a-si, a-c, ) Ag/Ag-Ge-Se/Pt Schindler et al., Proc. IEEE Non-volatile Memory Technology Symp. 82,

ECM: Visualization of Filament Ag/SiO 2 /Pt

grows from the IE backwards toward the AE

branches pointing to the AE Single filament

filaments + - Ag Pt - 200nm Yang, Gao, Chang,

5 ECM: Visualization of Filament Ag/SiO 2 /Pt structure, sputtered SiO 2 film The filament grows from the IE backwards toward the AE Branched structures were observed with wider branches pointing to the AE Single filament dominates Completed filament Partially formed filaments + - Ag Pt - 200nm Yang, Gao, Chang, Gaba, Pan, and W. Lu, Nature Communications, 3, 732,

erasing After erasing Ag Ag Pt Pt Yang, Gao, Chang,

6 Visualization of Filament, TEM Ag/SiO 2 /Pt structure A single filament dominates the switching process Before erasing After erasing Ag Ag Pt Pt Yang, Gao, Chang, Gaba, Pan, and W. Lu, Nature Communications, 3, 732,

7 Compositional Analysis of the filament Ag filament in SiO 2 The filament was verified to be composed of elemental fcc Ag particles (i.e. not Ag ions or oxides) Thin Ag filaments are not stable and naturally break into discrete Ag particles High conductance can be maintained when the particles are closely spaced Yang, Gao, Chang, Gaba, Pan, and W. Lu, Nature Communications, 3, 732,

be composed of elemental fcc Ag particles Thin Ag filaments are not stable and naturally break

8 Compositional Analysis of the filament Ag filament in a-si HRTEM, showing the particles are (111) Ag with fcc structure Ag particles forming the filament 2 nm The filament was verified to be composed of elemental fcc Ag particles Thin Ag filaments are not stable and naturally break into discrete Ag particles Yang, Gao, Chang, Gaba, Pan, and W. Lu, Nature Communications, 3, 732,

0 Ag + Ag + 100nm Ag + Ag + g f c d e f g Ag + Ag + Ag + Ag + Ag + b 2.5 2.0 1.5 1.0 0.

9 Current (μa) Current (μa) Visualization of Ag Filament, in-situ TEM Bulk RRAM on W probe Ag + a W 100nm a-si Ag b a Ag c d e W Time (s) a-si d e f g0.0 Ag + Ag + 100nm Ag + Ag + g f c d e f g Ag + Ag + Ag + Ag + Ag + b c d e Time (s) g f W - 20nm 20nm 20nm 20nm W W W W 20nm W W 20nm W 20nm W 20nm W 20nm Yang, et al. Nature Communications, 3, 732,

nm (density > 10 10 /cm 2 ) CMOS compatible materials and processes Jo et al.

10 a-si RRAM Crossbar Structure Pillar structure Crossbar array Two terminal resistance switching device Ag inside a-si matrix Small cell size, < 50 nmx50 nm (density > /cm 2 ) CMOS compatible materials and processes Jo et al. Nano Lett., 8, 392 (2008) Kim, Jo, W. Lu, Appl. Phys. Lett. 96, (2010) 10

0 1 0-1 -2-3 10-6 10-7 10-8 10-9 10-10 10-11 10-12 -4-2 0 2 4 Voltage (V) -4-2 0 2 4 6 Voltage (V ) read1 read2

11 Current (na) Voltage (V) Current (100 na) Resistance Switching Characteristics Ag Pt Sneak path involves one reverse-biased cell Voltage (V) Voltage (V ) read1 read2 read3-2v -3.5V 6 I READ 50 on on off 0 Jo, Kim, W. Lu, Nano Lett., 8, 392 (2008) Lu 1200 Group Kim, Jo, W. Lu, Appl. Phys. Lett. 96, (2010) Time 11 (ns)

12 Measured Current (na) Current (A) Output (V) Endurance and Speed Endurance Cycles 10 4, 10 5 on off on off 10 6, Virgin Bias (V) Endurance Cycle Time (us) > 1e8 W/E endurance 1e6 on/off Can be switched within 50ns Jo et al. Nano Lett., 8, 392 (2008) Write/Read/Erase/Read pulse : 50nsec,5V /50usec, 0.7V /100nsec, -3.5V /50usec, 0.7V Kim et al, Appl. Phys. Lett. 96, (2010) 12

13 Multi-Level Storage up to 8 levels (3 bits) per cell demonstrated cell resistance controlled by the current-limiting control resistor Jo et al. Nano Lett. 9, (2009). Kim et al, Appl. Phys. Lett. 96, (2010) 13

Integrated Crossbar Array/CMOS System Crossbar array

top of CMOS CMOS provides address mux/demux RRAM

10Gbits/cm 2 CMOS units larger but fewer units needed.

external selectors or diodes 500nm Kim, Gaba, Wheeler,

14 Integrated Crossbar Array/CMOS System Crossbar array CMOS Low-temperature process, RRAM array fabricated on top of CMOS CMOS provides address mux/demux RRAM array: 100nm pitch, 50nm linewidth with density of 10Gbits/cm 2 CMOS units larger but fewer units needed. 2n CMOS cells control n 2 memory cells 1R array, no external selectors or diodes 500nm Kim, Gaba, Wheeler, Cruz-Albrecht, Srivinara, W. Lu Nano Lett., 12, (2012). 14

West Connections Integrated Crossbar Array/CMOS System North Connections via Pad East Data A Switch 1 East Data B Switch 2 East Address <1> South Connections Pad Via between

15 West Connections Integrated Crossbar Array/CMOS System North Connections via Pad East Data A Switch 1 East Data B Switch 2 East Address <1> South Connections Pad Via between nanowire and CMOS CMOS chip I/O terminal Switch N N Decoder n East Address East Address <n> Kim, Gaba, Wheeler, Cruz-Albrecht, Srivinara, W. Lu Nano Lett., 12, (2012). 15

Integrated Crossbar Array/CMOS System I-V of the integrated Crossbar/CMOS system Average 2.30 V Stan. dev. 0.

16 Integrated Crossbar Array/CMOS System I-V of the integrated Crossbar/CMOS system Average 2.30 V Stan. dev V Threshold voltage (V) Tight distribution from 256 devices measured Devices shown good on/off and intrinsic diode characteristics Kim, Gaba, Wheeler, Cruz-Albrecht, Srivinara, W. Lu Nano Lett., 12, (2012). 16

Integrated Crossbar Array/CMOS System - Crossbar array operation, array written followed by read - Programming and reading through integrated CMOS address decoders - Each bit written with a single 3.

17 Integrated Crossbar Array/CMOS System - Crossbar array operation, array written followed by read - Programming and reading through integrated CMOS address decoders - Each bit written with a single 3.5V, 100us pulse Stored/retrieved array 1 Stored/retrieved array 2 Results from a 40x40 crossbar array integrated on CMOS Kim, Gaba, Wheeler, Cruz-Albrecht, Srivinara, W. Lu Nano Lett., 12, (2012). 17

18 # in bins # in bins Integrated Crossbar Array/CMOS System 1 and 0 states are clearly distinguishable from the 1600 cells in the crossbar Target R on = 500k Original K 100K 500K 1M 5M 10M 50M 100M 500M Complementary K 100K 500K 1M 5M 10M 50M 100M 500M Kim et al. Nano Lett., 12, (2012). 18

19 Multi-Level Storage Different on-states can be obtained by changing Rs Tight resistance distribution can still be obtained for multi-level storage Kim et al. Nano Lett., 12, (2012). 19

20 From Lab to Fab Crossbar Inc - Startup company founded in 2010 to fabricate a-si based RRAM in commercial fab. Fully VC-funded, Silicon Valley HQ CMOS compatible process with superior proven performance Currently has ~ 20 full-time staffs Crossbar Inc s non-volatile memory technology RRAM array fabricated on 8 wafers in a commercial fab CMOS Compatible 3D Stackable, Scalable Architecture Low thermal budget process Architectures proven include multiple Via schemes and Subtractive etching 20

Model Development i G( w, v) v w f ( w, v) First order model: Two equations describing switching behavior w: state variable I-V equation, tunneling through a barrier with thickness of w-l with

21 Model Development i G( w, v) v w f ( w, v) First order model: Two equations describing switching behavior w: state variable I-V equation, tunneling through a barrier with thickness of w-l with barrier height wl 1/ 2 ev 4 wl 2m 2m 4 ea ev h 2 I e 2 2h( w l) 2 l is the length of the filament, determined by Eq. 2 ev 2 e h 1/ 2 Series resistor ev 2 (1) dl dt d 0 e V / E wl e V E wl 0 / kt E 2 0 ed d is the step length of the filament V I R S V a (3) 0 (2) E=aV RRAM R S w-l V a The voltage across the device V is related to I and applied voltage V a P. Sheridan, K. Kim, W. Lu, Nanoscale 3, 3833 (2011). 21

22 SPICE Model DC Sweep Direct SPICE simulation to predict RRAM switching dynamics. Threshold effect, multi-level, exponential dependence of switching time on voltage captured Rs= 500kOhm Filament length vs. applied voltage Device current vs. applied voltage Device voltage vs. applied voltage P. Sheridan, K. Kim, W. Lu, Nanoscale 3, 3833 (2011). 22

23 SPICE Model, Transient Effects write read SET SET RRAM switching transient effects captured in SPICE P. Sheridan, K. Kim, W. Lu, Nanoscale 3, 3833 (2011). 23

24 Redox Memory Valency Change Cell Materials: TiO 2, HfO 2, TaO x... Switching type: bipolar Electric field-driven redox chemical effect Oxygen exchange between two pre-defined oxide layers bulk effect or filament effect On/off, uniformity Oxide layer 1 switching layer Oxide layer 2 base layer

25 Valency-Change Devices Based on TaOx Bipolar switching Y. Yang, P. Sheridan, W. Lu, App. Phys. Lett. 100, (2012) 25

26 Valency-Change Devices Based on TaOx Possible device type 1 asymmetric -½ Vread Vread Sneak path problem in passive Crossbar arrays Possible device type 2 symmetric I READ -½ Vread ½ Vread Vread 26

Complementary Resistive Cell based on TaOx CRS switching Read 0 Read 1 Internal distribution of V O can be used to represent the cell state Both 0 and 1 can have a

27 Complementary Resistive Cell based on TaOx CRS switching Read 0 Read 1 Internal distribution of V O can be used to represent the cell state Both 0 and 1 can have a highresistive layer and are of high resistance at low bias All 4 states need to be accessed during CRS operation Y. Yang, P. Sheridan, and W. Lu, Appl. Phys. Lett. 100, (2012) 27

28 Acknowledgements Grad students: *Sung-Hyun Jo, *Kuk-Hwan Kim Siddharth Gaba, *Ting Chang Patrick Sheridan, ShinHyun Choi Jiantao Zhou, Chao Du, Jihang Lee, Wen Ma, *Eric Dattoli Wayne Fung, Lin Chen *Seok-Youl Choi, *Woo Hyung Lee Collaborators: Dr. N. Srinivasa, Dr. D. Wheeler, Dr. T. Hussain. Dr. J. Cruz- Albrecht, HRL Labs, Prof. Z. Zhang, Prof. P. Mazumder, Prof. M. Zochowski, UM, Prof. D. Strukov, UCSB, Prof. J. Hasler, GeorgiaTech, Prof. G. Guo, Prof. T. Tu, USTC, China Prof. R. Li, CAS, China PostDocs: Dr. Yuchao Yang *Dr. Zhongqing Ji * Dr. Qing Wan Visiting scholars: Dr. L. Liu *Xiaojie Hao Funding: National Science Foundation (ECS , CCF , ECCS , CNS , CAREER ECCS ). DARPA SyNAPSE program DARPA UPSIDE program Air Force MURI program, Air Force q-2deg program, Engineering Translational Research (ETR) Grant * alumni 28

Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices

Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices Rashmi Jha and Branden Long Dept. of Electrical Engineering and Computer Science University of Toledo Toledo,