Addressing Challenges in Neuromorphic Computing with Memristive Synapses

Transcription

1 Addressing Challenges in Neuromorphic Computing with Memristive Synapses Vishal Saxena 1, Xinyu Wu 1 and Maria Mitkova 2 1 Analog Mixed-Signal and Photonic IC (AMPIC) Lab 2 Nanoionic Materials and Devices Lab ECE Department, Boise State University, ID ORNL, 2012 June Boise 30, State 2016 University 1

2 Agenda Introduction Synapse Devices and Challenges Mixed-Signal Neural Learning Architecture Realizing Multibit Synapses Conclusion 2

3 Reinventing Computing Von Neumann computing in the nano-cmos regime + Massive transistor count, but. Device variability Dark silicon issue Not well suited for processing massively parallel data streams and pattern recognition tasks that come easy to a brain. US Office of Science and Technology (OSTP) RFI, June 2015: Create a new type of computer that can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy efficiency of the human brain DOE, Brain Initiative, AFOSR, DARPA, SRC 3

4 Brain-Inspired Neuromorphic System Our Current Research Focus Source: DARPA SyNAPSE Program 4

5 Revisiting Biological Inspiration A B C V spk,in Synapse Inhibitive Connection V spk, out Neuron t 1 t 2 t 3 Synapse Dendrites From Previous Neurons Neuron V mem V thr Axon V mem Neuron V spk,in V mem Soma Pre Post Δt<0 Δw Pre Post Δt>0 0 Δt Δt = t post t pre Synaptic placiticity Synapse V spk,in V spk, out V spk, out t fire Emerging understanding of neural computation from Computational Neuroscience Hierarchical spiking neural networks with localized learning Synapses strengthen or weaken by relative firing times of the pre- and postneurons Plasticity rules: Spike-Timing Dependent Plasticity (STDP) 5

6 Neuromorphic Computing with RRAMs WTA bus Output Layer Forward spike Backward spike Pre-synaptic neuron ReRAM synapse Post-synaptic neuron Input Layer WTA bus To achieve biology-like synapse density, emerging nanoscale devices are under consideration Resistive RAM (RRAM) or Memristors Chalcogenide-based Conductive Bridge RAM (CBRAM) devices from Mitkova Group at Boise State Three necessary criterions for the realization of neuromorphic hardware capable of deep learning: (1) non-volatility of the trained weights, (2) massive synaptic density, and (3) ultra-low-power operation. 6

7 CBRAM I-V Characteristics I-V Sweep Resistance 7

8 Stochastic CBRAM Behavior V TH_Set Distributions R ON Distributions The CBRAM switching behavior is stochastic The analog synapse value depends upon the electroforming process Weak bridge-> more intermediate resistance values The analog resistance value relaxes in few minutes to hours 8

9 Spike Timing Dependent Plasticity (STDP) 0.2 A V pre V post Δt>0 t V pre V post Δt<0 t B ΔGmr (µs) 0.1 Pre 0 Post Δt<0-0.1 Δw or ΔG mr Pre Post Δt>0 V net =V post -V pre t V net =V post -V pre t Δt Δt (µs) Δt = t post t pre v p v n t v p v n t t pre t post t pre t post Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Accepted. 9

10 CBRAM Synapse Challenges Variability: Device characteristics such as the switching threshold voltages are variable from device to device Switching characteristics depend upon the initial forming step and compliance current Resistive Load: Thousands of devices in parallel present a difficult (low resistance) load to drive by the neuron circuit Resolution: Challenging to realize long-term persistence of weights for more than 1-bit resolution in CBRAM devices 10

11 CMOS Integrate and Fire Neuron V thr V den C mem Spike Generator V leaky M leaky SW 2 SW 1 Ф d =0 A v Ф d =1 1 V mem Ф 1 Ф 2 V refr V rest Ф f =0 1 SW 3 Ф d V axon Ф i Phase Ф f Bus V tch Controller Interface Ф c V cpr V mode V rst Asynchronous integrated and fire operation Accommodates RRAM Provides current summing node Sustain a fixed voltage for synapses Dynamic biasing for large current drive STDP compatible STDP-compatible spike generator In-situ STDP learning Winner-takes-all bus for effective local decision making Single contact point to a synapse WTA Bus V wtab Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3),

12 Novel Tri-mode Operation A Leaky Integrator B Voltage Buffer C Discharging V leaky V refr V rest V leaky V refr V rest V leaky V refr V rest V refr V refr M leaky Фd=1 V refr A v V mem V thr M leaky Фd=1 A v M leaky Фd=1 V refr A v V thr C mem SW 2 SW 1 1 Фd=0 Фf=0 1 SW 3 V axon V thr C mem SW 2 SW 1 Фd=1 0 0 Фf=1 SW 3 V axon V thr C mem SW 2 SW 1 Фd=1 0 Фf=0 1 SW 3 V axon V den V refr A v V mem Vcpr Фd V den V refr A v V mem Vcpr Фd V den V refr A v V mem Vcpr Фd Spike Generator Фi Фf Phase Bus V tch Ф1 Controller Interface V mode Ф2 V rst Фc Spike Generator Фi Фf Phase Bus V tch Ф1 Controller Interface V mode Ф2 V rst Фc Spike Generator Фi Фf Phase Bus V tch Ф1 Controller Interface V mode Ф2 V rst Фc V wtab V wtab V wtab A first CMOS neuron that is compatible with RRAMs and drives a large load Several resistive devices in parallel load the neuron Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3),

13 Simulation: Output Spikes Output Spikes Parameter Symbol Unit Min Max Step Positive amplitude α + mv α + τ + Negative amplitude α - mv Positive pulse width τ + ns Negative pulse width τ - ns Negative pulse slope s mv/ns α - slope τ - Source: X. Wu, V. Saxena and K. Zhu, A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing, International Joint Conference on Neural Networks (IJCNN),

14 Test Chip interfaced with CBRAM Devices A B Pre-spike V pre Post-spike V post V a+ tail + +V t,p Δt Over threshold potential created by STDP spike-pair V a- tail - -V t,m Net potential across synapse V net = V post - V pre Mixed-signal IC with 180-nm CMOS Neurons connected with CBRAM Synapses A first RRAM compatible STDP learning Neuron Power consumed in the neuron is 9.3pJ/spike/synapse (in terms of 10,000 synapses each having around 1MΩ resistance). Source: X. Wu, V. Saxena, K. Zhu and S. Balagopal, A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning, IEEE TCAS-II, 62(11), pp

15 Associative Learning Experiment Pre- Neuron 1 t 1 Pre-spike Neurons Output Layer IFN #1 IFN #2 Pre- Neuron 2 Resistive Synapses t 1 +Δt Post-Neuron IFN #3 Post-spike Input Layer t 2 Pre-Neuron 1(IFN #1) "Sight of Food" Pre-Neuron 2 (IFN #2) "Sound of Bell" Post-Neuron (IFN #3) "Salivation" Time (ms) Source: X. Wu, V. Saxena, K. Zhu and S. Balagopal, A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning, IEEE TCAS-II, 62(11), pp

16 Total Current (ua) Current (µa) Dynamic Resistive Load Driving 97% driving 10,000 x 1MΩ synapses , Synapses Driving Baseline ,000 1, Number of Synapses 10,000 Synapses 1,000 Synapses 100 Synapses 0 56µA 13µA Time (us) Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3),

17 Spike-based Pattern Recognition Circuit... WTA Image i j Input Network i j Input Neuron Matrix i j n Synaptic Network n Output Neurons Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3), 2015, in press. 17

18 Asynchronous WTA Bus Interface V leaky V refr V rest V thr Inhibitory connection Ф Excitatory connection d =1 C mem M leaky SW 2 1 SW 1 Ф d =0 Ф f =0 1 SW 3 V axon V den A v V mem V cpr Ф d Explicit one-one inhibitory connections Inhibitory connection Excitatory connection Spike Generator Implicit inhibition via shared WTA bus WTA Bus Ф i Phase Ф f Bus V tch Controller Interface Ф 1 Ф 2 Ф c V wtab V mode V rst V dd V mode Tri-state Buffer Delay V wtab Φ d Implicit inhibition via shared WTA bus V cpr V tch V rst Φ c D S Q Φ f Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Accepted. 18

19 Neuron # Neuron # Neuron # Demo: Handwrite Digits Classification First 20 Train (original sequence) Test (class-by-class) Input Spike Trains Output Spike Trains without Learning Output Spikes Train with Learning Conductance Evolution in Synapses (µs) Time (µs) Time (µs) Time (µs) Time (µs) 10 0 Source: X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3),

20 Parallel Multibit Synapses Emerging spike-based deep learning architectures require at least 4-bits of synaptic resolution. The devices fundamentally have bistable nonvolatile states with stochastic switching behavior Recent approach: Use several of these device in parallel Potentially multiple resistance states due to variation in individual threshold voltages Input Layer Forward spike Current integration Compound Multibit Synapse Backward spikes Output Neuron 20

21 Multibit Synapses: Dendritic Processing Dendritic processing to include sensitivity to time-overlap between the pre- and post-synaptic spikes Shift in time or pulse voltage in the back-propagating spikes Simulations exhibit remarkable STDP learning behavior; experiments underway with physical devices X. Wu and V. Saxena, Realizing Multibit Synapses with Bistable RRAM Devices, Unpublished result. 21

22 Conclusion Nanoscale emerging memory devices present opportunity for realizing non von Neumann computing Mixed-Signal architectures for spiking neural networks can realize a versatile neuromorphic computing motif Further need to characterize device capabilities and limitations for large scale integration Algorithm/architecture development to be driven ground up by emerging device capabilities 22

23 References 1. X. Wu, V. Saxena and K. Zhu, Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3), 2015, in press. 2. X. Wu, V. Saxena and K. Zhu, A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain- Inspired Computing, International Joint Conference on Neural Networks (IJCNN), 2015, Accepted. 3. X. Wu, V. Saxena and K. A. Campbell, Energy-efficient STDP-based learning circuits with memristor synapses, SPIE Machine Intelligence and Bio-inspired Computation: Theory and Applications VIII, X. Wu, V. Saxena and K. Zhu, A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning, IEEE Transactions on Circuits and Systems II: Express Briefs, In final review. 5. X. Wu and V. Saxena, Associative Learning on CMOS-Memristor Spiking Neuromorphic Chip, IEEE Transactions on Nanotechnology, In 2 nd round review. 23

24 Questions? 24