The N3XT Technology for. Brain-Inspired Computing
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1 The N3XT Technology for Brain-Inspired Computing SystemX Alliance Department of Electrical Engineering
2 Source: Google
3 Source: vrworld.com
4 Source: BDC Stanford Magazine University
5 988 5 Winter Olympic Games in Calgary, Canada
6
7 Source: Gogamguro.com
8 s of kw Source: Google
9 Small to moderate scale Large scale Scale Up Requires Energy Efficiency Application Emulating 4.5% of human brain: 3 synapses, 9 neurons Deep sparse autoencoder: 9 synapses, M images Hardware used Blue Gene/P: 36,864 nodes, 47,456 cores, CPUs (6, cores) Estimated power consumption 2.9 MW (LINPACK) ~ kw (cores only) Convolutional neural net with 6M synapses, 65K neurons 2 GPUs,2 W Restricted Boltzmann Machine: 28M synapses; 69,888 neurons Processing s of speech using deep neural network GPU CPU GPU CPU (4 cores) 55 W 65 W 238 W 8 W 9 S. B. Eryilmaz et al., IEDM
10 These nanotechnology innovations will have to be developed in close coordination with new computer architectures, and will likely be informed by our growing understanding of the brain a remarkable, faulttolerant system that consumes less power than an incandescent light bulb
11 Approaches of Neuromorphic Hardware
12 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware
13 Approaches of Neuromorphic Hardware Neuromorphic hardware Conventional hardware (CPU, GPU, supercomputers, etc)
14 Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc)
15 Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) Brain emulation on BlueGene [7] HTM [3]
16 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) Brain emulation on BlueGene [7] HTM [3] Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
17 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) TrueNorth [6] SpiNNaker [9] Human Brain Project [2] Brain emulation on BlueGene [7] HTM [3] Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
18 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) TrueNorth [6] SpiNNaker [9] Hebbian learning Spike-based ANN Brain emulation on BlueGene [7] Human Brain Project [2] PCM, RRAM, CBRAM HTM [3] Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
19 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) TrueNorth [6] SpiNNaker [9] Hebbian learning Spike-based ANN Brain emulation on BlueGene [7] Human Brain Project [2] PCM, RRAM, CBRAM HTM [3] ANN, RBM, sparse learning PCM, RRAM Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
20 Many of these breakthroughs will require new kinds of nanoscale devices and materials integrated into three-dimensional systems and may take a decade or more to achieve
21 N3XT Nanosystems Computation immersed in memory Memory Ultra-dense vertical connections Computing logic
22 N3XT Nanosystems Computation immersed in memory Memory Ultra-dense vertical connections Computing logic Impossible with today s technologies
23 N3XT: Computation Immersed in Memory 3D Resistive RAM Massive storage D CNFET, 2D FET Compute, RAM access MRAM Quick access D CNFET, 2D FET Compute, RAM access D CNFET, 2D FET Compute, Power, Clock thermal thermal thermal Not TSV Ultra-dense, fine-grained vias Silicon compatible
24 Aly et al., IEEE Computer,
25 Non-Volatile Memory (NVM) Top Electrode phase change material oxide isolation switching region Bottom Electrode metal oxide Top Electrode oxygen ion filament oxygen vacancy Bottom Electrode Active Top Electrode solid electrolyte filament metal atoms Bottom Electrode partially reset state fully reset state TiN TiN TiN 25nm poly c-gst T amorphous TiN SiO 2 poly c-gst amorphous 2 nm O 2 TiN SiO 2 TiN SiO 2 TiOx/ HfOx nm Cu ion Electrolyte Bottom electrode Phase change memory (PCM) Metal oxide resistive switching memory (RRAM) Conductive bridge memory (CBRAM) 26 D. Kuzum et al., Nano Lett. 23, Y. Wu et al., IEDM 23; A. Calderoni et al., IMW
26 Non-Volatile Memory (NVM) Synapse Analog programmable Scalable to a few nm Stack in 3D partially reset state fully reset state TiN TiN TiN 25nm poly c-gst T amorphous TiN SiO 2 poly c-gst amorphous 2 nm O 2 TiN SiO 2 TiN SiO 2 TiOx/ HfOx nm Cu ion Electrolyte Bottom electrode Phase change memory (PCM) Metal oxide resistive switching memory (RRAM) Conductive bridge memory (CBRAM) 27 D. Kuzum et al., Nano Lett. 23, Y. Wu et al., IEDM 23; A. Calderoni et al., IMW
27 Resistance (Ohm) Resistance (Ohm) Nanoscale Memory as Synaptic Weights Synaptic updates in the brain: basis for learning Requirement: analog resistance change -step grey scale (% resolution) Pulse Number 4 3 Partial RESET Pulse Number Partial SET Phase change synapse D. Kuzum et al., Nano Lett., p. 279 (22)
28 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
29 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
30 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
31 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
32 Hyper Dimensional (HD) Computing Elements of Hyper dimensional Computing: Also known as vector symbolic architectures or holographic reduced representation (Kanerva, Cognitive Computation, (2):39-59,29) Information is represented by High-dimensional representation (e.g., D =,) Variables and values are combined into a holistic record using vector algebra: Multiplication for Binding Addition for Bundling Composed vector can in turn become a component in further composition Holistic record is decoded with (inverse) multiplication Approximate results of vector operations are identified with exact ones using content-addressable memory 33 ENIGMA
33 HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
34 Algorithms HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
35 System and Circuit Design Algorithms HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
36 Associative memory enabled by novel device technologies System and Circuit Design Algorithms HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
37 Hyperdimensional (HD) Computing Monolithic 3D enables Energy-efficient classification Area efficient HD projection use RRAM variability & stochastic switching 3D RRAM + low power access transistors + address decoders High-density Inter-layer vias Low power computation
38 3D Enables In-Memory Computing 3D RRAM with FinFET BL select TiN/Ti (5 nm) TiN/Ti Layer 4 (L4) Layer 3 (L3) Layer 2 (L2) Layer (L) (TE) TiN TiN TiN TiN (BE) TiN (2 nm) 5 nm H. Li et al., Symp. VLSI Tech.,
39 Current ( A) Resistance ( ) Resistance ( ) B B B B MAP Kernels: 3D RRAM Approach Key HD operations: multiplication, addition, permutation k D C k B 4 XOR {, } system M k k M A equiv. Multiplication {-, } system C = Multiplication Input AB = pillar addr. = D C B A D = D = Input AB = pillar addr. = C = k M G T Logic Evaluation Cycle (#) Addition Symbol: -pillar exp. 2 Input AB = pillar addr. = D = Logic Evaluation Cycle (#) D C B A D = Input AB = pillar addr. = D C B A C = C = k M G T k k M G G Measured data on 4-layer 3D vertical RRAM Line: 2-pillar emulated Addition Cycle (#) L44 L33 L22 L L4 L3 L2 L Permutation gnd V DD V DD gnd B E+5 (a) gnd V B DD 2 ns (b) 2 ns V DD gnd Measured LRS (~kω) 5.3E E E+5.E+6 gnd V DD V DD gnd Measured HRS (4kΩ-MΩ).E+6.E E E E E+ 5.3E+5.3E+ 4.E+5 4.E+.E+6.E E E E E+5 5.3E+5 5.3E+5 4.E+5 4.E+5
40 3D Integration of Memory and Logic Circuits within the Same Layer & Across Layers Synapses/Weights (3D RRAM) Logic (Si CMOS) Neuron circuits Communication Synapses/Weights (CNFET/2D FET) + RRAM
41 Nano-Engineered Computing Systems Technology Aly et al., IEEE Computer,
42 Students and Post-Docs
43 Collaborators Gert Cauwenberghs Siddharth Joshi Emre Neftci (UC San Diego) Jinfeng Kang (Peking U) Chung Lam SangBum Kim Matt Brightsky K.S. Lee, J.M. Shieh, W.K. Yen (NDL, Taiwan)
44 Sponsors E2CDA Engima Non-Volatile Memory Technology Research Initiative
45 Stanford SystemX Alliance
46 Non-Volatile Memory Technology Research Initiative
47 End of Talk Questions? fully set state partially reset state fully reset state TiN TiN TiN poly c-gst poly c-gst poly c-gst amorphous amorphous SiO 2 SiO 2 SiO 2 TiN TiN TiN
48 Open Research Questions. Functionality performance/watt, performance/m 2 variability reliability 2. Scale up (system size), scale down (device size) 3. Role of variability (functionality, performance) 4. Fan-in / fan-out, hierarchical connections, power delivery 5. Low voltage (wire energy device energy) 6. Stochastic learning behavior statistical learning rules 7. Meta-plasticity (internal state variables) 8. Timing as an internal variable 9. Learning rules: biological? AI?. Algorithm-device co-design. Materials/fabrication: monolithic 3D integration a must, MUST be low temperature
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