LEADING THE EVOLUTION OF COMPUTE MARK KACHMAREK HPC STRATEGIC PLANNING MANAGER APRIL 17, 2018

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Bartholomew Wright
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1 LEADING THE EVOLUTION OF COMPUTE MARK KACHMAREK HPC STRATEGIC PLANNING MANAGER APRIL 17, 2018

2 INTEL S RESEARCH EFFORTS COMPONENTS RESEARCH INTEL LABS ENABLING MOORE S LAW DEVELOPING NOVEL INTEGRATION ENABLING FUTURE PRODUCT CAPABILITIES ANTICIPATING FUTURE INTEL UNIVERSITY RESEARCH Expanding the Frontier, Future Intel Collaborators 2

3 The number of transistors and resistors on a chip doubles every 24 months -Gordon Moore 3 3

4 10 >50 Years of Scaling Micron nm

5 Technology Innovation M0 SD G SD Strained High-k Self FinFET Hyper Hyper Silicon Metal Gate Align Via Transistor Scaling Scaling 90 nm 45 nm 32 nm 22 nm 14 nm 10 nm Generation Innovations in IC Materials & Structures Continue Scaling 5

6 Scaled 10 nm Features nm Fin Pitch 54 nm Gate Pitch 40 nm M0 Pitch 36 nm M1 Pitch 44 nm M2 Pitch Aggressive Pitch Scaling Improves Density 6

7 Logic Transistor Density Trend nm 14 nm 2.7x Transistor Density (MTr / mm 2 ) nm 22 nm 2.1x 2.5x 45 nm 2.3x HVM Wafer Start Date Hyper Scaling Unprecedented x Transistor Density 7

8 Logic Transistor Density Trend nm nm Transistor Density (MTr / mm 2 ) nm nm 45 nm HVM Wafer Start Date Transistor Density Continues ~Doubling Every 2 Years 8

9 Microprocessor Die Area Scaling 100 mm x 62 mm x Area 38.4 mm x 0.43x IO Logic IO Logic IO Logic 17.7 mm mm 2 IO Logic SRAM 100 SRAM mm SRAM mm SRAM mm 2 IO Logic 100 SRAM mm 2 45 nm 32 nm 22 nm 14 nm 10 nm Hyper Scaling x die area scaling on 14nm & 10nm 9

10 Heterogeneous System Integration Discrete ICs 2-D Integration (SoC) High Density Memory High Speed Memory Low Power Logic Power Regulator Sensors High Perf. Logic Radio Photonics 3-D Integration (SiP) Logic Memory Power Reg. Radio Sensors Photonics 10

11 Beyond CMOS Devices - Spintronic SpinFET Spin Torque Majority Gate (SMG) Spin Torque Domain Wall (STT/DW) All Spin Logic (ASL) Spin Wave Device (SWD) Nanomagnetic Logic (NML) 11

13 Modes of Event-Driven Learning Unsupervised Learning Pattern Detection Self-supervised Learning Pattern Association Supervised Learning Pattern Recognition CARS PLANES CATS Reinforcement Learning Decision Making 13

Loihi: a Groundbreaking Research Test Chip Neuromorphic Core Complex & unique feature set Most advanced features of all published chips to date 128 cores + three Lakemont cores

14 Loihi: a Groundbreaking Research Test Chip Neuromorphic Core Complex & unique feature set Most advanced features of all published chips to date 128 cores + three Lakemont cores Programmable learning rules Scalable neuromorphic fabric Novel design methodology Architecture-to-silicon modeling Asynchronous design flow Validation of POC algorithms with FPGA-based emulation 14

learning rules Scalable neuromorphic fabric Novel design methodology

15 Loihi: a Groundbreaking Research Test Chip Complex & unique feature set Most advanced features of all published chips to date 128 cores + three Lakemont cores Programmable learning rules Scalable neuromorphic fabric Novel design methodology Architecture-to-silicon modeling Asynchronous design flow Validation of POC algorithms with FPGA-based emulation 15

16 QUANTUM COMPUTING The massive parallelism enables algorithms to tackle problems intractable for classical computers

(all possible) inputs (filtered) results one result Applications Space: HPC ~50+ Qubits: Proof of concept Transform & Filter Measure Computational power exceeds supercomputers Learning test bed for

17 (all possible) inputs (filtered) results one result Applications Space: HPC ~50+ Qubits: Proof of concept Transform & Filter Measure Computational power exceeds supercomputers Learning test bed for quantum system ~1000+ Qubits: Small problems Limited error correction Chemistry, materials design Optimization ~1M+ Qubits: Commercial scale Fault tolerant operation Cryptography Machine Learning 17

(all possible) inputs (filtered) results one result Applications Space: HPC Transform & Filter A Quantum Computer Application Software Architecture Hardware Architecture Qubit devices Measure ~50+

18 (all possible) inputs (filtered) results one result Applications Space: HPC Transform & Filter A Quantum Computer Application Software Architecture Hardware Architecture Qubit devices Measure ~50+ Qubits: Proof of concept Computational power exceeds supercomputers Learning test bed for quantum system ~1000+ Qubits: Small problems Limited error correction Chemistry, materials design Optimization ~1M+ Qubits: Commercial scale Fault tolerant operation Cryptography Machine Learning 18

19 Larger Superconducting Qubit Chips Silicon Qubits From 300mm Wafers More Integrated Quantum System 17 Qubits Material Science, Quantum Machine Learning algorithms 49 Qubits Qubit Wafer In Process Control System Performance Simulation Cryogenic RF control IC 19

20 The future is bright 20

22 Legal Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer. Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Intel Corporation 22

Intel s approach to Quantum Computing

Intel s approach to Quantum Computing Dr. Astrid Elbe, Managing Director Intel Lab Europe Quantum Computing: Key Concepts Superposition Classical Physics Quantum Physics v Heads or Tails Heads and Tails