Efficient electron transport on helium with silicon integrated circuits

Transcription

1 Efficient electron transport on helium with silicon integrated circuits Forrest Bradbury 1 and Maika Takita 1, Kevin Eng 2, Tom M Gurrieri 2, Kathy J Wilkel 2, Stephen A Lyon 1 1 Princeton University 2 Sandia National Laboratories

2 Electron spins on helium are low density, but independent, flexible, and mobile: the Quantum Information American Dream

3 Electron spins on helium are low density, but independent, flexible, and mobile: Stationary qubits necessitate continual SWAP operations on neighboring qubits for information propagation Mobile qubits obviate this extra requirement Mobile electron spins in silicon are so far the best, but their coherence is limited by the Rashba interaction to T 2 = 3 µs Electron spins on helium expected T 2 > 100 seconds

4 Transport enabled computation Memory registers... Interaction Post Dot Single charge detection

5 twiddle sense door 3um He 2um Twiddle Sensing SiO 2 3um ~ ~ 3 twiddle sense door Plate Plate HEMT Preamp at 1.5 K

6 twiddle sense door 3um He 2um Twiddle Sensing SiO 2 3um ~ ~ 3 twiddle sense door Plate Plate HEMT Preamp at 1.5 K

7 twiddle sense door 3um He 2um Twiddle Sensing SiO 2 3um ~ ~ 3 twiddle sense door Plate Plate HEMT Preamp at 1.5 K

8 Twiddle Sensor: Potential Simulations Top metal plane held at -3V Twiddling right: Φ3 Twiddle Sense Door Plate1-400mV -80mV 0mV -320mV -400mV Twiddling left: Φ3 Twiddle Sense Door Plate1-400mV +80mV 0mV -480mV -400mV Electrical potential in volts at the helium surface above the channels

9 Calibration Twiddle Sensing Results Voltage signal is converted to number of electrons per channel via gain calibration of the amplification circuit and capacitance estimate of the sense line + HEMT input. This predicts the observed signal saturation where detector is no longer linear. Linearity

10 Calibration Twiddle Sensing Results Voltage signal is converted to number of electrons per channel via gain calibration of the amplification circuit and capacitance estimate of the sense line + HEMT input. This predicts the observed signal saturation where detector is no longer linear. Linearity Twiddle Sensing Sensitivity Noise in silicon samples ~ 360 electrons per Hz ½ with 120 parallel channels ~ 3 electrons per channel per Hz ½

11 Twiddle Sensing Results Twiddle Sensing Sensitivity Noise in silicon samples Electrons per Channel Quantization Measurements ~ 360 electrons per Hz ½ with 120 parallel channels ~ 3 electrons per channel per Hz ½ Electron turnstile for confinement Lower temperature

12 Twiddle Sensing with On-chip Amplification Better sensing by proximity: With HEMT preamp, ~2 pf With on-chip FET, ~0.02 pf Induced voltage is 100x 13.5 µm

13 Multi-Project Wafer from Sandia CMOS7 Process

14 Potential Energy 3-phase CCD Potential Underlying gates Helium electron - +

15 Device structure 120 horizontal channels Measurement gates for electron detection Right and Left Memory Cell Gates Vccd2 Vccd3 twiddle sense door

16 Horizontal CCD Loading: Photoemit electrons on plates Load them to pixels by opening the door plate Clocking Sequence 10 pixel to the left 10 pixel back to the right door sense twiddle

17 # of electrons per channel Horizontal Clocking Efficiency Clock (pixel) rate = 240kHz pixels transferred No measurable loss after 10 9 cycles!

18 Vertical channel CCD Vertical Clocking Efficiency Cornering Efficiency Distribution of electrons in horizontal channels

19 Vertical channel CCD

20 Vertical channel CCD

21 Vertical channel CCD

22 Vertical channel CCD Distribution of electrons in horizontal channels

23 Vertical channel CCD Channel N+60 each packet of electrons travels up and down 60 channels C-cycling Demonstrates vertical channel CCD cornering efficiency 2D control Channel N

24 # of electrons per channel Vertical CCD Cornering 2D control Vertical channel CCD Channel 61 pixels transferred One packet of electrons travels between Channel occupancy after C-Cycle Channel 1 # of channels moved

25 Conclusion Electron detection with twiddle gate Unprecedented reliability of a Charge Coupled Device -Essentially a perfect Electron Transfer Efficiency 5 clock lines for full control -2D Scalability: Move anywhere in our ~5000 position gate & channel array Si-Processing -First, non-optimized design with standard silicon processing -Possibilities for on-chip amplification