Jim Held, Ph.D., Intel Fellow & Director Emerging Technology Research, Intel Labs. HPC User Forum April 18, 2018

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1 Jim Held, Ph.D., Intel Fellow & Director Emerging Technology Research, Intel Labs HPC User Forum April 18, 2018

Quantum Computing: Key Concepts Superposition

Heads or Tails Heads and Tails 2) 4) N Quantum Bits or

than any possible supercomputer 300 Entangled Qubits =

require error correction and likely millions of qubits

2 Quantum Computing: Key Concepts Superposition Classical Physics Quantum Physics v Entanglement 1) 3) Heads or Tails Heads and Tails 2) 4) N Quantum Bits or Qubits = 2 N States 50 Entangled Qubits = more states than any possible supercomputer 300 Entangled Qubits = more states than atoms in the universe Fragility will require error correction and likely millions of qubits Fragility v Observation or noise causes loss of information 2

3 (all possible) inputs (filtered) results one result The promise of quantum computing Transform & Filter Measure Exponential speedup surpassing the limits of scaling 3

4 Changing the World Quantum Will Change Everything Travel and Logistics Image Processing Pharmacology Improved Forecasting Improved Stock ROI Cryptography Source: Google Images 4

5 5 Application Algorithms Compilers/Runtimes Control Electronics Challenges to be addresses at each level Quantum Chip

6 Intel Labs: Algorithms System Architecture Control Electronics Intel QuTech Research Collaboration TMG Components Research Patterning Atomic Layer Control Packaging 24nm Pitch Lines Metal Gate / High k on 300mm Silicon Wafer Assembly and Packaging Research QuTech s Expertise in qubit operation and control Combining Intel capabilities with Delft expertise 6

7 7 Application Algorithms Compilers/Runtimes Control Electronics Quantum Chip Qubit Device Design & Fabrication Assembly & Packaging Topology & Connectivity

8 Building Better Qubits Superconducting Qubits Spin Qubits in Silicon Very high quality microwave circuit Single electron transistors, where qubit is spin state 8

9 Superconducting Qubit Progress Resonator 6 Qubits 7 Qubit Array 17 Qubit Array Tangle Lake Starmon Geometry with up to 30us T1 Shared Feedlines Surface Code Topology 9

10 Flip-chip die evolution Octobox 6-port FC Surf-7 FC Surf-17 FC Surf-49 FC 2mm x 7mm 8mm x 8mm 14mm x 14mm wire bonding around perimeter Flip-chip bonding 22mm x 22mm TSVs needed 36mm x 36mm 10

11 Spin Qubits In Silicon Gate Ox SiGe spacer Si QW Stepped buffer Characterizing LAB devices First 300mm isotopically pure silicon and world class mobility QD array devices almost ready with FAB quality Si 11

Spin Qubits at higher temperatures Hot-Qubits To increase cooling power available for larger arrays Relaxation time T 1 Charge Noise Spin Relaxation Short coherence

12 Spin Qubits at higher temperatures Hot-Qubits To increase cooling power available for larger arrays Relaxation time T 1 Charge Noise Spin Relaxation Short coherence times affects gate operations T 1 1.1K; longer at lower B / higher Evs Charge Noise Single qubit gates & two-qubit gates are affected Linear increase 1 4K 12

13 13 Application Algorithms Compilers/Runtimes Control Electronics Quantum Chip Digital/Analog Control Error Correction I/O to Qubit plane

14 Scaling I/O to the Qubit Plane Processor 10 9 transistors 10 3 pins 3D NAND Memory bytes 10 2 pins 49-Qubit Transmon Array 49 qubits 108 pins 14

Requires several attenuators, filters, etc, for each line N (# qubits) qubit board/ package qubit chip 4K 20mK N control

15 Solution Cryogenic Control Main Controller (firmware/software) Control Electronics High-speed digital interface Main Controller (firmware/software) High-speed digital interface (~ 10 lines or log 2 (N) worst case) FRIDGE 300K FRIDGE 300K Requires several attenuators, filters, etc, for each line N (# qubits) qubit board/ package qubit chip 4K 20mK N control chip board/ package qubit board/ package control chip qubit chip 4K Custom designed control chip optimized for low T 20mK 15 15

16 16 Application Algorithms Compilers/Runtimes Control Electronics Optimization Mapping & Scheduling Fault tolerant operations Quantum Chip

17 QuBit Simulation Universal: single and two-qubit controlled gates High Perf QuBit Simulation Open Source Release External Collaboration: Alan Aspuru-Guzik (Harvard), Matthias Troyer (ETH Zürich) 17 17

18 Gate scheduling for quantum algorithms Mapping and scheduling under constraints: Logical dependency Exclusive activation Physical connectivity Scheduling Quantum Approximate Optimization Algorithm for hardware with linear connectivity: three strategies of increasing sophistication 18

19 19 Application Algorithms Compilers/Runtimes Compelling Applications Resilient Algorithms Real Workloads for Early Systems Control Electronics Quantum Chip

quantum system ~1000+ Qubits: Small problems Limited error correction Chemistry, materials design

20 Applications Space: HPC Quantum co-processor: augmenting, not replacing, traditional HPC systems ~50+ Qubits: Proof of concept Computational power exceeds supercomputers Learning test bed for quantum system ~1000+ Qubits: Small problems Limited error correction Chemistry, materials design Optimization ~1M+ Qubits: Commercial scale Fault tolerant operation Cryptography Machine Learning 20

21 Entanglement Gap Materials Science Quantifying entanglement provides a measurement of correlations between electrons which is useful for understanding the electronic properties of the material. Algorithm to measure entanglement: R n = Ψ n Perm A Ψ n For example, in determining whether simulated material is a metal or an insulator. Insulating quantum Hall state Conductor Collaboration: Damian Steiger, Matthias Troyer (ETH Zurich), Chris Monroe (U of MD) Short-range Interaction Strength 21

22 Performance Feedback loop Resilient Algorithms QPU CPU Hybrid quantum-classical Quantum state preparation Quantum measurement 1 Quantum measurement 2 <O 1 > <O 2 > Quantum Chemistry and Noise study: Comparing two variants of the VQE algorithm to approximate lowest energy of molecules Surprisingly, version requiring more quantum operations is more resilient to noise Collaboration: Alan Aspuru-Guzik, Harvard, Jarrod McClean, LBL 22 22

23 Machine Learning Classical Neuron Quantum Neuron Repeat Until Success circuit Non-linear Transfer Function Collaboration: Yudong Cao and Alán Aspuru-Guzik, Harvard University 23

24 24 Application Algorithms Compilers/Runtimes Control Electronics System Metrics Trade-offs & Constraints Co-design for scaling Quantum Chip

25 Moving to System Level Metrics Device-level metrics Physical qubit count Decoherence time T 1, T 2 System-level metrics Gate operation time Fidelity Logical qubit count Effective parallelization Utilization HW-SW co-design requires system metrics that impact real application performance 25

26 Conclusions The potential of quantum computing is generating tremendous excitement We re leveraging Intel s expertise in process and architecture to move faster A commercial system is ~10 Years Away 26

27 Legal Information This presentation contains the general insights and opinions of Intel Corporation ( Intel ). The information in this presentation is provided for information only and is not to be relied upon for any other purpose than educational. Statements in this document that refer to Intel s plans and expectations for the quarter, the year, and the future, are forward-looking statements that involve a number of risks and uncertainties. A detailed discussion of the factors that could affect Intel s results and plans is included in Intel s SEC filings, including the annual report on Form 10-K. Any forecasts of goods and services needed for Intel s operations are provided for discussion purposes only. Intel will have no liability to make any purchase in connection with forecasts published in this document. Intel accepts no duty to update this presentation based on more current information. Intel is not liable for any damages, direct or indirect, consequential or otherwise, that may arise, directly or indirectly, from the use or misuse of the information in this presentation. Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. Copyright 2018 Intel Corporation. Intel, the Intel logo, Xeon. Movidius and Stratix are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others

Intel s approach to Quantum Computing

Intel s approach to Quantum Computing Dr. Astrid Elbe, Managing Director Intel Lab Europe Quantum Computing: Key Concepts Superposition Classical Physics Quantum Physics v Heads or Tails Heads and Tails