TLD2326. Internal supply. Thermal protection IN_SET3 IN_SET2 IN_SET1. Current adjustment TLD2326EL CFB

Transcription

1 3 Channel High-Side Curren Source Package Marking PG-SSOP-14 TLD Overview Applicaions Exerior LED lighing applicaions such as ail/brake ligh, urn indicaor, posiion ligh, side marker,... Inerior LED lighing applicaions such as ambien lighing (e.g. RGB), inerior illuminaion and dash board lighing. VBATT GND DC/DC Converer DC/DC conroller 10kΩ CVS=4.7nF EN IN_SET3 VS Inernal supply Thermal proecion Oupu conrol OUT3 OUT2 IN_SET2 IN_SET1 Curren adjusmen OUT1 CFB RFB RSET3 RSET2 RSET1 DC/DC conrol FB GND Applicaion Diagram wih Daa Shee Rev

2 Overview Basic Feaures 3 Channel device wih inegraed oupu sages (curren sources), opimized o drive LEDs wih oupu curren up o 120 ma per channel Low curren consumpion in sleep mode PWM-operaion suppored via VS- and EN-pin Oupu curren adjusable via exernal low power resisor and possibiliy o connec PTC resisor for LED proecion during over emperaure condiions Dynamic overhead conrol Reverse polariy proecion and overload proecion Undervolage deecion Open load and shor circui o GND diagnosis Wide emperaure range: -40 C < T j < 150 C PG-SSOP-14 package wih exposed heaslug Descripion The LITIX Basic is a hree channel high side driver IC wih inegraed oupu sages. I is designed o conrol LEDs wih a curren up o 120 ma. In ypical auomoive applicaions he device is capable o drive i.e. 3 red LEDs per chain (oal 9 LEDs) wih a curren up o 60 ma, which is limied by hermal cooling aspecs. The oupu curren is conrolled pracically independen of load and supply volage changes. Table 1 Produc Summary Parameer Symbol Value Operaing volage range V S(nom) 5.5 V V Maximum volage V S(max) 40 V V OUTx(max) Nominal oupu (load) curren I OUTx(nom) 60 ma when using a supply volage range of 8 V - 18 V (e.g. Auomoive car baery). Currens up o I OUT(max) possible in applicaions wih low hermal resisance R hja Maximum oupu (load) curren I OUTx(max) 120 ma; depending on hermal resisance R hja Oupu curren accuracy a R SETx = 12 kω k LT 750 ± 7% Curren consumpion in sleep mode I S(sleep,yp) 0.1 µa Proecive Funcions ESD proecion Under volage lock ou Over Load proecion Over Temperaure proecion Reverse Polariy proecion Diagnosic Funcions OL deecion SC o Vs (indicaed by OL diagnosis) SC o GND deecion Daa Shee 2 Rev. 1.2

3 Block Diagram 2 Block Diagram VS EN IN_SET3 Inernal supply Thermal proecion Oupu conrol OUT3 OUT2 IN_SET2 IN_SET1 Curren adjusmen OUT1 DC/DC conrol FB GND Figure 1 Basic Block Diagram Daa Shee 3 Rev. 1.2

4 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen VS 1 14 NC VS 2 13 OUT3 EN 3 12 OUT2 NC 4 EP 11 OUT1 IN_SET FB IN_SET2 6 9 GND IN_SET1 7 8 NC Figure 2 Pin Configuraion Daa Shee 4 Rev. 1.2

5 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol Inpu/ Funcion Oupu 1, 2 VS Supply Volage; baery supply, connec a decoupling capacior (100 nf - 1 µf) o GND 3 EN I Enable pin 4 NC Pin no conneced 5 IN_SET3 I/O Inpu / SET pin 3; Connec a low power resisor o adjus he oupu curren 6 IN_SET2 I/O Inpu / SET pin 2; Connec a low power resisor o adjus he oupu curren 7 IN_SET1 I/O Inpu / SET pin 1; Connec a low power resisor o adjus he oupu curren 8 NC Pin no conneced 9 GND Ground 10 FB O Feedback Oupu 11 OUT1 O Oupu 1 12 OUT2 O Oupu 2 13 OUT3 O Oupu 3 14 NC Pin no conneced Exposed Pad GND Exposed Pad; connec o GND in applicaion Connec all GND-pins ogeher. Daa Shee 5 Rev. 1.2

6 General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Absolue Maximum Raings T j = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. Volages Supply volage V S V Inpu volage EN V EN V Inpu volage EN relaed o V S V EN(VS) V S - 40 V S + 16 V Inpu volage EN relaed o V OUTx V EN V V EN - V OUTx V OUTx Oupu volage V OUTx V Power sage volage V PS V V PS = V S - V OUTx IN_SETx volage V IN_SETx V Feedback volage V FB V Currens IN_SETx curren I IN_SETx No subjec o producion es, specified by design 2) ESD suscepibiliy, Human Body Model HBM according o ANSI/ESDA/JEDEC JS ) ESD suscepibiliy, Charged Device Model CDM according o JESD22-C101E Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 2 3 ma Diagnosis oupu Feedback curren I FB 0.5 ma Oupu curren I OUTx 130 ma Temperaures Juncion emperaure T j C Sorage emperaure T sg C ESD Suscepibiliy ESD resisiviy o GND V ESD -2 2 kv Human Body Model (100 pf via 1.5 kω) 2) ESD resisiviy all pins o GND V ESD V CDM 3) ESD resisiviy corner pins o GND V ESD V CDM 3) Daa Shee 6 Rev. 1.2

7 General Produc Characerisics 4.2 Funcional Range Pos. Parameer Symbol Limi Values Uni Condiions Min. Max Supply volage range for V S(nom) V normal operaion Power on rese hreshold V S(POR) 5 V V EN = V S R SETx =12kΩ I OUTx = 80% I OUTx(nom) V OUTx =2.5V Juncion emperaure T j C Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 4.3 Thermal Resisance Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Juncion o Case R hjc 8 10 K/W 2) Juncion o Ambien 1s0p board R hja Juncion o Ambien 2s2p board R hja2 No subjec o producion es, specified by design. Based on simulaion resuls. 2) Specified R hjc value is simulaed a naural convecion on a cold plae seup (all pins and he exposed Pad are fixed o ambien emperaure). T a = 85 C, Toal power dissipaion 1.5 W. 3) The R hja values are according o Jedec JESD51-3 a naural convecion on 1s0p FR4 board. The produc (chip + package) was simulaed on a 76.2 x x 1.5 mm 3 board wih 70 µm Cu, 300 mm 2 cooling area. Toal power dissipaion 1.5 W disribued saically and homogenously over all power sages. 4) The R hja values are according o Jedec JESD51-5,-7 a naural convecion on 2s2p FR4 board. The produc (chip + package) was simulaed on a 76.2 x x 1.5 mm 3 board wih 2 inner copper layers (ouside 2 x 70 µm Cu, inner 2 x 35 µm Cu). Where applicable, a hermal via array under he exposed pad conaced he firs inner copper layer. Toal power dissipaion 1.5 W disribued saically and homogenously over all power sages K/W 3) K/W T a =85 C T a = 135 C 4) T a =85 C T a = 135 C Daa Shee 7 Rev. 1.2

8 EN Pin 5 EN Pin The EN pin is a dual funcion pin: Inernal Supply EN Oupu Conrol V EN Figure 3 Block Diagram EN pin Noe: The curren consumpion a he EN-pin I EN needs o be added o he oal device curren consumpion. The oal curren consumpion is he sum of he currens a he VS-pin I S and he EN-pin I EN. 5.1 EN Funcion If he volage a he pin EN is below a hreshold of V EN(off) he LITIX Basic IC will ener Sleep mode. In his sae all inernal funcions are swiched off, he curren consumpion is reduced o I S(sleep). A volage above V EN(on) a his pin enables he device afer he Power on rese ime POR. V S V EN I OUT POR 100% 80% Figure 4 Power on rese Daa Shee 8 Rev. 1.2

9 EN Pin 5.2 Inernal Supply Pin The EN pin can be used o supply he inernal logic. There are wo ypical applicaion condiions, where his feaure can be used: In DC/DC conrol Buck configuraions, where he volage V s can be below 5.5V. 2) In configuraions, where a PWM signal is applied a he Vba pin of a ligh module. The buffer capacior C BUF is used o supply he LITIX Basic IC during Vba low (V s low) periods. This feaure can be used o minimize he urn-on ime o he values specified in Pos Oherwise, he power-on rese delay ime POR (Pos ) has o be considered. The capacior can be calculaed using he following formula: C BUF = I EN LS LOW max V S V D V SPOR See also a ypical applicaion drawing in Chaper 10. ( V BATT GND CBUF D1 EN IN_SET3 VS Inernal supply Thermal proecion Oupu conrol OUT3 OUT2 IN_SET2 IN_SET1 Curren adjusmen OUT1 RSET3 RSET2 RSET1 LI TIX Basic GND Figure 5 Exernal circui when applying a fas PWM signal on V BATT Daa Shee 9 Rev. 1.2

10 EN Pin V EN V BATT IOUT ON(VS) 100% 80% Swich off behavior depends on V BATT and load characerisics 20% Figure 6 Typical waveforms when applying a fas PWM signal on V BATT The parameer ON(VS) is defined a Pos The parameer OFF(VS) depends on he load and supply volage V BATT characerisics. 5.3 EN Unused In case of an unused EN pin, here are wo differen ways o connec i: EN - Pull Up o VS The EN pin can be conneced wih a pull up resisor (e.g. 10 kω) o V s poenial. In his configuraion he LITIX Basic IC is always enabled EN - Direc Connecion o VS The EN pin can be conneced direcly o he VS pin (IC always enabled). This configuraion has he advanage (compared o he configuraion described in Chaper 5.3. ha no addiional exernal componen is required. Daa Shee 10 Rev. 1.2

11 EN Pin 5.4 Elecrical Characerisics Inernal Supply / EN Pin Elecrical Characerisics Inernal Supply / EN pin Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SETx =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Curren consumpion, sleep mode Curren consumpion, acive mode Curren consumpion, device disabled via IN_SETx Curren consumpion, acive mode in single faul deecion condiion Curren consumpion, acive mode in double faul deecion condiion and one oupu disabled via IN_SETx I S(sleep) µa V EN = 0.5 V T j < 85 C V S = 18 V V OUTx = 3.6 V I S(on) I S(dis,IN_SET) I S(faul) I S(dfaul) ma ma ma ma 2) I IN_SET = 0µA T j < 105 C V S = 18 V V OUTx = 3.6V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C V IN_SETx = 5 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C R SET1 = 12 kω R SET2,3 = unconneced V OUTx = 18 V or 0 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C R SET1,2 = 12 kω R SET3 = unconneced V OUTx = 18 V or 0 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin Daa Shee 11 Rev. 1.2

12 EN Pin Elecrical Characerisics Inernal Supply / EN pin (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SETx =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Power-on rese delay ime 3) Required supply volage for oupu acivaion Required supply volage for curren conrol POR 25 µs V S = V EN = V V OUTx(nom) = 3.6 ± 0.3V I OUTx = 80% I OUTx(nom) V S(on) 4 V V EN = 5.5 V V OUTx = 3 V I OUTx = 50% I OUTx(nom) V S(CC) 5.2 V V EN = 5.5 V V OUTx = 3.6 V I OUTx 90% I OUTx(nom) EN urn on hreshold V EN(on) 2.5 V EN urn off hreshold V EN(off) 0.8 V EN inpu curren during low supply volage EN high inpu curren I EN(H) I EN(LS) 2.4 ma V S = 4.5 V T j < 105 C V EN = 5.5 V ma T j < 105 C V S = 13.5 V, V EN = 5.5 V V S = 18 V, V EN = 5.5 V V S = V EN = 18 V V S = 18 V, R EN = 10 kω beween VS and EN-pin No subjec o producion es, specified by design 2) The oal device curren consumpion is he sum of he currens I S and I EN(H), please refer o Pos ) See also Figure 4 Daa Shee 12 Rev. 1.2

13 FB Pin 6 FB Pin The following block diagram shows he feedback pin funcionaliy. OUT1 OUT2 OUT3 Oupu volage feedback I FB(SOC) FB Figure 7 Block Diagram FB pin 6.1 DC/DC Conrol Wih he FB pin he LITIX Basic IC realizes he dynamic overhead conrol. The IC provides a volage feedback o an exernal DC/DC converer. Using he circui shown in Figure 17 i is possible o adjus he DC/DC oupu volage in a way ha he volage drop over he oupu sages of he LITIX Basic IC is minimized - dynamic overhead conrol. This leads o a significan reducion of he overall driver s power dissipaion and an increased sysem efficiency. Figure 17 gives an applicaion example, how differen ligh funcions can be conrolled using a µc, if an open load diagnosis per LED chain is required. Noe: For correc oupu curren conrol and dynamic overhead conrol he parameers as specified in Pos and Pos need o be considered. FB source currens higher han given in Pos lead o a drop of he FB regulaion volage V FB(nom). The resisor R FB(PD) can be dimensioned by applying equaions Equaion (2) and Equaion (3). The following parameers are required: V OUT represens he maximum LED loads forward volage, i.e. number of LEDs muliplied wih he maximum LED forward volage. Temperaure drifs of he LED s forward volage needs o be considered! V BO represens he DC/DC oupu volage, which is predefined by he feedback resisors (Figure 17: R FB1, R FB2, R FB3 ). Please refer o he according DC/DC device daa shee for he dimensioning of hose resisors. n len represens he numbers of LITIX Basics using he longes LED-chains (e.g. if here are 3 devices conneced o one DC/DC converer and wo devices using LED chains wih 7 LEDs and one device is used wih LED chain lenghs of 6 LEDs he according n len =2.) β represens he DC gain of he exernal bipolar ransisor, which is conneced o he DC/DC s feedback pin. min V OUT 0.5 V V = {, } A n len V BO V OUT 1.1 V n len R FB PD, min V OUT 1.1 V = V BO V OUT R FB PD, max R FB1 V OUT (2) (3) Daa Shee 13 Rev. 1.2

14 FB Pin 6.2 Elecrical Characerisics FB Pin Elecrical Characerisics FB pin Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max FB regulaion volage V FB(nom) (V OUT - V OUT -1 V I FB(SOC) = 25 µa * FB operaing volage a power sage V PS(FB) = V S - V OUTx V PS(FB) 10 V No subjec o producion es, specified by design Daa Shee 14 Rev. 1.2

15 IN_SETx Pin 7 IN_SETx Pin The IN_SET pin is a muliple funcion pin for oupu curren definiion, inpu and diagnosics: IN_SET Logic I IN_SET V IN_SET V IN_SET(OL/SC) GND Figure 8 Block Diagram IN_SET pin 7.1 Oupu Curren Adjusmen via RSET The oupu curren of each channel can be adjused independenly. The curren adjusmen can be done by placing a low power resisor (R SET ) a he IN_SETx pin o ground. The dimensioning of he resisor can be done using he formula below: R SET k = I OUT (4) The gain facor k (R SET * oupu curren) is specified in Pos and Pos The curren hrough he R SET is defined by he resisor iself and he reference volage V IN_SET(ref), which is applied o he IN_SET during supplied device. 7.2 Smar Inpu Pin The IN_SETx pin can be conneced via R SET o he open-drain oupu of a µc or o an exernal NMOS ransisor as described in Figure 9. This signal can be used o urn off he oupu sages of he IC. A minimum IN_SET curren of I IN_SET(ac) is required o urn on he oupu sages. This feaure is implemened o preven glimming of LEDs caused by leakage currens on he IN_SET pin, see Figure 11 for deails. In addiion, he IN_SET pin offers he diagnosic feedback informaion. In case of a faul even he IN_SET volage is increased o V IN_SET(OL/SC) Pos Therefore, he device has wo volage domains a he IN_SET-pin, which is shown in Figure 12. Noe: If one oupu has a presen faul (open load or shor circui) and one or boh of he oher channels are dimmed via PWM a he IN_SET-pins a shor spike o V IN_SET(OL/SC) is possible. Please refer o Chaper 8.3. Daa Shee 15 Rev. 1.2

16 IN_SETx Pin Microconroller (e.g. XC866) OUT R SET /2 R SET /2 IN_SET Curren adjus Basic LED Driver GND V DDP = 5 V IN Figure 9 Schemaics IN_SET inerface o µc The resuling swiching imes are shown in Figure 10: I IN_SET IOUT ON(IN_SET ) OFF(IN_SET) 100% 80% 20% Figure 10 Swiching imes via IN_SET Daa Shee 16 Rev. 1.2

17 IN_SETx Pin I OUT [ma] k = I OUTx * V IN_SET(ref) / I IN_SETx I OUTx I IN_SET(ACT) I IN_SETx I IN_SET [µa] Figure 11 I OUT versus I INSET V IN_SET V IN _SET(OL/SC)max Diagnosic volage range V IN_SET(OL/SC)min V IN _SET (ref ) m ax Normal operaion and high emperaure curren reducion range Figure 12 Volage domains for IN_SET pin, if ST pin is conneced o GND Daa Shee 17 Rev. 1.2

18 Load Diagnosis 8 Load Diagnosis 8.1 Open Load An open load diagnosis feaure is inegraed in he driver IC. If here is an open load on one of he oupus, he respecive oupu is urned off. The poenial on he IN_SET pin rises up o V IN_SET(OL/SC). This high volage can be used as inpu signal for an µc as shown in Figure 9. The open load saus is no lached, as soon as he open load condiion is no longer presen, he oupu sage will be urned on again. An open load condiion is deeced, if he volage drop over he oupu sage V PS is below he hreshold according Pos and a filer ime of OL is passed. V IN_SET V IN _SET(OL/SC) V IN_SET(ref ) V OUT OL IN_SET (rese) V S VS VPS(OL) V F open load occurs open load disappears Figure 13 IN_SET behavior during open load condiion 8.2 Shor Circui o GND deecion The has an inegraed SC o GND deecion. If he oupu sage is urned on and he volage a he oupu falls below V OUT(SC) he poenial on he IN_SET pin is increased up o V IN_SET(OL/SC) afer SC. This condiion is no lached. For deecing a normal condiion afer a shor circui deecion an oupu curren according o I OUT(SC) is driven by he channel. Daa Shee 18 Rev. 1.2

19 Load Diagnosis V IN_SET VIN _SET(OL/SC) V IN _SET(ref ) V OUT SC IN_SET( rese) VF VOUT (SC) shor circui occurs shor circui disappears Figure 14 IN_SET behavior during shor circui o GND condiion wih ST conneced o GND and V DEN > V DEN(ac) 8.3 Double Faul Condiions The allows he diagnosis of each channel separaely. The diagnosis filer imes OL and SC (Pos and Pos ) are valid only for he channel, which diagnoses firs he faul condiion. For he oher channel or channels wih a subsequenial faul he diagnosis is repored immediaely wihou he diagnosis filer ime, if he filer ime OL has been elapsed for he channel wih he firs faul. During acivaion via IN_SET of a non-fauly oupu, where one channel has already a faul deeced, a shor spike o V IN_SET(OL/SC) could occur on he channel, which should be acivaed. Therefore, in general a diagnosis should be done earlies afer he diagnosis filer imes OL and SC o avoid any incorrec diagnosis readou. In he scenario menioned above he urn on ime ON(IN_SET) could be exended. The following figure shows he example behavior, if OUT1 has a faul and OUT2 is operaed in PWM-mode. OUT3 is disabled. Daa Shee 19 Rev. 1.2

20 Load Diagnosis I IN_SET1 VIN_SET(OL/SC) / RSET1 VIN_SET(ref ) / RSET1 V IN_SET 1 V IN _SET(OL/SC) V IN _SET(ref ) V OUT1 OL VS V S V PS(OL) VF I IN_SET2 V IN _SET(OL/SC) / R SET2 open load occurs V IN _SET(ref ) / R SET2 V IN_SET2 VIN _SET(OL/SC) urn on command VIN _SET(ref ) V OUT2 V F VOUT ( SC) Figure 15 Example single channel faul on OUT1 and PWM-operaion on OUT2 Daa Shee 20 Rev. 1.2

21 Load Diagnosis 8.4 Elecrical Characerisics IN_SET Pin and Load Diagnosis Elecrical Characerisics IN_SET pin and Load Diagnosis Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SETx = 12 kω, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max IN_SET reference volage IN_SET open load/shor circui volage IN_SET open load/shor circui volage IN_SET open load/shor circui curren V IN_SET(ref) V V OUTx =3.6V T j = C V IN_SET(OL/SC) V V S > 8 V T j = C V S = V OUTx (OL) or V OUTx = 0V (SC) V IN_SET(OL/SC) V I IN_SET(OL/SC) ma V S = 5.5 V T j = C V S = V OUTx (OL) or V OUTx = 0 V (SC) V S > 8 V T j = C V IN_SET = 4 V V S = V OUTx (OL) or V OUTx = 0 V (SC) OL deecion filer ime OL µs V S >8V OL deecion volage V PS(OL) V V S >8V V PS(OL) = V S - V OUTx Shor circui o GND V OUT(SC) V V S >8V deecion hreshold SC deecion filer ime SC µs V S > 8 V IN_SET diagnosis rese IN_SET(rese) 5 20 µs V S > 8 V ime SC deecion curren I OUT(SC) ma V S > 8 V V OUTx = 0 V IN_SET acivaion I IN_SET(ac) 2 15 µa See Figure 11 curren wihou urn on of oupu sages No subjec o producion es, specified by design Daa Shee 21 Rev. 1.2

22 Power Sage 9 Power Sage The oupu sages are realized as high side curren sources wih a curren of 120 ma. During off sae he leakage curren a he oupu sage is minimized in order o preven a slighly glowing LED. To increase he overall oupu curren for high brighness LED applicaions i is possible o connec wo or all hree oupu sages in parallel. The maximum curren of each channel is limied by he power dissipaion and used PCB cooling areas (which resuls in he applicaions R hja ). For an operaing curren conrol loop he supply and oupu volages according o he following parameers have o be considered: Required supply volage for curren conrol V S(CC), Pos Volage drop over oupu sage during curren conrol V PS(CC), Pos Required oupu volage for curren conrol V OUTx(CC), Pos Proecion The device provides embedded proecive funcions, which are designed o preven IC desrucion under faul condiions described in his daa shee. Faul condiions are considered as ouside normal operaing range. Proecive funcions are neiher designed for coninuous nor for repeiive operaion Over Load Behavior An over load deecion circui is inegraed in he LITIX Basic IC. I is realized by a emperaure monioring of he oupu sages (OUTx). As soon as he juncion emperaure exceeds he curren reducion emperaure hreshold T j(crt) he oupu curren will be reduced by he device by reducing he IN_SET reference volage V IN_SET(ref). This feaure avoids LED s flickering during saic oupu overload condiions. Furhermore, i proecs LEDs agains over emperaure, which are mouned hermally close o he device. If he device emperaure sill increases, he hree oupu currens decrease close o 0 A. As soon as he device cools down he oupu currens rise again. I OUT V IN_SET T j(crt) T j Figure 16 Oupu curren reducion a high emperaure Noe: This high emperaure oupu curren reducion is realized by reducing he IN_SET reference volage volage (Pos In case of very high power loss applied o he device and very high juncion emperaure he oupu curren may drop down o I OUTx = 0 ma, afer a sligh cooling down he curren increases again. Daa Shee 22 Rev. 1.2

23 Power Sage Reverse Baery Proecion The has an inegraed reverse baery proecion feaure. This feaure proecs he driver IC iself, bu also conneced LEDs. The oupu reverse curren is limied o I OUTx(rev) by he reverse baery proecion. Noe: Due o he reverse baery proecion a reverse proecion diode for he ligh module may be obsolee. In case of high ISO-pulse requiremens and only minor proecing componens like capaciors a reverse proecion diode may be reasonable. The exernal proecion circui needs o be verified in he applicaion. 9.2 Elecrical Characerisics Power Sage Elecrical Characerisics Power Sage Unless oherwise specified: V S = 5.5 V o 18 V, T j = -40 C o +150 C, V OUTx = 3.6 V, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Oupu leakage curren I OUTx(leak) Oupu leakage curren in boos over baery seup 7 3 µa V EN = 5.5 V I IN_SET = 0µA V OUTx =2.5V T j = 150 C T j = 85 C - 50 µa V EN = 5.5 V I OUTx(leak,B2B) I IN_SET =0µA V OUTx = V S = 40 V Reverse oupu curren -I OUTx(rev) 1 µa V S = -16 V Oupu load: LED wih break down volage <-0.6V Oupu curren accuracy limied emperaure range Oupu curren accuracy over emperaure Volage drop over power sage during curren conrol V PS(CC) = V S - V OUTx Required oupu volage for curren conrol k LT k ALL T j = C V S = V V PS = 2 V R SETx = kω R SETx = 30 kω T j = C V S = V V PS = 2 V R SETx = kω R SETx = 30 kω V PS(CC) 0.75 V V S = 13.5 V R SETx = 12 kω I OUTx 90% of (k LT(yp) /R SETx ) V OUTx(CC) 2.3 V V S = 13.5 V R SETx = 12 kω I OUTx 90% of (k LT(yp) /R SETx ) Daa Shee 23 Rev. 1.2

24 Power Sage Elecrical Characerisics Power Sage (con d) Unless oherwise specified: V S = 5.5 V o 18 V, T j = -40 C o +150 C, V OUTx = 3.6 V, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Maximum oupu curren I OUT(max) 120 ma R SETx = 4.7 kω The maximum oupu curren is limied by he hermal condiions. Please refer o Pos Pos IN_SET urn on ime ON(IN_SET) 15 µs V S = 13.5 V I IN_SET = µa I OUTx = 80% of (k LT(yp) /R SETx ) No OL or SC a oher channels IN_SET urn off ime OFF(IN_SET) 10 µs V S = 13.5 V I IN_SET = 100 0µA I OUTx = 20% of (k LT(yp) /R SETx ) VS urn on ime ON(VS) 20 µs 2) V EN =5.5V R SETx = 12 kω V S = V I OUTx = 80% of (k LT(yp) /R SETx ) Curren reducion emperaure hreshold Oupu curren during curren reducion a high emperaure T j(crt) 140 C I OUT(CRT) No subjec o producion es, specified by design 2) see also Figure 6 85% of (k LT(yp) /R SETx ) I OUTx = 95% of (k LT(yp) /R SETx ) A R SETx =12kΩ T j = 150 C Daa Shee 24 Rev. 1.2

25 Applicaion Informaion 10 Applicaion Informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. D RV L BO DBO V IN VBO V BATT CIN IN TLD5095 SWO SWCS SGND OVFB R CS C BO TSW R OVH R OVL RFB1 CVS =4.7nF VS Inernal supply EN Thermal proecion IN_ SET3 IN_ SET2 Curren adjus IN_ SET1 LITIX Basic Oupu conrol OUT3 OUT2 OUT1 DC/ DC conrol FB GND 4.7nF** 4.7nF** 4.7nF** ST RSET3 RSET2 RSET1 EN / PWMI FREQ / SYNC COMP FBH FBL R FB2 V BO V IN RFREQ C COMP RCOMP IVCC CIVCC PWMO GND R FB3 DIAG funcion A OUT funcion A Microconroller (e.g. XC866) EN RFB(PD) 1nF CVS =4.7nF VS Inernal supply EN Thermal proecion IN_ SET3 IN_ SET2 Curren adjus IN_ SET1 LITIX Basic Oupu conrol OUT 3 OUT 2 OUT 1 DC / DC conrol FB GND 4.7nF** 4.7nF** 4.7nF** DIAG funcion B OUT funcion B RSET3 RSET2 RSET1 VIN ** For EMI improvemen, if required. Figure 17 Sysem diagram DC/DC conrol Boos using 3 IN_SET pins Noe: This is a very simplified example of an applicaion circui. The funcion mus be verified in he real applicaion Furher Applicaion Informaion For furher informaion you may conac hp:// Daa Shee 25 Rev. 1.2

26 Package Oulines 11 Package Oulines Sand Off (1.45) 1.7 MAX. C 0.08 C 0.35 x ± C D ± MAX ±0.05 2) 0.15 M C A-B D 14x D 6 ± M D 8x Boom View A B 0.1 C A-B 2x 4.9 ±0.1 Exposed Diepad 3 ± ±0.2 Index Marking Does no include plasic or meal prorusion of 0.15 max. per side 2) Does no include dambar prorusion Dimensions in mm PG-SSOP-14-1,-2,-3-PO V02 Figure 18 PG-SSOP-14 Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp:// Daa Shee 26 Rev. 1.2

27 Revision Hisory 12 Revision Hisory Revision Dae Changes Inial revision of daa shee Updaed parameers K LT and K ALL in he chaper Power Sage 1.2 Updaed o laes emplae 1.2 Updaed applicaion drawing 1.2 Updaed package marking 1.2 Updaed package figure Daa Shee 27 Rev. 1.2

28 Table of Conens 1 Overview Block Diagram Pin Configuraion Pin Assignmen Pin Definiions and Funcions General Produc Characerisics Absolue Maximum Raings Funcional Range Thermal Resisance EN Pin EN Funcion Inernal Supply Pin EN Unused EN - Pull Up o VS EN - Direc Connecion o VS Elecrical Characerisics Inernal Supply / EN Pin FB Pin DC/DC Conrol Elecrical Characerisics FB Pin IN_SETx Pin Oupu Curren Adjusmen via RSET Smar Inpu Pin Load Diagnosis Open Load Shor Circui o GND deecion Double Faul Condiions Elecrical Characerisics IN_SET Pin and Load Diagnosis Power Sage Proecion Over Load Behavior Reverse Baery Proecion Elecrical Characerisics Power Sage Applicaion Informaion Furher Applicaion Informaion Package Oulines Revision Hisory Table of Conens Daa Shee 28 Rev. 1.2

29 Trademarks All referenced produc or service names and rademarks are he propery of heir respecive owners. Ediion Published by Infineon Technologies AG Munich, Germany 2018 Infineon Technologies AG. All Righs Reserved. Do you have a quesion abou any aspec of his documen? erraum@infineon.com Documen reference IMPORTANT NOTICE The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics ("Beschaffenheisgaranie"). Wih respec o any examples, hins or any ypical values saed herein and/or any informaion regarding he applicaion of he produc, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion warranies of non-infringemen of inellecual propery righs of any hird pary. In addiion, any informaion given in his documen is subjec o cusomer's compliance wih is obligaions saed in his documen and any applicable legal requiremens, norms and sandards concerning cusomer's producs and any use of he produc of Infineon Technologies in cusomer's applicaions. The daa conained in his documen is exclusively inended for echnically rained saff. I is he responsibiliy of cusomer's echnical deparmens o evaluae he suiabiliy of he produc for he inended applicaion and he compleeness of he produc informaion given in his documen wih respec o such applicaion. For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( WARNINGS Due o echnical requiremens producs may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies office. Excep as oherwise explicily approved by Infineon Technologies in a wrien documen signed by auhorized represenaives of Infineon Technologies, Infineon Technologies producs may no be used in any applicaions where a failure of he produc or any consequences of he use hereof can reasonably be expeced o resul in personal injury.