PT8A A-F/67A/68A NTC Heating Controller with Multi LEDs

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Stephen Fitzgerald
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1 PTA-A-F/A/A Feaures / seps hea emperaure seings wih EDs or EDs indicaor Auo emperaure conrol wih TC TC open proecion Pulse rigger for high curren / TRIAC (up o ma) Auo power off afer exac Hour heaing(i is opional o disable.) Dual Volage (0/0V 0/0Hz) operaions (only PTA-A/B/C available) Auo deec power supply Volage (0V/0V) and frequency (0/0Hz) Inernal V Zener DIP- and SOIC- package Applicaions Ceramic heaing conroller Pin Configuraion T TC CK K K Pin Descripion PTAx 0 Descripion The PTA///// are mixed signal CMOS SI chips specially designed for heaing conroller wih he exernal TC (egaive Temperaure Componen) sensor. TC open proecion is implemened for device safey and selecable or heaing emperaure levels. PTA/ are for sep levels (eg.00, 0, 0, 0, 0 ) and PTA/ are for sep levels (eg. 00, 0, 0, 0, 0, 00 ). They can drive TRIAC or direcly and deec he heaer s emperaure wih TC sensor inpu. They have up/down keys for emperaure seing, On/Off Key for heaing on/off conrol and EDs display mode. PTA/ have sep levels (eg.00, 0, 0, 0, 0, 00 ). They can drive TRIAC or direcly and deec he heaer s emperaure wih TC sensor inpu. They have up/down keys for emperaure seing and On/Off Key for heaing on/off conrol. They also have second ( seconds for PTAA) delay funcion before go ino off sae and lock-key funcion. Their EDs have special running flash mode (mode ) These devices can be used in boh 0V and 0V power line sysem, as hey can auomaically adjus he heaing power according o he power line volage o avoid heaing appliance damage or long heaing ime. They have selecable build-in imer o enable/ disable auo-power off funcion afer urn on hour and he imer is hour boh under 0Hz and 0Hz power supply. ame Pin o. Type Descripion T I TC volage inpu, TC open deecion inpu YC O Oupu signal for TC open deecion CK I Clock inpu from power line I Timer be disabled if ied ground O O sae indicaor / lock key indicaor for A/A K I UP, DOW push buon inpu K I push buon inpu ~ - O Six emperaure seps indicaor ED~ED oupu O TRIAC and rigger oupu Ground Ground Power Power Supply.

2 PTA-A-F/A/A Maximum Raings Sorage Temperaure... - o C o 0 o C Ambien Temperaure wih Power applied o C o o C Supply Volage o Ground Poenial (Inpu & V DD Only) V o.v Supply Volage o Ground Poenial (Oupu s Only) V o.v DC Inpu Volage V o.v Inpu/Oupu Curren... 0mA Inpu/Oupu Curren (Pin, VB only)... 00mA Power Dissipaion... 00mW oe: Sresses greaer han hose lised under MAXIMUM TIGS may cause permanen damage o he device. This is a sress raing only and funcional operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. Exposure o absolue maximum raing condiions for exended periods may affec reliabiliy. Recommended operaion condiions Sym Parameer Pin Min Typ Max Uni V DD Operaing Volage.0 V Z - V T A Operaing emperaure C F CK Frequency of CK CK - 0/0 - Hz DC Elecrical Characerisics DC Inpu Elecrical Characerisics (V DD =.V, T A = -0 ~ ºC, unless oherwise noed) Symbol Descripion Tes Condiions Min Type Max VT_ T I IH I I R PU-UP R PU- DOW Volage of T Inpu high curren Inpu low curren Inernal pull-up resisance Inernal pulldown resisance Uni evel Temp(ºC) -half half half... Pin:T 0... V DD =.V -half... V half half PI: V I = V DD - - ua PI: CK V I = V DD - - A PI: T V I = V DD na PI: V I = ua PI: CK V I = - - A PI: T V I = na PI: K, K KΩ PI: K, K KΩ

3 PTA-A-F/A/A DC Oupu Elecrical Characerisics Symbol Descripion Tes Condiions Min Type Max Uni I OH I O Oupu High Curren Oupu ow Curren Power Supply Characerisics PI: PI: - PI: PI: PI: - PI: PI: TC V DD =.V V OUT =.V V DD =.V V OUT =.0V V DD =.V V OUT =.0V V DD =.V V OUT =0.V V DD =.V V OUT =0.V V DD =.V V OUT =0.V V DD =.V V OUT = 0.V Symbol Descripion Tes Condiions Min Type Max Uni V POR Volage of POR V I DD Curren consumpion o loading, V DD =.V A Vz Volage of Zener I DD =00 A~0mA..0. V T PO Power off imer F CK = 0/0Hz 0 Min ine Clock Synchronizaion Characerisics Symbol Descripion Tes Condiions Min Type Max Uni V TCK V EVE Compare Threshold Volage of CK Pin 0V/0V evel Threshold Volage of CK Pin oe: The four comparaors (VT~VT) have abou 00mV hyseresis Pulse Characerisics VT 0 V CK >V VT EVE VT V CK <V VT EVE V DD =.V...0 V ma ma mv Symbol Descripion Tes Condiions Min Type Max Uni Tal_Ga e Widh of Gae rigger pulse Inernal RC Oscillaor Frequency Characerisics V DD =.0~V Z ; T A =-0~ºC s Symbol Descripion Tes Condiions Min Type Max Uni Fosc Frequency of RC Oscillaor V DD =.0~V Z ; T A =-0~ºC. 0. KHz V DD =.0~V Z ; T A =ºC 0 KHz

4 PTA-A-F/A/A Block Diagram

5 PTA-A-F/A/A Funcional Descripion Inpu Buon For PTA/// ) Up buon: Temperaure up adjusmen. Push i once he emperaure seing will increase one level unil he highes level is reached. ) Down buon: Temperaure down adjusmen. Push Down buon once, he emperaure seing will reduce one level unil he lowes level is reached. ) On/Off buon: This buon is oggled on Heaing-on sae and Heaing-off sae. For -key mode, his key will be se he emperaure by loop: Off () Off When power on IC firs, he iniial emperaure seing is evel (Inernal opion: evel) Delay funcion: Heaing-on & Heaing-off has no delay (Inernal opion: Heaing-on has 0. second delay & Heaingoff has second delay). ) : When in O sae, oupu high. For PTAA/A ) Up buon: Temperaure up adjusmen. Push Up buon once, he emperaure seing will increase one level unil he highes level is reached. ) Down buon: Temperaure down adjusmen. Push Down buon once, he emperaure seing will reduce one level unil he lowes level is reached. ) On/Off buon: This buon is oggled on Heaing-on sae and Heaing-off sae. PAAA: When power on IC firs, he iniial emperaure seing is evel PAAA: When power on IC firs, he iniial emperaure seing is evel If power is always on IC, he las seing emperaure level will be memorized when push O again Delay funcion: PTAA: Heaing-on has no delay & Heaing-off has second delay PTAA: Heaing-on has no delay & Heaing-off has second delay ) : ock key funcion When in Heaing-on sae, afer coninuously push on/off key down wice( The inerval is less han 00ms ), IC will lock curren emperaure level sae and disable up/down and on/off funcion, pin oupu high level When in lock sae push on/off key down wice again, IC will unlock curren emperaure level sae and enable up/down and on/off funcion, pin oupu low level EDs indicaor: ED: evel emperaure seing ( eg. 00 ) ED: evel emperaure seing ( eg. 0 ) ED: evel emperaure seing ( eg. 0 ) ED: evel emperaure seing ( eg. 0 ) ED: evel emperaure seing ( eg. 0 ) ED: evel emperaure seing ( eg. 00, for PTA/x, PTAA/A) ) Mode Sandby/Off sae: ED ~ ED are all off On Sae: The ED ha be seing level is on. ) Mode Sandby/Off sae: ED ~ ED are all off On sae: Heaing up: The ED ha be seing level is Flash. (Fclk/) Sable: This ED is on Drop: This ED is on ) Mode Sandby/Off sae: ED ~ ED are all off On sae: The ED ha be seing level and below he seing level are on. ) Mode Sandby/Off sae: ED ~ ED are all off On sae: evel : Heaing up/ Drop: ED is flash (Fclk/) Sable: ED is on evel: Heaing up/ Drop: ED and ED is round flash (Fclk/) Sable: ED and ED are on evel ~ eve: similar as upon oe:. When in sable sae, don flash even if deec he below or over seing emperaure(for mode and mode). When push up/down key, he seing ED will be on sae for.s before saring flashing(for mode and mode). When push up/down key, he seing ED will be forced o flash for.s (for mode) ) TC open sae The ED ha relae wih he seing emperaure is fas flash (Fclk/) Disable up/down key funcion If deec TC is no open, recover working sae ) ED drive syle ED-ED: High pulse drive (0Hz) : High level drive, PTA/A use pulse drive (0Hz) Rese Afer power on, he chip will be rese by inernal POR circui,, ED and pins oupu low level and IC is in Sandby sae Timer Once IC eners Heaing-on sae, inernal imer will sar o coun. I ll be imeou and auo heaing-off afer exac hour boh under 0Hz and 0Hz. This funcion can be disabled by Pin is ied o ground. The imer will be clear while push up/down key. Conrol signal oupu When working in Heaing-on sae, Gae oupu will be relaed o T inpu and CK inpu ampliude.

6 PTA-A-F/A/A Effec of TC and VT CK evel on. Workin g Sae O CK inpu volage V CK >V EVE (0v) V CK <V EVE (0v) TC (TC open deecion) V TCO~ V DD TC (ormal emp deecion) (rigger o /TRIAC) A,B,C (suffix) D,E,F (suffix) Below 0% seing emperaure % 00% Over 0% seing emperaure.% 0% Over seing emperaure 0 0 Below 0% seing emperaure 00% 00% Over 0% seing emperaure 0% 0% Over seing emperaure 0 0 Off X* X 0 0 X X 0~V TCO X 0 0 *oe: ) X means any inpu.

7 PTA-A-F/A/A Effec of TC and Pulse Trigger on a) High rigger peak curren (>ma), enough rigger A riac b) Pulse riggering reduce he false self rigger by he leakage of riac a high emperaure environmen. c) Tal_ = 00us (Inernal opion: 00us, 00us) d) 0VAC inpu, under half power sae, he minimum heaing-period is cycles (Inernal opions:,,, cycles) e) The drive pulse presen a boh posiive edge and negaive edge (Inernal opion: only posiive edge)

8 VAC IPUT VAC IPUT PTA-A-F/A/A Applicaion Circui Applicaion circui for PTAA/B/D/E D R /W T uf/0v C UP DOW Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAA/B/D/E R R R R R R ED ED ED ED ED R0 R Applicaion circui for PTAC/F R C /AC0V R /W D D T uf/0v C UP DOW Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAC/F R R R R R R ED ED ED ED ED R0 R

9 VAC IPUT VAC IPUT PTA-A-F/A/A Applicaion circui for PTAA/B/D/E D R /W T uf/0v C Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAA/B/D/E R R ED R ED R ED R ED R ED Applicaion circui for PTAC/F R C /AC0V R /W D D T uf/0v C Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAC/F R R R R R R ED ED ED ED ED

10 VAC IPUT VAC IPUT PTA-A-F/A/A Applicaion circui for PTAA/B/D/E D R /W T uf/0v C UP DOW Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAA/B/D/E R R R R R R R ED ED ED ED ED ED R0 R Applicaion circui for PTAC/F R C /AC0V R /W D D T uf/0v C UP DOW Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAC/F R R R R R R R ED ED ED ED ED ED R0 R 0

11 VAC IPUT VAC IPUT PTA-A-F/A/A Applicaion circui for PTAA/B/D/E D R /W T uf/0v C Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAA/B/D/E R R ED R ED R ED R ED R ED R ED Applicaion circui for PTAC/F R C /AC0V R /W D D T uf/0v C Q R C R.k R 00 C 0nF C 0K U T CT K CK K 0 PTAC/F R R ED R ED R ED R ED R ED R ED

12 0 VAC IPUT PTA-A-F/A/A Applicaion circui for PTAA/A R F 0V/A VAR Q F P FUSE C /AC0V R /W D D C RT TC E uf/0v D.V T R CT K 0K CK K R R C R.k 0nF 0 R R R R 00 R C PTAA/A R U UP R ED ED ED ED ED ED ED DOW R0 R

13 PTA-A-F/A/A Mechanical Informaion PE (DIP-) oe: ) Conrolling dimensions in millimeers. ) Ref: JEDEC MS-00D/BB PKG. DIMESIOS(MM) SYMBO Min Max A.. A 0. A.0.0 B B. BSC c D.0.0 E.0.0 E.. e. BSC.00.0 E.0.00

14 PTA-A-F/A/A WE (SOIC-) oe: ) Conrolling dimensions in millimeers. ) Ref: JEDEC MS-0E/AC PKG. DIMESIOS(MM) SYMBO MI MAX A.. A A.. b c D E.0.00 E.0.0 e. BSC 0.0. θ 0

15 PTA-A-F/A/A Ordering Informaion oe: Ordering o. Package Code Package PTAxXPE P ead free -pin DIP PTAxXWE W ead free -pin SOIC PTAAPE P ead free -pin DIP PTAAWE W ead free -pin SOIC PTAAPE P ead free -pin DIP PTAAWE W ead free -pin SOIC x shows 0~ and X shows A-F wih differen funcion. See Funcion Comparison Table. E = Pb-free Adding X Suffix= Tape/Reel Funcion Comparison Table Temp. evels Key Mode ED mode** Dual volage P/ Seps Seps -key -key Mode Mode Mode Y A B C* D* E* F* A* B* C* D* E* F* A* B* C* D* E* F* A* B* C* D* E* F* A* - *** - Mode - A* - *** - Mode - oe *: Conac Pericom for availabiliy **: ED mode descripion see Funcional Descripion, Page. ***: PTAA key mode is -keydelaylock key(heaing off has s delay and lock-key funcion). PTAA key mode is -keydelaylock-key(heaing off has s delay and lock-key funcion). Pericom Semiconducor Corporaion Pericom reserves he righ o make changes o is producs or specificaions a any ime, wihou noice, in order o improve design or performance and o supply he bes possible produc. Pericom does no assume any responsibiliy for use of any circuiry described oher han he circuiry embodied in Pericom produc. The company makes no represenaions ha circuiry described herein is free from paen infringemen or oher righs, of Pericom.

PI74STX1G126. SOTiny Gate STX Buffer with 3-State Output. Features. Descriptio n. Block Diagram. Pin Configuration

PI74STX1G126. SOTiny Gate STX Buffer with 3-State Output. Features. Descriptio n. Block Diagram. Pin Configuration PI74STXG6 4567890456789045678904567890456789045678904567890456789045678904567890456789045678904567890 4567890456789045678904567890456789045678904567890456789045678904567890456789045678904567890 SOTiny