Data Sheet, Rev. 1.0, March 2008 BTS4130QGA. Smart High-Side Power Switch. Automotive Power
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1 Daa Shee, Rev. 1.0, March 2008 Smar High-Side Power Swich Auomoive Power
2 BTS 4130QGA 1 Overview 3 2 Block Diagram 5 3 Pin Configuraion Pin Assignmen Pin Definiions and Funcions Volage and Curren Definiion 7 4 General Produc Characerisics Absolue Maximum Raings Funcional Range Thermal Resisance 9 5 Power Sage Oupu ON-Sae Resisance Turn ON / OFF Characerisics Inducive Oupu Clamp Maximum Load Inducance Elecrical Characerisics Power Sage 13 6 Proecion Mechanisms Loss of Ground Proecion Undervolage Proecion Overvolage Proecion Reverse Polariy Proecion Overload Proecion Curren Limiaion Elecrical Characerisics Proecion Funcions 17 7 Diagnosic Mechanism ST 0/1/2/3 Pin ST0/1/2/3 Signal in Case of Failures Diagnosic in Open Load, Channel OFF ST 0/1 Signal in case of Over Temperaure Elecrical Characerisics Diagnosic Funcions 21 8 Inpu Pins Inpu Circuiry Elecrical Characerisics 22 9 Applicaion Informaion Furher Applicaion Informaion Package Oulines Revision Hisory 25 Daashee 2 1.0,
3 Smar High-Side Power Swich Four Channel Device 1 Overview Basic Feaures Wihsand low Cranking Volage Fi for 12V Applicaion Four Channel device Very low Sand-by Curren CMOS Compaible Inpus Elecrosaic Discharge Proecion (ESD) Opimized Elecromagneic Compaibiliy Logic ground independen from load ground Very low Leakage Curren from OUT o he load in OFF Sae Green Produc (RoHS complian) AEC Qualified PG-DSO Descripion The is a quad channel Smar High-Side Power Swich. I is embedded in a PG-DSO package, providing proecive funcions and diagnosics. The power ransisor is buil by a N-channel power MOSFET wih charge pump. The device is monolihically inegraed in Smar echnology. I is specially designed o drive relays as well as resisive loads in he harsh auomoive environmen. Table 1 Elecrical Parameers (shor form) Parameer Symbol Value Operaing volage range OP 5.5V... 20V Undervolage swich OFF a T j = -40 C V s (USO) 3.2V Maximum load per channel P BULB 2 * R5W, relays or LED Over volage proecion (AZ) 43V Max ON Sae resisance a T j = 150 C per channel R DS(ON) 260mΩ Nominal load curren (one channel acive) I L (nom) 1.8A Minimum curren limiaion I L_SCR 5A Sandby curren for he whole device wih load I S(off) 16µA Maximum reverse baery volage -V s(rev) 32V Type Package Marking PG-DSO Daa Shee 3 Rev. 1.0,
4 Overview Diagnosic Feaure Open load deecion in OFF sae Feedback of he hermal shudown in ON sae Diagnosic feedback wih open drain oupu Proecion Funcions Shor circui proecion Overload proecion Curren limiaion Thermal shudown Overvolage proecion (including load dump) wih exernal resisor Reverse baery proecion wih exernal resisor Loss of ground and loss of proecion Elecrosaic discharge proecion (ESD) Applicaion All ypes of resisiv, inducive and capaciive loads Daa Shee 4 Rev. 1.0,
5 Block Diagram 2 Block Diagram Channel 0 IN0 inernal power supply driver logic over emperaure gae conrol & charge pump volage sensor clamp for inducive load over curren swich off T ESD proecion open load deecion OUT 0 ST 0/1 Channel 1 T IN1 Conrol and proecion circui equivalen o channel 0 OUT 1 Channel 2 IN2 inernal power supply driver logic over emperaure gae conrol & charge pump volage sensor clamp for inducive load over curren swich off T ESD proecion open load deecion OUT 2 ST 2/3 Channel 3 T IN3 Conrol and proecion circui equivalen o channel 0 OUT 3 GND Block diagram.emf Figure 1 Block diagram for he Daa Shee 5 Rev. 1.0,
6 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen Vs 1 20 Vs GND0/ Vs IN OUT0 ST 0/ OUT1 IN Vs GND2/ Vs IN OUT2 ST2/ OUT3 IN Vs Vs Vs Pinou SO20 shared diag.vsd Figure 2 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol Funcion 1, 10, 11, 12, 15, 16, 19, 20 Baery volage; Design he wiring for he simulaneous maximum shor circui currens from channel 0 and 1 and also for low hermal resisance 2 GND0/1 Ground; Ground connecion for channel 0 and 1 3 IN0 Inpu channel 0; Inpu signal for channel 0. Acivae he channel in case of logic high level 4 ST 0/1 Diagnosic feedback; of channel 0/1. Open drain. 5 IN1 Inpu channel 1; Inpu signal for channel 1. Acivae he channel in case of logic high level 6 GND2/3 Ground; Ground connecion for channel 2 and 3 7 IN2 Inpu channel 2; Inpu signal for channel 2. Acivae he channel in case of logic high level 8 ST 2/3 Diagnosic feedback; of channel 2/3. Open drain. 9 IN3 Inpu channel 3; Inpu signal for channel 3. Acivae he channel in case of logic high level Daa Shee 6 Rev. 1.0,
7 Pin Configuraion Pin Symbol Funcion 13 OUT3 Oupu 3; Proeced High side power oupu channel 3 14 OUT2 Oupu 2; Proeced High side power oupu channel 2 17 OUT1 Oupu 1; Proeced High side power oupu channel 1 18 OUT0 Oupu 0; Proeced High side power oupu channel Volage and Curren Definiion Figure 3 shows all erms used in his daa shee, wih associaed convenion for posiive values. I S V DS0 V DS1 V DS2 V DS3 I IN0 IN0 OUT0 I OUT0 V IN0 I IN1 IN1 OUT1 I OUT1 V IN1 I ST0/1 ST 0/1 T0/1 I IN2 IN2 OUT2 I OUT2 I IN3 IN3 OUT3 I OUT3 I ST2/3 ST 2/3 GND I GND V OUT0 V OUT1 V OUT2 V OUT3 Volage and curren convenion quad shared diag.vsd Figure 3 Volage and curren definiion Daa Shee 7 Rev. 1.0,
8 General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Absolue Maximum Raings 1) T J = 25 C; (unless oherwise specified) Pos. Parameer Symbol Limi values Uni Condiions Min. Max. Volages Supply volage V Reverse polariy Volage - (REV) 32 V Supply volage for shor circui proecion V ba(sc) 0 20 V R ECU = 20mΩ, R Cable = 16mΩ/m, L Cable = 1µH/m, l = 0 or 5m 2) see Chaper 6 Inpu pins Volage a INPUT pins V IN V Curren hrough INPUT pins I IN ma Curren hrough INPUT pins pulsed I IN -5 5 ma Only for esing Saus pin Curren hrough ST 0/1 pin I ST0/1-5 5 ma Curren hrough ST 2/3 pin I ST2/3-5 5 ma Power sage Load curren I L I L(LIM) A Power dissipaion (DC), all channel acive Maximum Swichable energy, single pulse P TOT 1.4 W T A = 85 C, T j <150 C E AS 76 mj I L = 2.3A, = 12V Temperaures Juncion Temperaure T j C Dynamic emperaure increase while T j 60 K swiching Sorage Temperaure T sg C ESD Suscepibiliy ESD Resisiviy IN pin V ESD -1 1 kv HBM 3) ESD Resisiviy ST 0/1, 2/3 pins V ESD -4 4 kv HBM 3) ESD Resisiviy OUT o all oher pins V ESD -5 5 kv HBM 3) shored 1) No subjec o producion es, specified by design 2) Se up in accordance o AEC Q and AEC Q ) ESD suscepibiliy HBM according o EIA/JESD 22-A 114B Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Daa Shee 8 Rev. 1.0,
9 General Produc Characerisics Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 4.2 Funcional Range T j = -40 C o +150 C; (unless oherwise specified) Pos. Parameer Symbol Limi values Uni Condiions Min. Max Operaing Volage OP V V IN = 4.5V, R L = 12Ω, V DS < 0.5V Undervolage swich OFF UV 3.2 V - 1), T j = -40 C, V DS < 0.5V Operaing curren I GND ma V IN = 5V One channel acive 0.9 Four channels acive Sandby curren for whole device wih load 1) Baery volage is decreasing 2) No subjec o producion es. Specified by design I S(OFF) µa T j = 25 C T j = 85 C 2) T j = 150 C, V s = 12V, R L = 12Ω, V IN = 0V Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 4.3 Thermal Resisance Pos. Parameer Symbol Limi values Uni Condiions Min. Typ. Max Juncion o Soldering Poin each channel R hjsp 15 K/W 1) Juncion o Ambien R hja 45 K/W wih 6cm² cooling area 1) 1) No subjec o producion es, specified by design Daa Shee 9 Rev. 1.0,
10 Power Sage 5 Power Sage The power sages are buil by an N-channel verical power MOSFET (DMOS) wih charge pump. 5.1 Oupu ON-Sae Resisance The ON-sae resisance R DS(ON) depends on he supply volage as well as he juncion emperaure T j. Figure 4 shows he dependencies for he ypical ON-sae resisance. The behavior in reverse polariy is described in Chaper Rdson -40 C Rdson +25 C Rdson +150 C 200 Rdson (mohm) VS (V) ron.vsd Figure 4 Typical ON-sae resisance A high signal (See Chaper 8) a he inpu pin causes he power DMOS o swich ON wih a dedicaed slope, which is opimized in erms of EMC emission. 5.2 Turn ON / OFF Characerisics Figure 5 shows he ypical iming when swiching a resisive load. IN V IN_H_min V IN_L_max V OUT dv/d OFF 90% ON 70% dv/d ON 30% OFF 10% Swiching imes.vsd Figure 5 Turn ON/OFF (resisive) iming Daa Shee 10 Rev. 1.0,
11 Power Sage 5.3 Inducive Oupu Clamp When swiching OFF inducive loads wih high side swiches, he volage V OUT drops below ground poenial, because he inducance inends o coninue driving he curren. To preven he desrucion of he device due o high volages, here is a volage clamp mechanism implemened ha keeps he negaive oupu volage a a cerain level ( -V DS(AZ) ). Please refers o Figure 6 and Figure 7 for deails. Neverheless, he maximum allowed load inducance is limied. IN LOGIC V DS V BAT I L GND OUT V OUT V IN L, R L Figure 6 Oupu clamp (OUT0 and OUT1) Oupu clamp.vsd IN V OUT - V DS(AZ) peak I L Swiching an inducance.vsd Figure 7 Swiching an inducance Daa Shee 11 Rev. 1.0,
12 Power Sage Maximum Load Inducance During demagneizaion of inducive loads, energy has o be dissipaed in he. This energy can be calculaed wih following equaion: E = L V DS( AZ) R L R L I ln L V DS( AZ) R L Following equaion simplifies under he assumpion of R L = 0Ω. V DS( AZ) + I L E = 1 -- L I V DS( AZ) The energy, which is convered ino hea, is limied by he hermal design of he componen. See Figure 8 for he maximum allowed induciviy ZL (mh) IL (A) Figure 8 Maximum energy dissipaion single pulse, T j,sar = 150 C max eas.vsd Daa Shee 12 Rev. 1.0,
13 Power Sage 5.4 Elecrical Characerisics Power Sage Elecrical Characerisics: Power sage = 12 V, T j = -40 C o +150 C. Typical values are given a T j = 25 C Pos. Parameer Symbol Limi values Uni Condiions Min. Typ. Max ON-sae resisance per channel R DS(ON) 130 mω T j = 25 C, 1) Nominal load curren per channel One channel acive Two channel acive Four channel acive 1) No subjec o producion es, specified by design 2) Volage is measured by forcing I DS. I L(nom) I L = 2A, V IN = 5V, See Figure T j = 150 C A T A = 85 C 1), T j <150 C Drain o source clamping volage V DS(AZ) = -V OUT V DS(AZ) V I DS = 40mA 2) Oupu leakage curren per channel I L(OFF) 1 5 µa V IN = 0V Slew rae ON 10% o 30% V OUT dv/d ON V/µs R L =12Ω, =12V See Figure Slew rae OFF 70% o 40% V OUT -dv/d OFF V/µs Turn-ON ime o 90% Includes propagaion delay Turn-OFF ime o 10% Includes propagaion delay ON µs OFF µs Daa Shee 13 Rev. 1.0,
14 Proecion Mechanisms 6 Proecion Mechanisms The device provides embedded proecive funcions. Inegraed proecion funcions are designed o preven he desrucion of he IC from faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are designed for neiher coninuous nor repeiive operaion. 6.1 Loss of Ground Proecion In case of loss of he module ground, where he load remains conneced o ground, he device proecs iself by auomaically urning OFF (when i was previously ON) or remains OFF, regardless of he volage applied on IN pins. In ha case, a maximum I (OUTGND) can flow ou of he oupu. 6.2 Undervolage Proecion Below UV_max, he under volage mechanism is me. If he supply volage is below he under volage mechanism, he device is OFF (urns OFF). As soon as he supply volage is above he under volage mechanism, hen he device can be swiched ON and he proecion funcions are operaional. 6.3 Overvolage Proecion There is a clamp mechanism for over volage proecion. To guaranee his mechanism operaes properly in he applicaion, he curren in he zener diode ZD AZ has o be limied by a ground resisor. Figure 9 shows a ypical applicaion o wihsand overvolage issues. In case of supply greaer han (AZ), he power ransisor swiches ON and he volage across logic secion is clamped. As a resul, he inernal ground poenial rises o - (AZ). Due o he ESD zener diodes, he poenial a pins IN and ST 0/1/2/3 rises almos o ha poenial, depending on he impedance of he conneced circuiry. Inegraed resisors are provided a he IN pins o proec he inpu circuiry from excessive curren flow during his condiion bu an exernal resisor mus be provided a he ST0/1/2/3 pins. V ccµc R PU_ST 0/1 IN0 R IN0 V BAT IN1 R IN1 ZD AZ R ST 0/1 ST 0/1 V ccµc ZD ESD R PU_ST 3 LOGIC IN2 IN3 R IN2 R IN3 OUT R L R ST 2/3 ST 2/3 ZD ESD GND R GND Overvolage proecion quad diag shared.vsd Figure 9 Over volage proecion wih exernal componens Daa Shee 14 Rev. 1.0,
15 Proecion Mechanisms In he case he supply volage is in beween of (SC) max and V DS(AZ), he oupu ransisor is sill operaional and follow he inpu. If a leas one channel is in ON sae, parameers are no longer warraned and lifeime is reduced compared o normal mode. This specially impacs he shor circui robusness, as well as he maximum energy E AS he device can handle. 6.4 Reverse Polariy Proecion In case of reverse polariy, he inrinsic body diode causes power dissipaion. The curren in his inrinsic body diode is limied by he load iself. Addiionally, he curren ino he ground pah and he logical pins has o be limied o he maximum curren described in Chaper 4.1, someimes wih an exernal resisor. Figure 10 shows a ypical applicaion. The R GND resisor is used o limi he curren in he zener proecion of he device. Resisors R IN and R ST are used o limi he curren in he logic of he device and in he ESD proecion sage. The recommended value for R GND is 150Ω, for R ST 0/1 = 15kΩ. In case he over volage is no considered in he applicaion, R GND can be replaced by a Shoky diode. VccµC Micro conroller proecion diodes R PU ST 0/1 IN0 R IN0 V BAT IN1 R IN 1 -VDS(REV) R ST /1 ST 0/1 ZD body OUT0, 1, 2, 3 IL(nom) R L R PU ST 2/3 VccµC ZD ESD IN0 R IN0 IN1 R IN 1 R ST 2/3 ST 2/3 ZD ESD GND R GND Reverse Polariy quad shared diag.vsd Figure 10 Reverse polariy proecion wih exernal componens 6.5 Overload Proecion In case of overload, or shor circui o ground, he offers several proecions mechanisms. Daa Shee 15 Rev. 1.0,
16 Proecion Mechanisms Curren Limiaion A firs sep, he insananeous power in he swich is mainained o a safe level by limiing he curren o he maximum curren allowed in he swich I L(LIM). During his ime, he DMOS emperaure is increasing, which affecs he curren flowing in he DMOS. A hermal shudown, he device urns OFF and cools down. A resar mechanism is used, afer cooling down, he device resars and limis he curren o I L(SCR). Figure 11 shows he behavior of he curren limiaion as a funcion of ime. IN I L I L(LIM) I L(SCr) ST 0/1 curren limiaion wih diag shared.vsd Figure 11 Curren limiaion funcion of he ime Daa Shee 16 Rev. 1.0,
17 Proecion Mechanisms 6.6 Elecrical Characerisics Proecion Funcions Elecrical Characerisics: Proecion = 12 V, T j = -40 C o +150 C. Typical values are given a T j = 25 C Pos. Parameer Symbol Limi values Uni Condiions Loss of ground Oupu leakage curren while GND disconneced Reverse polariy Drain source diode volage during reverse polariy Min. Typ. Max. I OUT(GND) 2 ma = 32V V IN = 0V -V DS(REV) 600 mv I L = - 2A, T j = 150 C V IN = 0V Overvolage Over volage proecion (AZ) V I s = 40mA Overload condiion Load curren limiaion I L(LIM) A T j = -40 C, T j = 25 C, T j = 150 C Repeiive shor circui curren limi I L(SCR) A One channel 1) Two channel 1) parallel Thermal shudown emperaure T jsc 150 C Thermal shudown hyseresis T JT 10 K 1) 1) No subjec o producion es, bu specified by design Daa Shee 17 Rev. 1.0,
18 Diagnosic Mechanism 7 Diagnosic Mechanism For diagnosis purpose, he provides saus pin. 7.1 ST 0/1/2/3 Pin saus pins are an open drain, acive low circui. Figure 12 shows he equivalen circuiry. As long as no hard failure mode occurs (Shor circui o GND / Over emperaure or open load in OFF), he signal is permanenly high, and due o a required exernal pull-up o he logic volage will exhibi a logic high in he applicaion. A suggesed value for he R PU ST01 is 15 kω.. R PU ST 0/1 R PU ST 2/3 V ccµc Channel 0 or 2 Diagnosic Logic ST 0/1 or ST 2/3 R ST 0/1 R ST 2/3 Channel 1 or 3 OR Diagnosic Logic ZD ESD GND ST pin quad shared diag.vsd Figure 12 Saus oupu circuiry 7.2 ST0/1/2/3 Signal in Case of Failures Table 2 gives a quick reference for he logical sae of he ST 0/1/2/3 pins during device operaion. Table 2 ST 0/1 2/3 ruh able Device operaion IN0/2 IN1/3 OUT0/2 OUT1/3 ST 0/1 ST2/3 Normal operaion L L L L H L H L H H L H L H H H H Open Load channel 0/2 L X > V (OL) X L 1) 1) L if poenial a he oupu exceeds he Openload deecion volage H X H X H Open Load channel 1/3 X L X > V (OL) L 1) X H X H H Over emperaure boh channel L L L L H X H X L L H X L X L Over emp channel 0/2 L X L X H H X L X L Over emp channel 1/3 X L X L H X H X L L Daa Shee 18 Rev. 1.0,
19 Diagnosic Mechanism Diagnosic in Open Load, Channel OFF For open load diagnosis in OFF-sae, an exernal oupu pull-up resisor (R OL ) is recommended. For calculaion of he pull-up resisor value, he leakage currens and he open load hreshold volage V OL(OFF) has o be aken ino accoun. Figure 13 gives a skech of he siuaion and Figure 14 shows he ypical iming diagram. I leakage defines he leakage curren in he complee sysem, including I L(OFF) (see Chaper 5.4) and exernal leakages e.g. due o humidiy, corrosion, ec... in he applicaion. To reduce he sand-by curren of he sysem, an open load resisor swich S OL is recommended. If he channel is OFF, he oupu is no longer pulled down by he load and V OUT volage rises o nearly. This is recognized by he device as open load. The volage hreshold is given by V OL(OFF). In ha case, he ST 0/1 signal is swiched o a logical low T01(L). V ba S OL R OL OUT OL comp. I LOFF I leakage GND V OL(OFF) R GND R leakage Figure 13 Open load deecion in OFF elecrical equivalen circui Open Load in OFF.vsd IN V OUT V (OL) I L ST 0/1 or ST 2/3 T(HIGH) T(LOW) Diagnosic In Open load quad shared diag.vsd Figure 14 ST 0/1 in open load condiion Daa Shee 19 Rev. 1.0,
20 Diagnosic Mechanism ST 0/1 Signal in case of Over Temperaure In case of over emperaure, he juncion emperaure reaches he hermal shudown emperaure T jsc. In ha case, he ST 0/1 signal is oggling beween T01(L) and T01(H). Figure 15 gives a skech of he siuaion. IN V OUT ST 0/1 T J T JSC T JSC Figure 15 Sense signal in overemperaure condiion Diagnosic In Overload shared oggling.vsd. Daa Shee 20 Rev. 1.0,
21 Diagnosic Mechanism 7.3 Elecrical Characerisics Diagnosic Funcions Elecrical Characerisics: Diagnosics = 12 V, T j = -40 C o +150 C. Typical values are given a T j = 25 C Pos. Parameer Symbol Limi values Uni Condiions Min. Typ. Max. Load condiion hreshold for diagnosic Open Load deecion volage V OL(OFF) V ST 0/1 or ST 2/3 pin Saus oupu (open drain) High level; Zener limi volage Saus oupu (open drain) Low level Diagnosic iming Saus change afer posiive inpu slope wih open load Saus change afer posiive inpu slope wih overload Saus change afer negaive inpu slope wih open load Saus change afer negaive inpu slope wih overemperaure T (HIGH) 5.4 V I ST = +1.6mA 1), Zener Limi volage T (LOW) 0.6 V I ST = +1.6mA 1) dst(on_ol) µs 2) dst(on_ovl) 30 µs 2) dst(off_ol) 500 µs dst(off) 20 µs 2) 1) If ground resisor R GND is used, he volage drop across his resisor has o be added 2) No subjec o producion es, specified by design Daa Shee 21 Rev. 1.0,
22 Inpu Pins 8 Inpu Pins 8.1 Inpu Circuiry The inpu circuiry is CMOS compaible. The concep of he Inpu pin is o reac o volage ransiion and no o volage hreshold. Wih he Schmid rigger, i is impossible o have he device in an un-defined sae, if he volage on he inpu pin is slowly increasing or decreasing. The oupu is eiher OFF or ON bu canno be in an linear or undefined sae. The inpu circuiry is compaible wih PWM applicaions. Figure 16 shows he elecrical equivalen inpu circuiry. The pull down curren source ensures he channel is OFF wih a floaing inpu. IN R I To driver s logic I I ESD Inpu circuiry.vsd Figure 16 Inpu pin circuiry 8.2 Elecrical Characerisics Elecrical Characerisics: Diagnosics = 12 V, T j = -40 C o +150 C, all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Typical values are given a T j = 25 C Pos. Parameer Symbol Limi values Uni Condiions Min. Typ. Max. INpu pins characerisics Low level inpu volage V IN(L) 1 V 1) High level inpu volage V IN(H) 2.5 V 1) Inpu volage hyseresis V IN(HYS) 0.2 V 2) Low level inpu curren I IN(L) 5 20 µa V IN = 0.4V High level inpu curren I IN(H) µa V IN = 5V Inpu resisance R I kω See Figure 16 1) If ground resisor R GND is used, he volage drop across his resisor has o be added 2) No subjec o producion es, specified by design Daa Shee 22 Rev. 1.0,
23 Applicaion Informaion 9 Applicaion Informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. V DD V DD V BAT Vdd OUT OUT IN0 IN1 V s OUT0 OUT1 IN ST0/1 Microconroller (e.g. XC22xx) V DD OUT OUT IN IN2 IN3 ST2/3 OUT2 OUT3 GND GND Figure 17 Applicaion diagram wih Noe: This is a very simplified example of an applicaion circui. The funcion mus be verified in he real applicaion. 9.1 Furher Applicaion Informaion For furher informaion you may visi hp:// Daa Shee 23 Rev. 1.0,
24 Package Oulines 10 Package Oulines 0.35 x max 1) max ) x ± GPS05094 Index Marking ) 1) Does no include plasic or meal prorusions of 0.15 max per side 2) Does no include dambar prorusion of 0.05 max per side Figure 18 PG-DSO (Plasic Dual Small Ouline Package) Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pbfree finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). Daa Shee 24 Rev. 1.0,
25 Revision Hisory 11 Revision Hisory Version Dae Changes Creaion of he daa shee Daa Shee 25 Rev. 1.0,
26 Ediion Published by Infineon Technologies AG Munich, Germany 2008 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.
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More informationDisribued by: www.jameco.com -800-83-44 The conen and copyrighs of he aached maerial are he propery of is owner. Preferred Device Schoky Barrier Diodes These Schoky barrier diodes are designed for high
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